JPS62149245A - Duplex system for electronic exchange - Google Patents

Abstract

PURPOSE:To prevent system-down by switching the 1st and 2nd common buses and connecting it to the 3rd common bus if a fault takes place in any function equipment in a group so as to connect the entire other group of the 1st board group to the 2nd board group. CONSTITUTION:The 1st kind board groups 141, 142 mounted with a main CPU, a local CPU, a common memory and a time switch 4 whose fault relates directly to the system-down of an electronic exchange are duplicated in various function equipment provided in a common shelf. The 2nd kind of board group 143 not relating directly to the system-down is not duplicated. The 1st common bus 151 is connected to the 3rd common bus 153 via a switch group 154 and when the function equipment on the board group 141 is in the operating state and a fault takes place therein, the switch group 154 is all turned off, the 2nd common bus 152 is connected to the 3rd common bus 153, the board group 154 is operative instead to cope with the occurrence of the fault.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an electronic exchange, and particularly to a redundancy system for dealing with the occurrence of a failure.

(Prior Art) Telephone exchanges are required to have a high level of reliability, so various duplex systems have been proposed to deal with failures. Conventional duplication methods include, for example, as shown in Figure 19, a method in which the processor (CPLJ) and memory are duplicated, all combinations of processors and memory are prepared, and the combinations are switched when a failure occurs. As shown in FIG. 20, there is an N+1 method in which when a failure occurs in any one of N processors with a specific function, the system is switched to an extra processor. Of course, in addition to functional devices such as processors and memories, the power supplies that supply power to these devices are also duplicated.

However, all of these conventional duplexing systems require complicated hardware to control bus switching when a failure occurs. Furthermore, each of the duplicated power supplies must have an extremely large capacity to supply power to all of the duplicated functional devices such as processors and memories.

(Problems to be Solved by the Invention) As described above, in the conventional duplex system, the hardware is complicated and the power supply capacity is also increased, resulting in a problem that the device becomes larger and more expensive.

The present invention has been made to solve these problems, and an object of the present invention is to provide a redundant system for electronic exchanges that can cope with the occurrence of failures with a simple configuration and that also reduces power supply capacity.

[Structure of the Invention] (Means for Solving the Problems) In the present invention, when a failure occurs, one of the plurality of boards on which various functional devices are mounted together with the power supply in the shelf is activated. Only the first type of board group, which is equipped with functional devices such as processors, memory, and functional devices such as time switches for converting time-division time slots, which are directly involved in system downtime, is duplicated, and each of the duplicated groups are connected to first and second common buses, respectively. On the other hand, the second type of board group, which is equipped with functional devices such as processors that handle application services such as call management, which are not directly involved in system down of the electronic exchange even if a failure occurs, is not duplicated; Either one of the two common buses is selectively connected to a third common bus. The power supplies are duplicated, and each power supply individually supplies power to the duplicated group of type 1 boards, and shares power to the group of type 2 boards. is connected to. The roughly duplicated first type board group is connected to the third common bus via one of the first and second common buses, and when a failure occurs in at least one of the groups, The other group is connected to a third common bus via the other of the first and second common buses.

(Function) When a failure occurs in one of the functional devices in one of the first type board groups connected to the second type board group, the first and second common buses are switched. By being connected to the third common bus, the entire other group of the first boards is connected to the second board group instead of the entire one group, thereby avoiding a system down. In this case, the means for controlling bus switching when a failure occurs is simply switching the connections between the first and second common buses and the third common bus, which is very simple and requires simple hardware. It's over.

In addition, each redundant power supply has a redundant first power supply.
It is sufficient to have the capacity to supply power to one group of the board groups and the functional devices in the second board group, and the capacity is smaller than that required when power is supplied to all the duplicated devices.

(Embodiment) FIG. 1 is a schematic configuration diagram of an electronic exchange according to an embodiment of the present invention, in which a common control shelf 1 and a plurality of line/trunk shelves 2a to 2n are stacked as shown in FIG. It has a structure.

The common control shelf 1 includes a main CPU (Mcpu) card 11 that handles exchange processing, maintenance, etc., and an application CPIJ (acpu) that handles various applications such as call management, messaging, and directories.
) card 12, the main CPU card 11, application CPU card 12, and line/trunk (L/T) card 21, and a local CPU (
A card (card-shaped circuit device) that constitutes a common control unit such as the Lcpu ) card 13 and the time switch (TSW) card 14 that converts time division time slots.
has been implemented. In the present invention, the various cards 11 to 14 in the common control shelf 1 are collectively referred to as a common control card. Further, the processors in each common control card 11 to 14 are connected to a common memory 16 connected to a common bus 15.
They can communicate with each other via.

On the other hand, inside the line/trunk shelves 2a to 2n, there are line/trunk shelves to which subscriber terminals such as telephones and data terminals are connected.
Trunk (L/T) cards 21 are installed according to the number of lines. The connection between the common control shelf 1 and the line/trunk shelves 2a to 2n includes a data highway for transmission from the local CPU card 13 to the line/trunk card 21 and a data highway for reception from the line/trunk card 21 to the local CPU card 13. A control highway 3 for serial transmission and a PCM highway 4 for exchanging PCM time slots are connected between the time switch card 14 and the line/trunk card 21.

Next, each part of FIG. 1 will be explained in detail.

FIG. 3 shows the internal configuration of the line/trunk card 21, particularly the line/trunk card connected to the digital telephone 31. As shown in FIG. In FIG. 3, a digital telephone LS I (DTLS I) 32 is a digital telephone 1.
131 and a boat controller (PC) 33 consisting of a CPU that controls line/trunk cards and telephones and office lines connected thereto. In addition, an interface LSI (I
The LSI 34 is an LSI that controls communication between the boat controller 33 and the local CPL 113 (FIG. 1) in the common control shelf 1, and operates in slave mode as described later.

FIG. 4 shows the internal configuration of the local CPU card 13 within the common control shelf 1. In FIG. 4, an interface LSI (ILSI) 41 has the same configuration as the interface LSI 34 in FIG. 3, but has a different mode setting input from the outside, and operates in a mask mode as described later. Local memory 42 is 〇-Cal C
The buffer 45 is used to store programs and data for operating the PU (Lcpu) 43, and the buffer 45 is used to connect and disconnect the common bus 15 and the local bus 46 in the local CPU card 13. When a certain local CPU 43 accesses the common bus 15, when the decoder 44 detects an address assigned to the common memory 71 (described later), the buffer 45 is turned on to connect the common bus 15 and the local bus 46. In addition,
Different addresses are assigned to the local memory 42 and the common memory 71.

Figure 5 shows the main CPU card 1 in the common control shelf 1.
The internal configuration of 1 is shown. As shown in the figure, the main CPU card 11 has almost the same configuration as the local CPU card 13 shown in FIG. 4, and the local memory 51. Main CPt
J (Mcpu) 52. Decoder 53. Buff? 5
4 and a local bus 55. However, the main CP
Since the U card 11 is not connected to the control highway 3, it does not include an interface LSI.

Although not shown, the application CPU card 12 in the common control shelf 1 also has the same configuration as the main CPU card 11 shown in FIG.

FIG. 6 shows the internal configuration of the time switch card 14 in the common control shelf 1, which includes a time switch controller and time switch 61, a decoder 62, and a buffer 63. Time switch card 14 is the main CP
It is accessed only by U52,
Specifically, the decoder 62 monitors whether or not the address on the common bus 15 matches the address for time switch control, and only when they match, turns on the buffer 63 and connects the time switch controller and time switch 61 to the common bus. Connect to 15.

FIG. 7 shows the common memory card 16 in the common control shelf 1.
It has an internal configuration including a common memory 71, a decoder 72, and a buffer 73, and the method of accessing the common memory 71 is the same as the access method described above for the time switch card 14 shown in FIG.

Next, referring to FIG. 8, the processors in the common control card in the common control shelf 1, for example, the local CPU 43 in the local CPU card 13 shown in FIG. 4, and the line/trunk card 21 shown in FIG. The communication method with the processor (boat controller 33) inside the boat will be explained.

As described above, communication between processors in different shelves is performed by serial transmission under interrupt control.

In FIG. 8, the control highway 3 has a data highway (data input/output line), a frame synchronization signal transmission line, and a data highway cross transmission line,
The M highway 4 has a transmission line for a PCM highway clock and a transmission line for a PCM highway frame synchronization signal.

A clock generator 47 in the local CPU card 13 sends a data highway clock to the control highway 3. On the other hand, the line corresponding section 36 in the line/trunk card 21 includes a CODEC, 5LIC, and the like.

In this embodiment, the interface LSI has two modes depending on the mode setting input: a mask mode that has the function of transmitting data in a time slot that is previously assigned to itself in synchronization with the time slot change point, and a The device used is configured to be able to switch between a slave mode and a slave mode, which has a function of transmitting data only at a time slot address obtained by a slot designation address.

Interface 181 in local CPU card 13
41 operates in mask mode and is inserted between the local CPU and the control highway 3. Data is sent from the interface LSI 41 to the control highway 3 in synchronization with the time slot change point. Furthermore, when receiving data from the interface LSI 34 in the line/trunk card 21,
When the header is detected, it is received and the local CPU
43 as a reception request.

Interface LS in line/trunk card 21
I34 is a boat controller 33 that operates in slave mode and controls input/output of the control highway 3, PCM highway 4, and each port in the card 21.
Connect with. Sending data from this interface LS134 to the control highway 3 is possible only in the time slot designated by the time slot designation address from the outside. In addition, when receiving the interface LSI 34, the data is received via the control highway 3 after detecting the header, and the received data is valid only when the address of the received data matches the time slot specified address from the outside. Based on the judgment, an interrupt request as a reception request is generated to the boat controller 33.

When the boat controller 33 receives an interrupt request, it reads the received data from the reception register in the interface LSI 34 and controls the line/trunk card 21 in accordance with the data. When sending data to the line correspondence section 36, the boat controller 33 writes control data to the line correspondence section control section in the interface LSI 34, and then the interface LSI 34 sends the data to the line correspondence section 3.
The control data is sent to 6.

The status of the line support section 36 or data from subscriber terminals such as the digital telephone 31 are transmitted to the interface LS.
It is periodically fetched into the I10 register of the line correspondence section control section in I34. By periodically reading the data in the I10 register, the boat controller 33 detects changes in the state of the line corresponding section 36 or changes the state of the local CPU 43.
control data for is written to the transmission register in the interface LSI 34. After this, interface L
The SI 34 transfers the contents of the transmission register to the data highway (
data output line).

Next, a communication system between the processors in the common control shelf 1, that is, between the processors provided in the common control cards, which is a feature of the present invention, will be explained. For inter-processor communication within the common control shelf 1, each local CPtJ
43 processes the data related to the status of subscriber terminals collected from the line/trunk card 21 under its control and the data from the subscriber terminals to a predetermined level, and then the main CPU
52 or application CPU, and main CPU 52 and application C.
There is data transmission for transmitting terminal control data obtained through exchange processing by each PU to the local CPU 43 side.

As described above, communication between processors within the same shelf is achieved by connecting a common memory 16 that can be commonly accessed by each processor to the common bus 15, writing data to be transmitted to this common memory 16, and This is done by reading the data to be received from this common memory 16.

The method of connecting a common memory to a common bus and transmitting data between arbitrary processors via the common memory is well known, for example, as seen in the control according to IEE 796. According to this method, a processor that requires access to a common memory issues a control signal on a common bus, and data transmission is performed by occupying the common bus during the access period. In that case, if accesses by multiple processors conflict, processing is performed based on a predetermined priority order.

In this embodiment, each local CPU 43 writes the status or dial information data into the common memory 16 each time a status change occurs on the subscriber terminal side and each time dial information is sent from the subscriber terminal. Main CP
By periodically polling the contents of the common memory 16, U52 learns of changes in the status of each subscriber terminal and performs processing accordingly. For example, when a call is initiated from a subscriber terminal, it is detected and the call is processed. In this series of call processing routines, data originally stored in the common memory 16 or from the subscriber terminal to the local CP
When the data stored in the common memory 16 via U43 is needed, the common memory 16 is accessed and the data is read and processed. If the control data controlling the subscriber terminal side changes as a result of this processing, the control data is written into the common memory 16.

On the other hand, the local CPU 43 also checks the contents of the common memory 16 in order to determine whether or not a change has occurred in the control data of the subscriber terminal, and to detect the contents of the control data if a change has occurred. Polling regularly.

In this way, each processor (main CPU 52, local CPU 43, etc.) writes data to be transmitted into the common memory 16, and polls the contents of the common memory 16 periodically or whenever necessary to read data to be received. This allows communication between these processors. In this way, there is a difference in the functional level between the local CPU 43, the main CPU 52, and the application CPU, and even though data is collected from the local CPU 43 side to the main CPLJ 52 and the application CPU, the main CPU 52, the application CPU, etc. can execute its own processing program (for example, exchange processing program) without interruption, improving processing efficiency.

Also, local CPU (Lcpu) 43. Main C
PU (Mcpu) and application CPU (
Act)u) is connected via the common memory 16 on the common bus 15, so that 1ylcpu -1c
pu, l cpu-A cpu, M cpu-A
Since communication between CPUs can be performed flexibly, it is possible to provide more advanced services while maintaining real-time performance.

Further, as shown in FIG. 9, the local CPU 43 located between the serial transmission area and the parallel transmission area moves from the physical level, which is the processing level of the line/trunk card 21, to the logical level, which is the processing level of the local CPtJ 43. By performing this conversion, the main CPU 52 can handle input and output at the highest level of abstraction. In addition, Figure 9 crawl-in/trunk card 21. Local C
Each function of PU43 and main CPU52,
A specific example of communication data between these processors is shown. In this way, the local CPU 43 can control command data transmission between subscriber terminals and trunks, and there is no need for the main CPtJ 52 to manage command data.
There are advantages in that the load on the computer 52 is reduced, changes, additions, etc. are facilitated, expandability is improved, and productivity is also increased.

Next, the internal configuration of the interface LSI (34, 41, etc.) will be explained with reference to FIG. As mentioned above, the interface LSI is the control highway 3
A mask mode that has the function of sending data to the internal data highway in synchronization with the time slot change point, and an address that matches the address given by the time slot specified address from the outside. It is configured so that it can be switched to slave mode, which is possible only in the time slots of . A control unit that switches the master/slave mode based on a mode setting input is located in the data highway transmitting/receiving unit 101.

In FIG. 10, a data highway transmitting/receiving section 101 operates by a frame synchronization signal DHFS and a data highway clock DHCLK, and a data highway transmitting register 102 and a data highway transmitting register 10
3 through data input line DHIN and data output line D
Sends and receives data to and from HOUT. in this case,
As described above, the timing of transmission and reception differs depending on the mode. That is, in the mask mode, the data in the transmission register 102 is sent out in synchronization with the change point of the time slot, and in the case of reception, the data is received after header detection and stored in the reception register 103. In slave mode, the data in the transmission register 102 is transmitted only in the time slot whose address matches the time slot designation address from the outside, and when receiving data, the data is received after detecting the header, and the data is transmitted according to the time slot designation from the outside. Data is stored in the reception register 103 only when the address matches the address in the received data.

The CPU interface control unit 104 decodes address data from the data bus, and
Send data to each block within SI.

The line correspondence unit control unit 105 has an input register 106. It has an output register 107 and an input/output designation register 108 for designating an input/output mode, and is connected to the line correspondence section 36 (FIG. 8).

The PCM time slot control unit 109 counts the number of time slots using the PCM frame synchronization PCMFS and the PCM clock PCMCLK, and controls the boat controller 3.
3, the address is compared with the PCM time slot address set in the PCM time slot designation register 110, and when they match, control is performed to provide frame synchronization to the GODEC.

In the electronic exchange of this embodiment, when transmitting the same data from the local CPU 43 to a plurality of boat controllers 33, the slave mode interface LSI 34 to which those boat controllers 33 are connected
A common group address is given to each group, and data is transmitted using this group address. This group address has meaning as a collection of addresses of multiple interface LSIs 34, and each interface LSI
It is registered in advance in SI34.

Note that there are two methods for transmitting the same data from the local CPU 43 to multiple boat controllers 33: (1) sending normal calls to each boat controller in sequence and transmitting the same data; (2) transmitting the same data to each boat controller in sequence; and (2) transmitting the same data to each boat controller 33 as described above. Multiple interface LSI34
A possible method is to add transmission data to a representative group address and transmit the data. Although method (2) is simple, it requires sequentially transmitting addresses and transmission data to each boat controller individually. On the other hand, ■
In the method described above, transmission can be performed between the local CPU 43 and a plurality of boat controllers 33 at once, so the time required for transmission is shortened, and the local CPU 43
The load on J43 is also reduced. - Next, the transmission signal format in this embodiment is
This will be explained with reference to the figures. As shown in the figure, one frame is formed by a header, address, control data, and information data. Address is a single boat controller 33
The addresses are divided into individual addresses for transmitting data individually to multiple boat controllers 33, broadcast addresses for transmitting the same data to multiple boat controllers 33, and simultaneous broadcast addresses for transmitting the same data to all boat controllers 33. It will be done. Information (referred to as an identifier) indicating the distinction between an individual address, a broadcast address, and a simultaneous broadcast address is the upper part (MSB side) in the address format shown in the lower part of Figure 11.
2 bits are used.

In the case of an individual address, the upper 2-bit identifier indicating the distinction of this address is followed by a single interface L.
An SI address (ILSI address) is added, and in the case of broadcasting, a group address indicating an arbitrarily designated group is added.

Now, a single group address (#
Assuming that A) represents the address information of the plurality of interface LSIs, when transmitting the same data from the local CPLJ 43 to the interface LSIs 34 connected to a plurality of boat controllers 33, the address information shown in FIG. As shown above, set the identifier “10°” in the upper 2 bits of the address format, and continue with #1.
#A may be added as a representative address of ~#n.

As a result, data from the local CPU 43 is sent to the interface LSI 34 connected to the plurality of boat controllers 33 by - times of transmission operations.

The interface LSI 34 to which the data from the local CPLJ 43 has been sent in this way extracts a group address from the data received via the data highway and compares it with a group address registered in advance. As a result of this comparison, when both addresses match, the information data in the transmission data is received. In addition, in FIG. 12, group addresses #A and #B correspond to the in/trunk card 2 in which the interface LSI 34 is installed.
1 indicates a card connected to a standard telephone (STT). This line/trunk card can receive transmitted data from local CPU 43, but other line/trunk cards cannot receive the same data.

The thirteenth factor shows the configuration of the address processing circuit provided in the line/trunk 21 for performing the above-mentioned processing, and the upper two bits (li identifier) of the received address are E, - of the selector 131. 8 terminals (control input terminals)
supplied to The A and B terminals (data input terminals) of the selector 131 are supplied with the group address stored in the memory 132 in the line/trunk 21 and the LSI address assigned to the individual interface LSI 34, respectively. From the selector 131, (E, S)-(0
, O), the LSI address is also (E.

When S)=(1,0), each group address is output and supplied to the first input terminal of the comparator 133. Address information following the upper two bits of the received address is supplied to the second input terminal of the comparator 133, and when the values at the first and second input terminals match, the output of the comparator 133 becomes "1". On the other hand, the information on the upper two bits of the received address is further input to the two-person gate 134, and it is determined whether the upper two bits are "11", that is, whether the received address is a broadcast address. The output of the AND gate 134 and the output of the comparator 133 are input to a two-man OR gate 135. The “1” output of the OR gate 135 becomes a reception request to the port controller 33. That is, when the receiving address is an individual address (LSI address) corresponding to the received interface LSI, when it is a broadcast address (group address) including the received interface LSI, and when it is a -broadcast address. A request is issued to receive the information data following the address.

Such a configuration is effective when storing programs in each boat, such as when starting up the system when the system goes down. That is, since the time required to load programs, etc. is determined only by the number of programs to be loaded, regardless of the number of boats, the time required to start up the system is significantly reduced.

Next, the duplication method in this embodiment will be explained.

This duplication is applied to the common control shelf 1. 14th
The figures are diagrams for explaining the duplex structure within the common control shelf 1, with (a) being a front view and (b) being a rear view.

The left and right sides of FIG. 14 (a) and (b) are reversed.

As shown in FIG. 14, among the various functional devices provided in the common control shelf 1, the main CPU (Mcpu
), O-cal CPU (Lcpu).

The first type of board group on which the common memory and time switch (TSW) are mounted is duplicated as shown at 141 and 142 and placed on the left and right sides of the shelf 1.

Further, the second type board group 143 on which application CPUs (ACpu) which are not directly involved in system down even if a failure occurs is mounted is not duplicated and is placed in the center of the shelf 1. The power supplies for supplying power to these functional devices are also duplicated as shown at 144 and 145, and are placed at both left and right ends of the shelf 1.

The first type of substrate groups 141 and 142 are connected to first and second common buses 151 and 152, respectively, and the second type of substrate group 143 is connected to a third common bus 153.

These common buses 141 to 143 and power lines 156 and 15
7 and ground wire 158 are patterned on the motherboard of shelf 1.

Between the first and second common buses 151, 152 and the third common bus 153, there is a switch group 1 for bus switching.
54,155 is inserted. FIG. 15 shows details of the switch group 154, in which two directional gates G1. It is constructed using G2 as a unit switch and is controlled by switch control lines 81 and 82. Gate Q1. Q2 is turned on when the corresponding switch control line 81.32 becomes "H" level. Therefore, for example, 81 = "H", 82 - "L"
II, the signal is transferred from the common bus 153 to the common bus 15.
It is transmitted only to one side.

Gate G1. When G2 is off, the output is oven.

It is assumed that the switch group 155 is configured similarly.

When one of the first type board groups 141 and 142 is in an operating state, the switch control line S1. S2 becomes “H” as necessary
or set to “L” level, and the first common bus 151
and a third common bus 153 are connected. At this time, all switch control lines connected to the switch group 155 are at the "L II level."

Conversely, the other one 142 of the first type substrate group 141, 142
is in the operating state, the switch control lines S1 and 82 connected to the switch group 155 are appropriately set to "H" by the R/W (read/write) signal, chip select signal, etc.
'' or ``L II level, and the second common bus 152 and third common bus 153 are connected, and at that time, all the switch control lines connected to the switch group 154 are at the ``L'' level.

In this way, the first and second common buses 151, 152 are selectively connected to the third common bus 153, thereby selectively connecting the first board group 141, 142 and the second board group 143. Connected.

Now, the first common bus 151 is connected to the third common bus 153 via the switch group 154, and the first board group 141
, 142 is in an operating state, if a fault occurs in any of the functional devices on this board group 141, this fault is detected as follows, and the fault is detected based on it. The switch group 154 is all turned off, the second common bus 152 is connected to the third common bus 153, and the board group 142 becomes operational instead of the board group 142 to deal with the occurrence of a failure.

As a failure detection means for the main CPU 52, a watchdog timer 161 may be used as shown in FIG. The watchdog timer 161 includes a counter 162 and a clock generator 16 that supplies a clock to the counter 162.
3, and the counter 162 is the main CPLI 52.
It is cleared at regular intervals by the program executed by the program. For example, assume that the clock period is 10flSeC, and when the counter 162 counts 10 consecutive clocks, the McPU fault occurrence notification line 164 is set to the "'H" level to notify the occurrence of a fault. If a problem occurs such as the program running out of control, 10m5ecx
10 = Since a clear signal for the counter 162 cannot be generated within 100m5ec, the occurrence of a fault is detected by the counter 162, and the detection result is MCI)tl fault notification 1
It will be released on 164th. In addition, 0-CalCPLJ
Detection of the occurrence of a failure in No. 43 can be similarly performed using a watchdog timer.

On the other hand, time switch (TSW) failure detection is performed by selecting an unused time slot in the main CPU 52, sending a test pattern to the PCM highway 4 in that time slot, and returning the test pattern via the PCM highway 4. This can be done by comparing the test pattern with the sent test pattern. That is, if both test patterns match, it is determined to be normal, and if they do not match, it is determined to be abnormal. At this time, the looping of the test pattern on the PCM highway 4 is performed by providing a looping switch 170 on the time switch card 14 as shown in FIG. It is only necessary to close only one loop to form a loop.

Furthermore, failure detection in the common memory 71 can be performed by providing the common memory 71 itself with the function, for example, 1 byte/
In the case of an 8-bit configuration, 13 bits are used for fault detection, and in the case of a 16-bit configuration, 22 bits are used for fault detection.
This may be done using a known error detection LSI. Incidentally, failure detection of the time switch and the common memory 71 is performed by the register 165 in FIG.
The detection results are output to the W fault notification line 166 and the memory fault detection line 167, respectively.

The various failure detection signals obtained in this way are synthesized by an OR circuit 180 as shown in FIG. input to the interrupt line of the main CPU 52 on another board group 142 that is not
Start the program. In this case, by simultaneously turning off all the switch groups 154 and turning on the switch groups 155 appropriately, the first common bus 151 and the third common bus 153 are separated, and the second common bus 15
2 and the third common bus 153 are connected as described above.

According to the duplication method as described above, the switch group 154.
155 to the first and second common bus 151°15
The occurrence of a failure can be dealt with simply by switching the connections between the second and third common buses 153 all at once, and the hardware for switching control becomes extremely simple.

On the other hand, the redundant power supply 144.145 is connected to the power supply line 156.
The first substrate group 141, 142 is connected to the first substrate group 141, 142 through
A second board group 14 which is connected to each of
3, and the redundant first board group 141
. . Therefore, compared to the prior art in which each of the duplicated power supplies supplies power to all of the duplicated functional devices and non-duplicated functional devices, the power capacity can be reduced. Note that the power lines 156 and 157 are
When connected directly to the board group 143, the power supplies 151, 152
Current flows from the side with higher potential to the side with lower potential.

The diodes 159 and 160 are for preventing such a backflow phenomenon.

[Effects of the Invention] The redundant system for electronic exchanges according to the present invention can deal with the occurrence of failures using simple hardware.
At the same time, there is an advantage that the capacity of each of the duplicated power supplies can be kept to a minimum, and this can contribute to downsizing and lowering the cost of switching equipment.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of an electronic exchange according to an embodiment of the present invention, FIG. 2 is a diagram showing a stacked shelf structure of the electronic exchange, and FIG. 3 is a diagram showing a line/trunk card in the same embodiment. Figure 4 is a diagram showing the internal configuration of the 〇-Cal CPtJ card in the same embodiment, Figure 5 is a diagram showing the internal configuration of the main CPU card in the same embodiment, and Figure 6 is a diagram showing the internal configuration of the main CPU card in the same embodiment. FIG. 7 is a diagram showing the internal configuration of the time switch card in the example, FIG. 7 is a diagram showing the internal configuration of the common memory card in the example, and FIG. 8 is a diagram showing the local CPU card and line /
Diagram for explaining the communication method in the trunk card, No. 9
The figure shows a specific example of the distribution of functions between the line/trunk card, the local CPU, and the main CPU, and the communication data between them. Figure 13 shows a transmission signal format for explaining the data transmission method from the local CPU to the port controller in the line/trunk card in the embodiment; the 12th factor is a conceptual diagram for explaining the data transmission method; 14(a) and 14(b) are diagrams showing the configuration of the address receiving circuit in the line/trunk card used to implement the same data transmission method, and FIGS. 15 is a diagram showing details of the bus switching switch group in FIG. 14, and FIGS. 16 to 18 are fault detection accompanying the duplex system. A diagram to explain the means,
FIGS. 19 and 20 are diagrams for explaining the conventional duplex system. 1...Common control shelf, 2a-2n...Line/
Trunk shelf, 3...control highway,
4... PCM highway, 11... Main CPU card, 12... Application CPU card, 13
...Local CPU card, 14...Time switch card, 15...Common bus, 16...Common memory, 21...Line/trunk card, 33...Boat controller, 34.41...・Interface LSI, 43... Local CPLI, 52... Main CPLI, 71... Common memory, 141, 142.
...First board group, 143...Second board group, 144
, 145...N source, 151-153...first to third
common bus, 154, 155... bus switching switch group, 159, 160... backflow prevention diode, 1
61...Watchdog timer. Applicant's agent Patent attorney Takehiko Suzue

Claims (3)

[Claims] (1) In an electronic exchange having a shelf equipped with a plurality of circuit boards provided with functional devices and a power source for supplying power to the circuit boards, a functional device that is directly involved in system down of the electronic exchange when a failure occurs among the circuit boards. The first type of board group equipped with is duplicated, and each of the duplicated groups is connected to the first and second common buses, so that even if a failure occurs, it will not be directly involved in the system down of the electronic exchange. The second type of board group provided with functional devices that do not have the same function is not duplexed and is connected to a third common bus to which either the first or second common bus is selectively connected, and the power supply is duplexed. At the same time, each power supply is wired in such a way that it individually supplies power to the redundant type 1 board group, and shares the power supply to the second type board group, and further redundancy occurs. When a failure occurs in at least one of the first type board groups connected to the third common bus via one of the first and second common buses,
A duplex system for electronic exchanges, characterized in that the other group is connected to a third common bus via the other of the first and second common buses. (2) The first board group is a functional device that is directly involved in system down of the electronic exchange when a failure occurs, and is equipped with a processor that controls exchange processing, memory, and a time switch for converting time division time slots. A patent claim characterized in that the second board group is provided with a processor that manages application services such as call management as a functional device that does not directly contribute to system down of the electronic exchange even if a failure occurs. A redundant system for electronic exchanges as described in item 1. (3) The power supply is connected to one of the first substrate groups and the second substrate group.
2. A redundant system for an electronic exchange according to claim 1, characterized in that the system has a capacity to simultaneously supply power to a group of boards.