JPH01291343A - Memory managing device - Google Patents

Abstract

PURPOSE:To curtail an inter-memory transfer processing at the time of giving and receiving a data train and to decrease a memory activity ratio and a bus activity ratio by providing plural memory mapping circuits for converting an address space of a CPU to an address space of a common data memory. CONSTITUTION:CPU address spaces of a data train to which two processing units 161, 162 execute an access pass through memory mapping circuits 13, 14 of a memory managing device 10, respectively and converted to address spaces of a data memory 11, respectively. As for two data memory address spaces, one is selected by an address selector circuit 12, it becomes an address and an access of read/write of the memory 11 can be executed. In such a way, the data train can be given and received without executing an inter-memory transfer processing between the processing units 161, 162, a memory activity ratio and a bus activity ratio are decreased, and also, a complicated memory management by a software becomes unnecessary.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory management device, and more particularly to a memory management device that manages addresses of data memory connected to a CPU, and manages reading and writing of data. It is.

[Conventional technology]

Generally, in an information processing device, data is transferred between the CPU and the main memory, and data processed by the CPU is stored and data necessary for processing by the CPU is read. FIG. 8 and FIG. 9 are diagrams each showing a process of processing between a plurality of processing units.

When data strings are exchanged within a single CPU or CPU or between multiple CPUs, the following method θ is used.

(i) Receiving data strings between multiple processing units is a passing operation. As shown in FIG. D,at
a:M) Write to 81, then another processing unit (n) 8
3 reads this data string and performs the predetermined processing, and then reads the processed data string (Z, B.

C) to the data memory (Data:N) 81, and then write this data string (N) to another processing unit (n+1) 84.
Z, B, C) are passed. Note that the processing unit here refers to each process of a program executed by the CPU.

(Communication) Operation of changing a shared data string between multiple processing units As shown in FIG.
:M) is processed by the processing unit (n+1) 93 to partially change the data string (Dat
a:M) was copied into the memory of the processing unit (n+1) 93 and rewritten. That is, in the case of FIG. 9, first, the data string (A, B, C) is read out from the memory 91 to the surface processing units 92 and 93 and processed respectively, and only the processing unit 93 reads this data string ( Z, B, C) and stored in the memory within the device.

An example of such memory is "Electronic Communication Handbook JP" published by the Institute of Electronics and Communication Engineers on March 30, 1978.
, 1258.

[Problem to be solved by the invention]

In this way, when data strings are exchanged, data strings are transferred between memories, which increases memory usage and bus usage, and requires software to manage complex memory buffers. I needed it. As a result, the load on the CPU has increased.

An object of the present invention is to solve such conventional problems and to improve inter-memory transfer when sending and receiving data strings when processing is performed across multiple processing units within a single CPU or between multiple CPUs. An object of the present invention is to provide a memory management device capable of reducing processing, reducing memory usage rate and bus usage rate, and reducing complicated memory buffer management to reduce the load on a CPU.

[Means to solve the problem]

In order to achieve the above object, the memory management device of the present invention includes:
A memory management device installed in a data processing system that exchanges data strings between processing units within a CPU, which is independent of the memory connected to the CPU and is used for exchanging data strings. a data memory common to the unit; and a plurality of memory mapping circuits for converting the address space of the CPU into the address space of the data memory;
The present invention is characterized in that it includes an address selector circuit that selects the address output of the memory mapping circuit that is accessing the data memory from among the address outputs from the memory mapping circuit to the data memory. Also, multiple C
A memory management device installed in a data processing system that exchanges data strings between CPUs, which mutually utilizes memories connected to other CPUs, or is provided independently from other CPUs to transfer data strings. A data memory common to the processing units used for transfer and reception, a memory mapping circuit provided for each CPU in order to convert the address space of the CPU into the address space of the data memory, and a memory mapping circuit provided for each CPU, and Another feature of the present invention is that it includes an address selector circuit that selects the address output of the memory mapping circuit that is accessing the data memory from among the address outputs to the data memory.

[For production]

In the present invention, (i) in the case of a single CPU, a common data memory is provided for exchanging data strings between each processing unit independent of the memory within the CPU, and a memory mapping circuit is used for each processing unit. After converting the address space of the CPU and the address space of the data memory for each unit, only one address space is selected by the address selector circuit from among the plurality of address spaces of the data memory converted by the plurality of memory mapping circuits. In addition, (j]) In the case of multiple CPUs, data strings are exchanged between the first processing units of each CPU via the data memory, and the address space of the CPU is stored for each processing unit of each CPU using the memory pin pink circuit. After converting the address space of the data memory, the address selector circuit selects only one of the plurality of address spaces of the data memory converted by the plurality of memory mapping circuits.

〔Example〕

The principles and embodiments of the present invention will be explained in detail below with reference to the drawings.

(i) Transfer operation of data strings between multiple processing units Processing unit n-1 processed under the address space of the CPU
This will be explained by taking as an example a case where a data string is passed from , to processing unit n, and then to processing unit n+1 (
(corresponding to Figure 8).

First, a data string M that processing unit n-1 attempts to output to processing unit n is created in the CPU address space of processing unit n-1. At this time, the CPU address space of the data string M handled by the processing unit n-1 is
A correspondingly provided memory mapping circuit converts it into the address space of the data memory. Therefore, the entire data string M that processing unit n-1 attempts to output to processing unit n will be created in the data memory.

Next, in the processing unit n, the CPU address space of the data string M handled by the processing unit n is converted into the data memory address space by a memory mapping circuit provided corresponding to the processing unit n. Therefore, it becomes possible to read the data string M from the processing unit n.

In this way, data strings can be transferred from processing unit n-1 to processing unit n without any transfer processing between memories.

Next, processing unit n applies processing to data string M, and = 7- Ml and M2 (here, Ml is a change area for M, M
2 is an unaltered area in M), and the data string is passed to the processing unit n+1.

In the processing unit n, the memory mapping circuit provided for the processing unit n converts the CPU address space of the M1 area of the changed area into a newly allocated data string in the data memory, and converts the CPU address space of the M1 area of the changed area into the newly allocated data string of the unchanged area M2 area. The CPU address space of is converted into the address space of the data string in the previous data memory, and this is passed to the processing unit n+1.

In the processing unit n+1, the data string N handled by the processing unit n+1
The CPU address space of is converted into the data memory address space by a memory mapping circuit provided corresponding to the processing unit n+1. Therefore, data string N can be read from processing unit n+1.

As a result, the M1 area in the data string N that is passed to the receiver is
The newly allocated data memory area is used, but for the M2 area, processing unit n to processing unit n+1 is used.
Receipt can be achieved without memory-to-memory transfer processing during the passing process.

(ii) Changing operation of shared data string between multiple processing units Processing unit n and processing unit n+1 have a shared data string M, and the processing unit n+1 side partially rewrites this. (corresponding to the figure).

In the processing unit n, C of the shared data string M handled by the processing unit n
The PU address space is converted into a data memory address space by a memory mapping circuit provided for each processing unit n. Therefore, it becomes possible to read the data string M from the processing unit n.

In the processing unit n+1, the CPU address space of the shared data string M handled by the processing unit n+1 is converted into the data memory address space by a memory mapping circuit provided for the processing unit n+1.

This means that processing unit n and processing unit n+1 share the same data string.

At this time, if processing unit n+1 changes a part of data string M to make it Ml+M2 (Ml is the changed part and M2 is the remaining part of the shared part), a Using a memory mapping circuit, the CPU address space of the modified area M1 is converted to a newly allocated data string in the data memory, and the CPU address space of the remaining M2 of one shared area is converted to the previous data memory. Convert to the address space of the data string in .

As a result, the Ml area uses the newly allocated data memory area, but the remaining M2 area can be shared and used with the processing unit n without the need for inter-memory transfer processing. .

FIG. 1 is a block diagram of a memory management device showing a first embodiment of the present invention, and shows a case where two processing units for sending and receiving data strings exist within a single CPU.

In FIG. 1, 10 is a memory management device of the present invention, and 11 is a memory management device of the present invention.
12 is a data memory; 12 is an address selector circuit; 13.
14 is a memory mapping circuit, 15 is a CPU, 16 is a program/data memory, and 161.162 are processing units (1) and (2) stored in the program/data memory.
), 17 is a data bus, and 18 is an address bus.

The CPU address space of the data strings accessed by the two processing units 161 and 162 is transferred to the address space of the data memory 11 via two memory mappings 13 and 14 provided corresponding to the two processing units. converted. One of the address spaces of the two data memories is selected by the address selector circuit 12, which becomes the address of the data memory 11, and the memory 11 can be accessed for read/write.

Here, it is assumed that the data memory 11 is composed of a dedicated data RAM.

FIG. 2 is a block diagram of the memory mapping time in FIG. 1.

In FIG. 2, 21 is a memory mapping circuit, 22 is a CPU address bus, 23 is a data memory address bus, and 211 is an address conversion table.

For example, address 1-5 from CPU 15 to data string
000H (here, H indicates hexadecimal) is 60 of the physical address at that location according to the address conversion table 211.
Converted to 00H.

FIG. 3 is a block diagram of a memory management device showing a second embodiment of the present invention, and shows a case where there are two processing units that input and output data strings between a plurality of CPUs.

In FIG. 3, 30 is a memory management device of the present invention, 31
32 is a data memory, 32 is an address selector circuit, and 33.
34 is a memory mapping circuit (1).

(2), 35.36 is c p u (1), (2), 37
．． 38 is a program/data memory, 371 and 381 are processing units (1) (2), 39 is a data bus, 4], 4
2 is an address bus.

The address space of the CPU 35 is provided by the memory mapping circuit 3.
3 into the address space of the data memory 31, it is selected by the address selector circuit 32, and the data string in the data memory 31 can be manipulated. C
From the PU 36 side, after the logical address space of the CPU 36 is converted into the address space of the data memory 31 via the memory mapping circuit 34, the address selector circuit 3
2, the data string in the data memory 31 can be manipulated.

Here, the data memory 31 may be composed of a dedicated data RAM, or a part of the main memory of the CPUs 35 and 36 may be used. Furthermore, as shown in FIG. 3, in the case of processing between two CPU processing units, two
It is also possible to use a button RAM.

In addition, in the embodiment, the data memory 31 for sending and receiving data
program/data memory 37. of the CPUs 35, 36.
38 is shown, but for example,
If the frequency of access is not high, it is also possible to share the data memory for receiving and passing data with the program/data memory. In this case, in FIG. 3, the CPU 35 or 3
By adding one of the address buses 41 and 6 (one of 41 and 42) to make it a three-person operation, and switching between the output of the memory mapping circuit 33 and 34 and the address bus 41 or 42 as necessary. realizable.

FIGS. 4 and 5 are diagrams illustrating an operation for receiving and passing data strings between a plurality of processing units.

As shown in FIG. 4, for example, processing units (1) (2) (
In the transfer operation between the three processing units in 3), the address space 6000 of the CPU used by the processing unit (1) is
~6FFF is converted by the memory mapping circuit 42 to 71 (response space 2000 ~ 2FFF) of the data memory. Also, the address space 8 of the CPU of processing unit (2)
000 to 8FFF are assigned to address spaces 2000 to 2FF of the same data memory by the memory mapping circuit 43.
F, and data strings can be input and output between processing units.

As shown in FIG. 5, in the processing unit (2), M in the address space 54 of the CPU used by the processing unit (2)
When changing one area (8000 to 8100), the memory mapping circuit 52 corresponding to the processing unit (2) creates a new data memory space PMI (
4000-40 F F) and make changes. Regarding the M2 area (8100 to 8 FFF) which is an unchanged area, the memory mapping circuit 52 corresponding to the processing unit (2) maps the M2 area to PM2M7C3100 to 2 FFF in the original data memory space 51. Convert to

When passing the data string N consisting of M1+M2 to the processing unit (3), the CPU address space (AOOO-AFFF) 55 of the processing unit (3) is transferred by the memory mapping circuit 53 corresponding to the processing unit (3). PMI area of data memory address space 51 (4000 to 40 F F)
and PM2M7C3100-2FFF), it becomes possible to input and output data strings between processing units.

As is clear from FIGS. 4 and 5, in this embodiment, whether there is a single CPU or multiple = 15 CPUs, input/output is performed between multiple processing units. Data strings have the advantage that they can be exchanged without memory-to-memory transfer processing for unmodified areas.

FIGS. 6 and 7 are explanatory diagrams showing an example of an operation for changing a shared data string between a plurality of processing units. here,
A case is shown in which processing unit (1) and processing unit (2) share data string M.

As shown in FIG. 6, in the processing unit (1), the M area (1000 to IFFF) of the CPU address space 64 is mapped to the PM area (1000 to IFFF) of the data memory space 61 by the memory mapping circuit 62 corresponding to the processing unit (1). 2000~2 F F
F). In addition, in processing unit (2), C
M area of PU address space 65 (3000 to 3FFF)
A memory mapping circuit 63 corresponding to the processing unit (2)
Data memory space 61 (7) PM area (2000
-2F F F) conversion. Therefore, the same data string can be shared and read out.

FIG. 7 shows an example in which only the FF byte of the contents of the CPU address space 75 of the processing unit (2) is rewritten from the lower address. That is, in the processing unit (2), the data N area (3000
~3FFF), the unmodified area (3100~3FFF)
Using the memory mapping circuit 73, the data up to F F) are mapped to (410
0 to 4 FF F). Furthermore, regarding the changed area (3000 to 30 FF) of the CPU address space 75, the memory mapping circuit 73 is used to change the new P M 1 area (60 FF) of the address space 71 of the data memory.
00 to 6OFF), the processing unit (2
) is the CPU 7 space 75 (7) (3000~3
It is possible to use F F F).

As a result, even if a part of the contents of the same data string is changed between multiple processing units and used in each processing unit, the entire contents of the data string must be transferred between memories. This can be achieved by rewriting only the changed area.

In addition, in these embodiments, one memory pine pink circuit is provided for each processing unit, but in order to increase the speed,
A plurality of memory mapping circuits may be provided in each processing unit, and by providing a plurality of memory mapping circuit conversion tables shown in FIG. It is also possible to integrate memory mapping circuitry.

〔Effect of the invention〕

As explained above, according to the present invention, when processing is performed dividedly among a plurality of processing units, that is, each processing unit exists within a single CPU, or
Regardless of whether the data string exists across the processing units, (i) when transferring the data string between the processing units, it is possible to transfer the data string without performing inter-memory transfer processing, and (ii) the processing unit When changing and using a part of a data string shared between devices, this data string can be used without performing inter-memory transfer processing on the unaltered area of the data string. As a result, the memory usage rate and bus usage rate are reduced, and the need for complicated memory management registration by software is eliminated.

[Brief explanation of the drawing]

FIG. 1 shows a first embodiment of the present invention, in which a single CP
A block diagram of a memory management device when a plurality of processing units are required in U, FIG. 2 is a diagram showing an example of the memory mapping circuit in FIG. 1, and FIG. 3 is a diagram showing a second embodiment of the present invention. FIG. 4 and FIG. 5 are diagrams each showing an example of a data string transfer operation between a plurality of processing units; FIGS. 6 and 7 are diagrams showing an example of an operation for changing a shared data string between multiple processing units, and FIGS.
Each figure is a diagram showing a conventional processing process between a plurality of processing units. 10.30: Memory management device, 11.31: Data memory, ], 2,32 Near address selector circuit, 13.14
,21,33,34,4.2,43,52゜53.62
, 63, 72, 73: Memory mapping circuit, 15, 3
5,36: CPU, 16,37゜38 Niprogram/Data memory, 17.39:=19= Data bus, 18,41,42 Near address bus (CP
U address space), 161, 162, 371° 372:
Processing unit, 211 Near address conversion table, 44, 64
, 74: CPU7 dress space for processing unit (1), 45,
54, 65, 75: CPU address space for processing unit (2), 55: CPU address space for processing unit (3), 41
, 51, 61, 71: data memory address space. Patent applicant Nippon Telegraph and Telephone Corporation □ Agent Patent attorney Masatoshi Isomura

Claims (2)

[Claims] (1) A memory management device provided in a data processing system that exchanges data strings between processing units within a CPU, which is independent of the memory connected to the CPU, and
A data memory common to processing units used for sending and receiving data strings, a plurality of memory mapping circuits that convert the address space of the CPU into the address space of the data memory, and an address from the memory mapping circuit to the data memory. A memory management device comprising: an address selector circuit that selects an address output of a memory mapping circuit that is accessing the data memory from among the outputs. (2) A memory management device installed in a data processing system that exchanges data strings between multiple CPUs, which mutually uses the memory connected to other CPUs or is installed independently from the memory. a memory mapping circuit provided for each CPU to convert the address space of the CPU into the address space of the data memory;
A memory management device comprising: an address selector circuit that selects an address output of a memory mapping circuit that is accessing the data memory from among address outputs from the memory mapping circuit to the data memory.