JPS593532A - Data processing device - Google Patents

Abstract

PURPOSE:To relax restrictions of an address space, to increase the transfer data units and the number of circuits to be handled, by providing a control part which discriminates a direct memory access permission signal, selects one of plural devices or memories and connects it to a bus. CONSTITUTION:A bus control part BSC detaches a memory M1 from a bus BS by a bus occupancy permission signal from a processing device CPU, and controls so that a memory M3 is connected to the bus BS instead. In this case, the control part BSC can transfer a data through the bus BS to a memory M2 or M3 from an input interface IF1 in accordance with control of a direct memory access control device DMAC1. Also, in accordance with control of a direct memory access control device DMAC2, the control part BSC can transfer a data through the bus BS to an output interface device IF2 from the memory M2 or M3.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to data diversification using a storage program using a data processing device in a data transmission system, particularly a processing device such as a microprocessor.

The present invention relates to a data processing device that performs processing such as buffering and transfer control.

Prior Art and Problems In a data transmission system, file management of buffer memory 1. Management of communication control procedures, etc. is generally handled by a storage program using a processing device such as a microprocessor. The structure shown in FIG. 1 or 2 is adopted.

FIG. 1 shows the case of unidirectional data transmission, and FIG. 2 shows the case of bidirectional data transmission. In each figure, CPU is a processing device such as a microprocessor, Ml is a memory such as a read-only memory (ROM) that stores a program, and M2 is a random access memory (R, 4Af) for writing or reading data. Memory, BS, IFl
, IF5 is an input interface it, IF2.1F4 is an output interface device, I) MAC1 to DMAC4 are direct memory access control devices, CTL is a control unit, and each memory M1.1F4 is connected to the bus BS. M2.
Interface devices IF1 to IF4. Direct memory access control devices DMAC1 to DMAC4, etc. are assigned addresses so as not to overlap each other.

When exchanging data via bus BS, processing unit CPU or direct memory access control unit DMAC
1 to DMA C4 sends address information, read/write designation, etc., and the memory corresponding to that address, the interface device, is selected as a result of decoding the address information, and sends data on the bus BS, or on the bus BS. It operates to receive the data of.

The control unit CTL also controls the memory M1 .
M2, each interface device, a direct memory access control device, etc., is used to create a control signal that specifies the device, and is provided in order to reduce the waste of each device decoding address information.

FIG. 3 is a block diagram of the main part of the control unit CTL. Parts of address information A12 to A15 are decoded by a decoder DEC, and signals Sf1 and 5M2 are sent to the memory M1.
M2 is designated, and a hard register such as a diinterface, an ace device, a direct memory access control device, etc. is designated by the signal REG. For example, if address bit A15 is 10', the gate of decoder DEC is closed, and memory M2 is specified by signal SM2, and address bit
415 is #1'', Tetres pits A12 to A14 are decoded, and signal REG or signal SM1 or 5M
2, the register is designated or the memory IJM1 or M2 is designated.

Data from input devices (not shown) are input to input interface devices IF1. The contents of the memory M2 are temporarily stored in the memory M2 via the IF3, and the processing device cpv sends the contents of the memory M2 to the output interface devices IF2 and IF4 according to the transfer procedure program stored in the memo I) Ml. Transfer to ). .

For high-speed and large-capacity data input/output, the processing unit CPU uses input/output interface devices IF1 to IF4 and direct memory access control devices DMA1 to DM.
It is common to control A4 and transfer data directly to and from memory M2 using a direct memory access method, thereby reducing the processing load on the processing unit CPU.

When transferring data using this direct memory access method, for example, when transferring data from the input interface device IF1 to the memory M2, the direct memory access control device DMAC1 sends a bus occupation request signal to the processing device cpv, and the processing device CPU By accepting the request signal, the program processing is stopped, and the direct memory access control device DMAC1 occupies the bus BS to transfer the data from the input interface device IF1 to the memory M2.

Here, the address space handled by the processing unit CPU is finite, and therefore the data capacity handled is limited, so the number of multiplexed lines is limited, and the unit of transfer data cannot be increased, etc. It may be necessary to divide the functions by providing multiple processing devices. However, with the increase in hardware, disadvantages such as an increase in software division loss arise.

OBJECTS OF THE INVENTION The present invention aims to economically improve data processing capacity through effective use of address information.

Since the configuration memory of the invention tends to have a large storage capacity such as 64KB, 128f#, 256KB, etc.,
Measures are taken to prevent access to portions that overlap addresses of program memory or other devices, leaving unused portions.

This inconvenience can be avoided by selectively using the same address over and over again when transferring data by direct memory access or the like. Examples will be described in detail below.

Embodiment of the invention FIG. 4 is a block diagram of an embodiment of the invention.
The same reference numerals as those in FIG. 1 and FIG. 2 indicate the same parts, ESC is a bus control section, and M3 is a memory assigned the same address as the memory M1. The bus BS includes a processing unit [CPU, memories M1 to M6, input/output interface device IF1.
IF2 and direct memory access control unit fkDM
AC1, I) MAC2 is connected.

The bus control unit ESC disconnects the memo 1Jf1 from the bus BS in response to the bus occupancy permission signal from the processing unit CPU.
Instead, it controls the connection of the memory M6 to the bus BS, and at this time, according to the control of the direct memory access control device 1) HA (A), the input interface device I
Data can be transferred from F1 to memory M2 or M3 via bus BS, and data can also be transferred from memory M2 or M6 to output interface device IF2 via bus BS under the control of direct memory access control device DMAC2. . Therefore, conventionally memory M
Although the data transfer was performed by the direct memory access method using only the memory M6, in the above-described embodiment, the memory M6 can also be used, so that the unit of transfer data can be increased.

FIG. 5 is a block diagram of another embodiment of the present invention, in which the same reference numerals as in FIGS. 1, 2, and 4 indicate the same parts;
M4 is a memory. Memory J/3°M4 is memory M1
The memory M6 is assigned the same address as 9, and the memory M6 is used as a backup memory for data going from the input interface device IF1 to the output interface device IF2, and the memory M4 is used as a buffer memory for data going from the input interface device IF5 to the output interface device IF4. It is used.

The bus control unit ESC analyzes which direct memory access control device the bus occupancy permission signal from the processing unit CPU is output to, and if it is directed to the direct memory access control devices DMAC1 and DMAC2, it is sent to the bus occupancy permission signal instead of the memory M1. The memory M6 is connected to the bus BS, and the direct memory access control device DMAC5, 1) MAC4
In this case, memory M4 is connected to bus B instead of memory M1.
control to connect to S.

The bus occupancy approval signal from the direct memory access control device is accepted by hardware in the processing unit CPU, and a bus occupancy permission signal is output. At the same time, when data is transferred from the memory M4 to the output interface device IF4, the bus switching is done automatically and instantaneously, and there is no program processing involved, increasing the processing load on the processing unit CPU. There's nothing to do.

FIG. 6 (α), (,6) is a block diagram of the main part of the bus control section, where DEC is a decoder and 01 to G7 are gate circuits. FIG. 6(,) shows a main part of an example of the bus control unit B'SC in FIG. Output of signal SM1 specifying M1 is prohibited, and memory M3 is specified by signal SM5.

FIG. 6(b) shows a main part of an example of the bus control unit ESC in FIG. 5, and DMA1 to DMA4 are bus occupancy permission signals that enable data transfer under the control of the direct memory access control units DMAC1 to DMAC4. The output of the signals SM 1 and 5M2 specifying which bus occupancy permission signal is added is prohibited, and the output of the signal DMA is prohibited.
1, DMA 2, the signal SM
5 is output to specify memory M6, and when either signal DMA3 or DMA4 is applied, signal SM4 is output and memory M4 is specified. Instead of arranging such bus control units in a centralized configuration, it is also possible to arrange them in a distributed manner.

When using Ml, the address 'ooooo of memory M1
Assuming that the same address as "~' 5 FFF" is assigned to area A1 corresponding to memory M3, and addresses '6000'' to 'FFFF' are assigned to area A2 corresponding to memory M2, conventionally 64 KB of memory is used. Even if miniaturization were attempted, only the 40 KB capacity of area A2 could be used for data storage, but according to the present invention, the entire 64 KB memory can be used for data storage.

In other words, there is no access to the memory M1 that stores the program when data is accessed through direct memory access, and therefore a memory with a large storage capacity is made effective by using a double address where the address assigned to memory M1 is assigned to memory M3. As a result, the unit of data to be transferred can be increased, and the number of multiplexed lines can be increased. Furthermore, the same address can be similarly assigned not only to the memory but also to other devices, so that the desired device can be selected by identifying the bus occupancy permission signal. Also, not only double addresses, but six addresses.

It can also be applied to the case of allocating quadruple addresses.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention arranges a plurality of devices or memories to which the same address is assigned to a bus BS, and identifies a direct memory access permission signal to access one of the plurality of devices or memories. By providing a control unit ESC that selects one and connects it to the bus BS, it is possible to alleviate the constraints on the address space and economically increase the number of transfer data units and the number of lines that can be handled. There are advantages that can be achieved.

[Brief explanation of the drawing]

1 and 2 are block diagrams of a conventional data processing device, FIG. 6 is a block diagram of main parts of a conventional control section, and FIGS. 4 and 5 are blocks of different embodiments of the present invention. FIGS. 6(G) and 1(A) are block diagrams of main parts of the control section of different embodiments of the present invention, and FIG. 7 is an explanatory diagram of an example of the address space of the memory. CPU is a processing unit, M1 to M4 are memories, BS is a bus,
IFl, IF3 are input interface devices, IF2,
IF4 is an output interface device, DMAC1 to DM
AC4 is a direct memory access control device, and ESC is a bus control section. Patent applicant: 1 representative from outside Fujitsu Ltd. Patent attorney: Hisashi Tamamushi, 3 outsiders Figure 1 Figure 2 Figure 3 Figure 4 wj s Figure 6 (a) (G) Figure 7 Figure 161-

Claims (1)

[Claims] In a data processing device that is equipped with a processing device, a program memory, a data memory, a direct memory access control device, an input/output interface device, and a bus common to these devices, and sends and receives data via a cipher using direct memory access control, In addition to arranging multiple devices or memories with the same address assigned to the same bus,
A data processing device characterized by comprising a control unit that identifies a direct memory access permission signal and selects and connects one of a plurality of devices or memories having the same address.