WO1988006319A1

WO1988006319A1 - Dma data transfer apparatus

Info

Publication number: WO1988006319A1
Application number: PCT/JP1988/000101
Authority: WO
Inventors: Mikio Yonekura
Original assignee: Fanuc Ltd
Priority date: 1987-02-14
Filing date: 1988-02-04
Publication date: 1988-08-25
Also published as: JPS63200261A

Abstract

A DMA data transfer apparatus which controls the operation performed when data are exchanged between a first apparatus (3) among a plurality of apparatuses and a second apparatus (4) by utilizing a system bus (5). There are provided a DMA controller (1), a bus arbiter (6) for receiving from the DMA controller (1) a request for using a system bus (5) and for arbitrating among requests for use from different apparatuses to decide the approval, and a buffering circuit (2) between the first apparatus (3) and the system bus (5). The buffering circuit (2) can receive data in a predetermined number of steps from the first apparatus (3) to transfer the data to the second apparatus (4) in parallel form at a time. The buffering circuit (2) can also receive an amount of data at a time from the second apparatus (4) and transfer the data to the first apparatus (3) in a predetermined number of steps.

Description

Description D M A Data transfer equipment Technical field

The present invention relates to a data transfer apparatus using direct memory access (DMA). Background art

Data transfer by direct access (DMA) that directly transfers data between storage devices, input / output devices, and other peripheral devices using the system bus without using the CPU For this purpose, a dedicated control device (DMA controller, hereinafter referred to as DMAC) is commercially available as LSI and is widely used.

FIG. 1 shows a conventional DMA data transfer device using such a DMAC. In the figure, 1 is a DMA controller (DMAC), 6 is a bus arbiter, 30 is a peripheral device, and 30-1 is a controller of this peripheral device (PDC below the peripheral device controller). , 20 is a bidirectional buffer, 40 is a RAM. 51 is a 16-bit system bus. DMAC1 controls the data transfer by DMA. Bus ♦ — — When the system bus 51 is shared by a plurality of devices, the bus 6 arbitrates the right to use the system bus 51 with another device, and the system 6 for the DMAC1. Use bus 5 1 It is for obtaining Genes. The PDC30-1 controls peripheral devices like a front-end disk controller or a CRT controller, for example. The bidirectional buffer 20 is a data buffer that can pass through only one direction in response to data writing or reading under the control of the DMAC1. Here, the RAM 40 exchanges data with the peripheral device 30 via the system bus 51. The system bus 51 is a bus shared by a plurality of devices as described above.

The meaning of each input / output in the DMAC1, PDC30-1 and bus arbiter 6 in FIG. 1 will be described. DRQ. In PDC30-1 is the output end of the DMA data transfer request (DMA request signal) to DMAC1, DRQ in DAC1 is its input HLDRGI in DMAC1 is bus' Arbiter 6 uses system bus 51 6 The output terminal of the hold request signal requesting the request, the GSEL in the nos' arbiter 6 is the input terminal of the hold request signal, and the BMM in the bus arbiter 6 uses the system bus 51 for the DMAC1. (Information of approval of use of system bus 51) The output end of the bus 'master' mode signal, HLDAK in DMAC1 is the input end of the bus master mode signal, DACK in DMAC1 For example, the right to use the system bus 51 has been obtained for the PDC 30-1, that is, the output end of the DMA acknowledgment signal indicating the use

DACK in PDC30-1 is the input end, * I0RD in DMAC1 is the data read (read) signal (food logic) for PDC30-1 * I0WR is the output end of the data write (write) signal (negative logic) to PDC30-1. WR is the output end of the data write (write) signal sent to RAM 40 via system bus 51. RD is an output terminal of a data read (read) signal to be sent to the RAM 40 via the system bus 51, and RD in the PDC 30-1 is an input terminal of the data read (read) signal * I0BD from the * I0RD. WR is the input end of the * data write (write) signal from the I0WR, and * in the bus arbiter 6 is the input of a signal (* indicates negative logic) indicating the completion of data reading or data writing from the RAM 4. RDY in the bus end and bus arbiter 6 is output in response to the signal indicating the completion of the data read or data write in the * XACK. The data read or data write in the RAM 40 is completed. Output to the DMAC1 and the RDY of the DMAC1 is its input. D00 to D07 in the PDC 30-1 are input / output of transfer data to / from the peripheral device 30.

The operation of the DMA data transfer device having the configuration shown in FIG. 1 will be described below with reference to the timing diagram of FIG. 2A, in which data is transferred from the PDC 30-1 to the RAM 40. First of all peripheral equipment

Data for one transfer (generally 8 bits in many cases) is prepared in PDC30-1. Then, PDC30-1 sends a DMA request signal to DMAC1. That is, the output from the DRQ is set to the “1” level. In response, DMAC1 holds the request for the right to use the system bus 51 to the no-slave bitter 6. Send a request signal. That is, the output from the HLDRa is set to α 1 "(1). The nos' arbiter 6 inputs the output from the HLDBQ to the GSEL terminal (2). After arbitrating with the device having the higher priority (3) and ending the use of the system bus 51 by another device having higher priority, the right to use the system bus 51 is obtained. When you get the right to use the bus' Arbiter 6

B MM (the bus ♦ master ♦ mode) signal output as "1", transmitted to DMAC0HLDAK terminal (4), the DMAC1 becomes HLDAK input force t ^t 1 ", DMA Akuno Li Tsu di signal to PDC30- 1 To transmit the establishment of the right to use the data bus, that is, the DACK output is set to ^κ 1 "(5). When the DACK output is set to ^κ 1 ", the DMAC1 outputs the data read signal * I0BD to the PDC 30-1 and the data write signal (-inverted) to the RAM 40 via the system bus 51. , Which means that the signal level is "0" (5).

In PDC30-1, DRQ is set to "0" (6). Then, in the PDC30-1, a data read signal from the * I0BD output terminal of the DMAC1 is input from the ^ "terminal, whereby the data prepared in the peripheral device 30 is transferred to the system bus 5. Transfer to AM 40 via (1) When the data writing is completed in AM 40, a signal is sent from RAM 40 to bus arbiter 6 to notify the completion of data writing. Is performed by setting the * XACK input of the bus' arbiter 6 to "0". Sends a ready signal to DMAC1. That is, the RDY input of the DMAC1 is set to ^tt 1. When the DMAC1 receives the "1" level RDY input and recognizes the completion of data writing, it reads data from the PDC30-1 as described above. (Read) signal (* I0RD output) and the data write signal WR- to the RAM 40 are set to "1", and the DMA acknowledge signal to the PDC 30-1, ie, DACi (output is set to "0") (9) In the DMAC1, if the DACK output is set to "0", the hold request signal, that is,

Return the HLDAK output to "0" (10). Also, a signal indicating completion of writing data from the RAM 40, that is, * XACK input is

Data write signal from DMAC1, i.e., by the WR input is returned to ¹¹ 1, returns to "1" (10). As a result, the ready signal, that is, the RDY output also returns to "0". (11) In the PDC30-1, the data read (read) signal (* I0RD output) from the DMAC1, that is, the PDC30-1 Data transmission stops when the RD input returns to "1" (10). Since the HLDRQ output from DMAC1 has become "0", the GSEL input of the slave * 6 is "0" (11), and accordingly the BMM output also becomes "0" (12) As a result, the HLDAK input of DMAC1 returns to "0" (13). The above is the operation of one cycle of data transfer from the PDC 30-1 to the RAM 40 in the conventional DMA data transfer device.

The timing of the data transfer from the RAM 40 to the PDC 30-1 in the conventional DMA data transfer device shown in FIG. 1 is shown in FIG. 2B. The operation procedure and timing are described in the second embodiment. A figure Is exactly the same as in the case of, where RD in Fig. 2A is WR, and Only "ϋ" is replaced by * I0RD and * I0WR. However, the signal * XACK from βΑΜ40 is sent not only at the time of completion of data writing but also at the same time as the transfer data from the RAM 40 in FIG.

In the configuration of DMA data transfer as shown in Fig. 1, the width of data that can be transmitted at one time in PDC30-1, that is, the number of bits (most PDC30-1s usually have 8 bits) is In many cases, the number of bits of the system bus 51 or BAM 40 is smaller than 16 bits (for example, 16 bits, or 32 ^ * bits).

In such a case, the conventional DMA data transfer device described above uses only a part of the bits of the system bus, so that the efficiency of use of the system bus is low and the frequency of use of the system path increases. However, there is a problem that the time for occupying the system bus becomes longer.

Also, in peripheral devices that have a limited response time on the DMA controller side in response to DMA requests (for example, edge-to-edge disk drives), the response time margin is so small that data is missed, There is also a problem that the probability of occurrence of writing is increased. For example, in the case of a disk drive with a disk drive, data is transferred between the floppy disk and a register in the floppy disk controller every 10 μsec. After that, there is a restriction on the response time of the DMA controller that data must be transferred to and from other devices by DMA during the next less than 10 / sec. DMA co If the controller cannot acquire the right to use the system bus in less than 10 seconds, data may be read or lost,

Disclosure of the invention

An object of the present invention is to improve the efficiency of using the system bus when transferring DMA data to a device having a small data width, to reduce the frequency of using the system bus, and to reduce the time occupied by the system bus. Provides a DMA data transfer device that increases the response time margin for DMA transfers from devices that have a limited response time to DMA requests, thereby reducing the probability of data reading and writing errors Is to do.

A DMA data transfer device according to the present invention includes a system bus shared by a plurality of devices, and a first device of the plurality of devices being connected to a second device of the plurality of devices. A DMA controller for controlling the operation of exchanging data by using the system bus, and the DMA controller receiving a request for using the system bus from the DMA controller, What is claimed is: 1. A DMA data transfer device comprising: a bus arbiter for granting approval of use of said system bus to a controller, wherein a buffering circuit is provided between said first device and said system bus. The buffering circuit receives a predetermined number of data transfers from the first device, transfers the predetermined number of data simultaneously and in parallel to the second device, The buffering circuit is In response to one data transfer from the second device, the transfer of data once the divided into the predetermined number of times to the first device Features. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing a conventional DMA data transfer device,

FIG. 2A is a diagram showing the timing of data transfer from the PDC 30-1 to the RAM 40 in the configuration of FIG. 1,

FIG. 2B is a diagram showing timing of data transfer from βΑΜ40 to PDC 30-1 in the configuration of FIG. 1,

FIG. 3 is a diagram showing a basic configuration of the present invention,

FIG. 4 is a diagram showing a configuration related to data transfer from the PDC 30-1 to the RAM 40 in the embodiment of the present invention.

FIG. 3 is a diagram showing a configuration relating to data transfer from the RAM 40 to the PDC 30-1 in the embodiment of the present invention;

Fig. 5A is a diagram showing the timing in FIG. 4A in the form of a metal- Fig. 5B is a diagram showing the timing in the configuration of Fig. 4B-Fig. 6 is a notifying FIG. 11 is a diagram illustrating another embodiment of the first transfer register specifying unit 2-2 and the first buffer register unit 2-3 of the circuit 2; BEST MODE FOR CARRYING OUT THE INVENTION

FIG. 3 is a diagram showing a basic configuration of the present invention. In this figure, 1 is a DMA controller, 2 is a buffering circuit, 3 is a first device, 4 is a second device, 5 is a system bus, and 6 is a bus ♦ arbiter. Here, the first device 3 and the second device 4 exchange data via the system bus 5, respectively. Storage device, input / output device, and other peripheral devices. The DMA controller 1 uses the above system bus 5 without the CPU between the storage device, the input / output device, and other peripheral devices as described above in the background art section. It controls the operation of this data transfer when exchanging data. When receiving a request to use the system bus 5 from the DMA controller 1, the bus arbiter 6 adjusts the right to use the system bus 5 with another device, and When the use of the system bus 5 by the higher-priority device is completed and the right to use the system bus 5 is established, the DMA controller 1 is notified of this. That is, use approval of the system bus 5 is given to the DMA controller 1. The system bus 5 is a means for bidirectionally transmitting various main information in the system, for example, data, addresses, control signals, and the like.

A general DMA data transfer device is composed of the above-mentioned DMA controller 1, nos arbiter 6, and system bus 5, and is composed of the first device 3 and the second device 4. The feature of the present invention lies in that a non-offering circuit 2 is provided between the first device 3 and the system bus 5. . The buffering circuit 2 receives a predetermined number of data transfers from the first device 3 and transfers the predetermined number of data simultaneously and in parallel to the second device 4. The buffering circuit 2 receives one data transfer from the second device 4 and divides the one data into the predetermined number of times. To the first device 3.

When the data of the first device 3 is transferred to the second device 4 in the DMA data transfer device of the present invention, the buffering circuit 2 provided in the present invention uses the number of bits in one data transfer. After receiving a small number of transfer data from the first device 3 for a predetermined number of transfers, the data is transferred to the second device 4, and conversely, when data is transferred from the second device 4, the data is transferred to the first device 3. The number of bits that can be transferred is a predetermined multiple of the number of bits that can be transferred to the buffering circuit 2, and then the bits that can be transferred from the buffering circuit 2 to the first device 3 and to the first device 3. The number is transferred by the predetermined number.

Thus, in the DMA data transfer device of the present invention, the utilization efficiency of the system bus 5 is improved, the number of times the system bus 5 is used is reduced, and the response time margin on the DMA controller side is reduced. Can be larger. FIG. 4A and FIG. 4B each relate to the configuration relating to the data transfer from PDC 30-1 to 40 and the data transfer from RAM 40 to PDC 30-1 in the embodiment of the present invention. FIG. 3 is a diagram showing a configuration.

First, the configuration shown in FIG. 4A will be described.

In FIG. 4A, DMAC 1, bus arbiter 6, peripheral devices

The 30, PDC 30-1, RAM 40, and 16-bit system bus 51 are the same as in the first side configuration.

As described above, in the present invention, a buffer is used instead of the bidirectional buffer 20 provided on the data transfer path between the peripheral device 30 and the 16-bit system bus 51 in FIG. Ring Circuit 2 is provided. FIG. 4A shows only the configuration related to the data transfer from the PDC 30-1 to the RAM 40, out of the configuration of the buffering circuit 2.

The buffering circuit 2 in FIG. 4 includes a buffer register—a PDC transfer sequencer section 2—1, a first transfer register designating section 2—2, a first buffer register section 2-3, and a first buffer register section 2-3. DMAC transfer controller 2-4.

Buffer 7 register-PDC transfer sequencer section 211 controls data transfer between buffering circuit 2 and PDC30-1. The first buffer register section 2-3 is configured to hold the data transferred under the control of the buffer register—PDC transfer sequencer section 2-1 for a predetermined number of times (two times in this embodiment). The first transfer register designating section 2-2 controls the holding of the transferred data in the first buffer register section 2-3, and confirms that the predetermined number of transfers have been performed. Check by counting. The first DMAC transfer control section 2-4 mainly controls the transfer of the predetermined number of data in the first buffer register section 2-3 to the RAM 40 using the DMAC1. .

Hereinafter, details of the configuration of each of the above units will be described.

The off-register and the PDC transfer sequencer section 2-1 consist of an SR flip-flop 22 and a sequencer 23. The SR flip-flop 22 indicates whether or not data is being transferred between the PDC 30-1 and the first buffer register section 2-3. 1 DACK input and sequence Connected to the IN input of sensor 2 3. The sequencer 2 3, flip Tsufufu port _y Bed 2 2 valid Q output receives the IN input as soon first buffer Rejisutako down preparative roll (BC) output by Ri first buffer register section 2 - 3 in a register in the 31 Output a signal to enable data writing to 1 or 32, and send a data read (read) signal to PDC30-1 from RD output. Then, after timing sufficient to complete the data transfer from the PDC 30-1 to the register 31 or 32 by these signals, the end signal is output from the END output. This end signal indicates the end of one-side data transfer from PDC30-1 to buffering area 2, and is synchronized with the clock and has a pulse width of about one clock cycle. The signal is input to the first transfer register setting section 2-2, and the flip-flop 22 is reset to return the DACK input of the PDC 30-1 to the "0" level. Although the internal configuration of the sequencer 23 is not shown, it is triggered at the rise of the IN input and outputs three types of pulses having a predetermined width at predetermined timings. It is easily configured with a counter and a differential circuit.

The first transfer register setting section 2-2 comprises a T flip-flop 24 and three end circuits 25, 26 and 27, and the T flip-flop circuit 24 is provided with a signal from the sequencer 23. Each time an end signal is input, the Q output is inverted in synchronization with the rising edge of the clock, and the end circuits 25 and 26 are sequentially opened. The BC outputs of the sequencer are both connected to the AND circuits 25 and 26, and each output is connected to the first buffer level. Connected to the control input of the register in the registers 2 and 3. In this way, the register register control (BC) if signal from the sequencer 23, that is, the signal that enables the register 31 or 32 to be written, is transmitted by the first transfer. After passing through the register setting section 2-2, each time the end signal of the sequencer 2 3 is output, that is, every time one data transfer from the PDC 30-1 to the buffering circuit 2 is completed, another Will be input to the control input of this register. Further, the Q output of the flip-flop 24 is connected to the other input of an AND circuit 27 whose one input is connected to the END output of the sequencer 23, and When the buffer register control (BC) output of the sensor 23 is input to the last register in the first buffer register section 2-3, the AND circuit 27 must Are also set so that the end signal can pass through. In other words, the output of the AND circuit 27 completes data transfer from the PDC 30-1 to all (two in this example) registers 31 and 32 in the first buffer register section 2-3. It shows that you have done.

The first buffer register section 2'-3 includes two 8-bit registers 31 and 32, and a buffer circuit 33. The output terminals of the registers 31 and 32 are connected to the 8-bit data output terminals D00 to 07 of PDC30-1 respectively, and the outputs of the first transfer register setting unit 2-2 are connected to the output terminals. The outputs of circuits 25 and 26 are the respective control inputs. The output terminals of these registers 31 and 32 are connected in parallel to the input terminal of a 16-bit buffer circuit 33. This buffer circuit 33 The DACK output of DMAC1 is used as a control input, and data can be passed when CK is at the ^α 1 "level. In other words, this control input plays the role of a read signal from DMAC1.

The first DMAC transfer control section 2-4 comprises a differentiating circuit 29, an SR flip-flop 28, and an AND circuit 21. The differentiating circuit 29 receives the DACK output of as input and detects the falling edge of the DACK signal, that is, the end of data transfer from the referencing circuit 2 to βΑίΙ40 due to DilACl, and ends the DMA transfer. The signal of is output. The output of Differentiated West Road .29 is connected to the reset input of SR flip-flop 28. In addition, the output of the AND circuit 27 of the second transfer register setting unit 2-2 of the previous arrest, that is, the data transfer from the PDC 30-1 to all the registers of the first knock register unit 2-3 is performed. The signal indicating that the operation has been performed is connected to the set input of the SR flip-flop 28. Thus, the SR flip-flop 28 is in a state in which the buffering circuit 2 is performing data transfer with the PDC 30-1 or in a state in which data is transferred between the buffer circuit 2 and the RAM 40 by the DMAC 1. When the Q output is "0", it corresponds to the former, and when the Q output is ¹¹ 1 ", it corresponds to the latter. The AND circuit 21 is connected to the RAM 40 by the DMAC1. During data transfer between (-"0 ^Ώ simple)

When a new signal from the DRQ output of the PDC30-1 is not accepted, the DACK output of the DMAC1 falls and the "5" of the SR flip-flop 28 becomes "1" until the PDC30 -Pass the DRQ signal from 1. The output of the AND circuit 21 is connected to the SR register flip-flop of the buffer register: PDC transfer sequencer 2-1 When the AND circuit 21 is open, the DMA request signal from the DRQ output of the PDC 30-1 is connected to the SR flip-flop 2 When 2 is set, data transfer from the PDC 30-1 to the first buffer register section 2-3 starts as described above.

In the following, the operation of the configuration of FIG. 4A as described above will be described with reference to the timing diagram of FIG. 5A.

First, when 8-bit data is prepared in the PDC30-1, the PDC30-1 sets the DRQ output to the "1" level. Flip-flops. If the initial states of VI, 24 and 28 are all Q = "0", the inputs of AND circuit 21 are both 1 and flip-flop 22 is set, and the Q output Becomes "1" (1). The Q output of flip-flop 22 is connected to the DACK input of PDC30-.1, and DACK becomes "1" (2). On the other hand, the Q output of flip-flop 22 is also input to sequencer 23. The sequencer 23 immediately sets the buffer register control output BC to "1" and the read signal output RD to the PDC30-1 to "0" level when the IN input rises. (2). The buffer register control output BC is an input to one of the AND circuits 25 and 26, but the initial state of flip-flop 24 is Q = 0 and Due to this, only AND circuit 25 is open. On the other hand, the read signal output of the sequencer

When the RD is input to the PDC 30-1, the 8-bit data is transmitted from the PDC 30-1 (3), and out of the registers 31 and 32, the above-mentioned AND circuit 25 outputs a signal. Trigger input This 8-bit data is loaded into register 31. When the data transfer to the register 31 is completed, the sequencer 23 returns the levels of BC and ^ to their original levels, and further increases the width of the clock 1 cycle in synchronization with the clock pulse from END 岀. A pulse (end signal) is output (4). The END output is Sennyo the reset input of flip Ppufu opening-up 2 2, Q output of the full re Ppufuko-up 2 2 by the end-signal, and ^a 0 ⁿ (5). The Q output is also PDC30- since 1 is Sennyo the DACK input also becomes ^κ 0 ^"(5>. On the other hand, the END output is also a T flip Ppufuro-up 2 4 T input And the Q output is inverted, ie, "1"

( Five ) . As a result, the AND circuit 26 in which the Q output is directly connected to one input is opened. The Q output of the flip-flop 24 is also connected to one input of an AND circuit 27, and the END output is connected to the other input of the AND circuit 27. However, as described above, since the end signal is output with a width of one clock cycle in synchronization with the clock in the sequencer 23, the end signal is output to the flip-flop 24. When this pulse arrives and synchronizes with the rising edge of the next clock pulse, it is almost near the falling edge of the end signal pulse, and the Q intensity of this flip-flop 24 increases from ^κ 0 to “ 1 ", and the rising of this Q output competes with the falling part of the end signal input to the other of the AND circuit 27 in the AND circuit 27, and the rising of the Q output from the AND circuit 27 May be exposed to a very short hazard pulse, The SR flip-flop 28, which uses the output of the AND circuit 27 as a reset input, is a clock synchronous type and is not affected by the above hazard pulse.

In PDC30-1, DACK is "0", so when the next 8-bit data is sent from peripheral device 30, the DRQ output is set to ^α1 again (6). As described above, the DRQ output sets the flip-flop 22 (6), sets the DACK input of the PDC 30-1 to "1", drives the sequencer 23, and sets the sequencer 23 to the sequencer 23. The BC output of 23 is set to "1" and the RD output is set to "0" (7) Here, as described above, the Q output of flip-flop 24 is inverted to "1". Therefore, the AND circuit 26 is open, and this time, the 8-bit data from the PDC 30-1 is loaded into the register 32 (8).

When the data transfer is completed, the BC and RD outputs are returned to their original levels, and the end signal is output from the sequencer 23 (9). This end signal is the same as the previous time. By resetting, the input of the PDC30-1 is returned to "0" (10) and the flip-flop 24 is inverted. However, for the same reason as before, the AND circuit 27 Just before the Q output of the flip-flop 24 connected to one input is inverted, the end signal passes through the other input of the AND circuit 27. In other words, the end signal of this time is set to 0 when the other input of the AND circuit 27 is at the “1” level before the inversion of the Q output of the flip-flop 24. 2 7, the output of this AND circuit 27 becomes “1” and flip-flop 28 is set. Yes (10). Here, the DRQ signal from the PDC 30-1 is cut off by the ground path 21 because the output of the flip-flop 28 becomes "0". Become. In addition, the Q output of flip-flop 28 is connected to the DRQ input of the flip-flop 28, which becomes "1" (11). through the bus arbiter 6 in Te頗of as described (12) obtains a scan te Mubasu 5 1 use攉the DACK output and ^kappa 1 "(13). DACK output DMAC1 begins counting Tsu off § surface path 33 is a control input, and when it becomes "1", the no-floor area 33 can be passed, and the register 31 and the register 3 2 can be passed. The total of 16 bits of data that was loaded into the RAM are transferred in parallel to 40 via the system bus 51. DMAC1 to RAM

A data write signal is sent to the RAM 40 with the WR at the "0" level, and the 16-bit data is written to the RAM 40. As in the description of FIG. 1, when the data writing is completed at βΑΜ40, the completion of the data writing from the SAM 40 to the bus arbiter 6 is determined by setting the XACK signal to ^κ 0 ". This is transmitted in such ^a way that the RD Υ input becomes “1a” (14), which causes the DMAC1 to return WR to its original level, and also returns the DACK output to ^κ 0 (15) . WR is "by Ri 40 and the child was returned to the 1 a ^* XACK κ 1" to苠(16), which by the RDY input of DMAC1 (RDY output of the path arbiter 6) Tabakoru to ^{α 0} "(17 ). DMAC1 DACK output is differential surface

This differentiating circuit 29 detects the falling edge of the input and outputs a pulse of a predetermined width. "1"-"0" Detects the falling edge of ^π (15), and outputs a pulse to reset flip-flop 28 '(18). 's DRQ signals, so that it can pass through the Anne de circuits 2 1, i.e., become acceptable. the 5 Alpha Figure 1 9, from § emissions de circuits 2 1 above is opened, the previously ^α This shows the case where the DRQ of the PDC30-1 that was 1 "was waiting, so that the next 8-bit data reading starts immediately after flip-flop 28 is reset. Is shown. Subsequent steps are repetitions of the previous cycle. Next, the configuration of FIG. 4 will be described.

In FIG. 4, the DMAC1, bus arbiter 6, peripheral device 30, PDC 30-1, AM 40, and 16-bit system bus 51 are the same as those in the configuration of FIGS. 1 and 4A. It is.

As described above, in the present invention, instead of the bidirectional buffer 20 provided on the data transfer path between the peripheral device 30 and the 16-bit system bus 51 shown in FIG. A buffering circuit 2 is provided. FIG. 4B shows only the configuration related to data transfer from the PDC 30-1 to the RAM 40 out of the configuration of the buffering circuit 2.

The buffering circuit 2 is composed of a buffer register—a PDC transfer sequence section 2—1, a second transfer register designating section 2—5, a second buffer register section 2—6, and a It consists of two DMAC transfer controllers 2-7. The main functions of these parts are basically the same as those of the corresponding parts in FIG. 4A. The buffer register PDC transfer sequencer section 2 — 1 ′ in FIG. 4B has exactly the same functions as those in FIG. 4A described above, and includes the SR flip-flop circuit 22 ′ and the sequencer 23 ′. Consists of The sequencer 23 'of FIG. 4B replaces the first buffer register control (BC) output and the data read signal (RD) output of sequencer 23 of FIG. ^ It has a register control (BC ') output and a data write signal (WR).

In the second transfer register setting section 2-5, the AND circuits 25 and 26 in the first transfer register setting section 2-2 in Fig. 4A have been replaced with NAND circuits 38 and 39. In other respects, this is exactly the same as the above-mentioned first transfer register setting unit 2-2. However, the meaning of the output signal of the AND circuit 27 ′ is evident from the description of the second buffer register section 2-6 below. This indicates that all data in registers 34: and 35 have been transferred to PDC30-1.

The second buffer register section 2-6 includes two 8-bit registers 34 and 35, and two buffer circuits 36 and 37 ". The two registers 34 and 35 are Of the 16-bit data input from the RAM 40 via the system bus 51, the upper 8 bits and the lower 8 bits are input, respectively.These two registers 34 and 35 store the DMAC1 * The I0WR output is used as a control input, and the notifier circuits 36 and 37 are connected to the output side of the registers 34 and 35, respectively. The outputs of the NAND circuits 38 and 39 in the second transfer register setting section 2-5 are used as control inputs. The outputs of these two buffer circuits 38 and 39 are connected in parallel and input to the 8-bit data input / output terminals D00 to D07 of the PDC 30-1.

The second DMAC transfer controller 2-7 is also similar to the first DMAC transfer controller 2-4 described above, but the difference between the two is that the SR flip-up circuit shown in FIG. 4A is used. The set 28, reset input, and Q and output 28 are respectively interchanged in the SR flip-flop circuit 28 'in FIG. 4B. That is, in the second DMAG transfer control unit 2-7 in FIG. 4B, the output terminal of the differentiating circuit 29 'for detecting the falling edge of the DACK output of the DMAC1 is connected to the SR flip-flop 28'. The output end of the AND circuit 27 'of the second transfer register setting unit 2-5 that notifies the end of data transfer between the second buffer register unit 2-6 and the PDC 30-1 The Q output of the SR flip-flop 28 'is connected to the reset input of the SR flip-flop 28', and the buffer register PDC transfer sequencer section of the DMA request signal from the PDC 30-1 2 — Connected to one input terminal of AND circuit 2 1 that controls input to and cutoff of 1. The output terminal of the SR flip-flop 28 'is connected to the DRQ input of the DMAC1. As a result, in the initial state where Q of the SR flip-flop 28 ′ is “0”, the D Α request signal from the PDC 30-1 in the AND circuit 21 ′ is cut off, Since hundreds = ^α1 ”is connected to the DRQ input of DMAC1, DMAC1 performs the D Μ Α data transfer control operation and the second Data write control to the registers 34 and 35 in the register 2 — 6 by * I0WR output, and read control of RAM 40 via the 16-bit system bus 51 by the RD output of DMAC1, The data in the RAM 40 is loaded into the registers 34 and 35. Upon completion of this load, the falling of the output is detected by the differentiating circuit 29 ', and this output is set by setting the SR flip-flop 28' to set the Q output to "1" and the AND circuit 21 '. 'Enable to pass the DRQ output from PDC30-1 at. Also, as in the previous arrest, the AND circuit 27 'of the second transfer register setting unit 2-5, which notifies the end of the data transfer between the second buffer register unit 2-6 and the PDC 30-1. The output resets the SR flip-flop 28 ', and starts data transfer between the RAM 40 and the second buffer register section 2-6 by the DMAC1 again.

In the following, the operation of the configuration of FIG. 4B as described above will be described with reference to the timing diagram of FIG. 5B.

First, assume that the initial states of flip-flops 22 ′, 24 ′ and 28 ′ in the configuration of FIG. 4B are all Q = “0”. Then, the output terminal of the flip-flop 28 'is connected to the DRQ input terminal of the DMAC1 and is "1", so that if the DMAC1 is used, the system bus 51 is connected to the system bus 51 via the noise arbiter 6. (1) On the other hand, the Q output terminal of flip-flop 28 'is connected to the input terminal of AND circuit 21' together with the DRQ output terminal of PDC 30-1, and Q = 0 "Means that the DRQ output of PDC30-1 is shut off. Now, DMAC1 is connected via bus arbiter 6. When the right to use the system bus 51 is obtained (2), the DACK output is set to "1", and the * I0WB and "!" Outputs are set to "0". RD! ? Sent to AM 40, * I0WB becomes the trigger input for registers 34 and 35 as described above. Thus, the upper and lower 8 bits of the 16-bit data are loaded from the RAM 40 to the registers 34 and 35 via the system bus 51. When the data is transferred from the RAM 40, the * XACK input of the bus arbiter 6 becomes "0" and returns to the DACK output power of the DMAC 1 "0" in the same manner as in the case of FIG. 3, 4). The DACK output is connected to the differentiating circuit 29 '. The output of the differentiating circuit 29' sets the flip-flop 28 '(6), and sets the "^ output to" 0 ". "0" back to, the Do ivy Q output to the other "1 ⁿ is input to the aforementioned a down de circuit 21 ', to allow accept DRQ output PDC30-1. Here, when the PDC 30-1 is ready to receive data, the PDC 30-1 sets the DRQ output to "1", which in turn sets the flip-flop 22 'through the above-mentioned AND circuit 21'. The Q output is set to "1" (7). As a result, the DAC [(input of the PDC 30-1 becomes "1" (8), while the sequencer 23 'receives the BC "

(2nd buffer control) Set the output to "1" and the WR output to "0" (send the data write signal, 8). Although the BC output is connected to the inputs of the NAND circuits 38 and 39, only the NAND circuit 38 opens because the Q output of the flip-flop 24 'has the initial value "0". It has become. Thus, the BC output passes through the NAND circuit 38 to the control input of the buffer circuit 36. Then, it can pass through the buffer circuit 36. In addition, since the output that has become "0" is input as the "^ input" of the PDC 30-1, the 8-bit data of the register 34 connected to the buffer circuit 36 is transferred to the PDC 30-1. (9). At the end of this 8-bit data transfer, the BC and WB outputs are returned to their original levels (10), and the sequencer outputs the end signal from the END output (11). This end signal is exactly the same as that in the configuration of FIG. 4A described above, and resets the flip-flop 22 to return the DACK input of the PDC 30-1 to ^κ 0 ”. (11) While the next DRC output from the PDC 30-1 is acceptable, the Q output of the flip-flop 24 'is inverted to open the (11) -NAND circuit 34. As in the case of Fig. 4, the buffer circuit 37 can be passed by the next DRQ output, and the 8-bit data of the register 35 is transferred to the PDC 30-1 (12 13 14). The flip-flop 28 'is reset by the end signal after the data transfer to the second register 35 (16), similarly to the case of Fig. 4A. In the configuration shown in Fig. B, the Q output terminal of the flip-flop 28 'is connected to one input terminal of the AND circuit 21'. When the flip-flop 28 'is reset, the DRQ output from the PDC 30-1 is cut off by this AND circuit 21'. When the DRQ input is set to "1" (16), the next data transfer cycle from the RAM 40 is started.

In the above description, FIG. 4A shows an embodiment of the present invention. 4B shows the configuration related to the data transfer from the PDC 30-1 to the RAM 40 of the buffering circuit 2, and FIG. 4B shows the configuration related to the data transfer from the RAM 40 to the PDC 30-1. However, as mentioned in the explanation so far, both configurations have much in common.

The difference between the two components is that the flip-flop 28 'has its setting input and Q, "5: output replaced, respectively, and the first transfer register setting in Fig. 4A. Only AND circuits 25 and 26 of part 2-2 are replaced by NAND circuits 38 and 39 in the second transfer register setting section 2-5 of Fig. 4B, respectively. Further, the DMA data transfer device according to the present invention is performed as part of the system under the control of a host computer that controls the entire system. 4A Fig. 4-1, 4B Fig. 4-2, The common configuration in each case is that the data transfer from the PDC30-1 to the! The same configuration is used for data transfer to Only, it may be Rukoto to be selectively connected by the selector to be switched in advance by phosphodiester Topurose Tsu support portion (not shown).

In the above-described embodiment, two registers of 8 bits are arranged in parallel in the i-th and second buffer register sections 2-3 and 2-5. There can be no more than 2 ^k (k is an integer greater than 1). For this purpose, for example, a configuration as shown in FIG. 6 may be used. FIG. 6 shows the first transfer register setting section 2-2 and the first buffer register section 2-3 for data transfer from the PDC 30-1 to the RAM 40 shown in FIG. 4A. Is shown in the case where the number of registers in the first register register 2-3 is increased to 2 ² = 4. In FIG. 6, components that are the same as those in FIG. 4A are omitted as much as possible.

Figure 6 is an extension of the register H t, the four indicated by H _2, H _3, H _4, Accordingly, Ann gate (3 input for the control input of each register Circuit 73, 74, 75, 76), and the input from the END output of the sequencer 23 so that the above four gates are sequentially opened each time one of the above-mentioned end signals is output. There is a counter that connects two T flip-flops 71 and 72 that operate at the falling edge of the pulse. Further, the fourth when E down de signal reaches AND circuit 2 7 is a Anne de circuit 2 7 other two inputs Q have Q ₂ also both ^tt 1 "- 4 th end-signal en Circuit 27.

Furthermore, in the description so far, the number of data bits when directly communicating with the PDC is set to 8 bits, which is 8 bits in the currently used peripheral device controller (PDC). This is because there are many bits, and in the present invention, this bit number may be any number of bits.

As described above, according to the present invention, the use efficiency of the data bus is good, the use frequency of the data bus is low, the time for occupying the data bus is short, and the DMA control for the DMA request is performed. A DMA data transfer device is provided that increases the response time margin on the side of the camera. Industrial applicability

The present invention is useful for DMA data transfer between devices having different data widths.

Claims

New Section

1. a system bus (5) shared by a plurality of devices; and-a first device (3) of the plurality of devices is connected to a second device (4) of the plurality of devices. A DMA controller (1) for controlling an operation of exchanging data using the system bus (5);

A bus arbiter (S) which receives a request to use the system bus (5) from the DMA controller (1), and gives the DMA controller (1) permission to use the system bus (5); A DMA data transfer device comprising:

A west off-road (2) between the first device (3) and the system bus (5);

The buffering circuit (2) receives a predetermined number of data transfers from the first device (3) and transmits the predetermined number of data simultaneously and in parallel to the second device ('4 ), And the buffering circuit (2) receives one data transfer from the second device (4) and divides the one data into the predetermined number of times. DMA data transfer device characterized by transferring data to the first device (3).

2. The buffering circuit (2) includes the first device.

A buffer register PDC transfer sequencer section (2-1) for controlling data transfer between (3) and the buffering circuit (2), and holding data for a predetermined number of times by the data transfer; Buffer registers (2-3, 2-6) for storing Transfer register designating section (2-2, 2-6) for controlling the holding of the transferred data in the buffer register section (2-3, 2-6) and confirming that the transfer has been performed a predetermined number of times. — 5) and data transfer between the buffer register section (2-3, 2-6) and the second device (4) is performed using the DMA controller port (1). 2. The DMA data transfer device according to claim 1, further comprising a DMAC transfer control unit (2-4, 2-7) for controlling the transfer.

3. The buffer register section (2-3, 2-6) has a first number consisting of a number corresponding to the predetermined number of times for holding one read data from the first device (3). The contents of the registers (31, 32, 77, 78, 79, 80) and all the registers belonging to the first register group are simultaneously and simultaneously controlled by the DMA controller (1). And a first 3-state buffer circuit (33) for outputting in parallel.

A second register group (34, 35) comprising a number corresponding to the predetermined number of times, for simultaneously and in parallel inputting data from the second device (4); The contents of the group of registers (34, 35) are provided on the output side of each of the registers (34, 35), and are sequentially turned on under the control of the transfer register designation unit (2-5). 3. The DMA device according to claim 2, further comprising a 'second 3-state' non-slip circuit (36, 37) for enabling transfer of the contents of a corresponding register to said first device. Data transfer device.

4. The transfer register designating section (2-2, 2-5) A group of first gate circuits that output a signal that enables each register (31, 32, 77, 78, 79, 80) in the first register group to be written in sequence

(25, 26, 73, 74, 75, 76) and control of the buffer register register PDC transfer sequencer section (2-1), each gate of the first gate circuit group. First transfer register design flip-flop circuit that outputs a signal that sequentially opens the HI path

(24) having

A second gate circuit group (38, 39) for sequentially turning on the second tri-state 'buffer circuit (36, 37); a buffer / register—PDC transfer sequencer section; Under the control of (2-1), a second transfer register designating flip-flop circuit for outputting a signal for sequentially opening each of the gate circuits (38, 39) of the second gate circuit group The DMA data transfer device according to claim 3, having (24 ').

5. The transfer register designating section (2-2, 2-5) outputs the buffer from the first device (3) by the output of the first transfer register designating flip-flop circuit (24). Register section

A first transfer end gate circuit (27) for outputting a signal indicating the end of data transfer to (2-3, 2-6), and

The second transfer register designation flip-flop] The output of the II path (24 ') enables the data transfer from the buffer register section (2-3, 2-6) to the second device (3). The DMA data transfer device according to claim 4, further comprising a second transfer end gate circuit (27 ') for outputting a signal indicating the end.

6. The buffer register PDC transfer sequence section (2 (1) a flip-flop circuit (22) for indicating whether or not data is being transferred from the first device (3) to the buffer register section (2-3);

Upon receiving the valid Q output of the flip-flop circuit (22), control is performed for each data transfer to each of the gates (25 26) of the first gate circuit group each time data is transferred. And outputs a trigger signal for changing the output state of the transfer register designating flip-flop circuit (24), and outputs the trigger signal to the first device (3). 5. The DMA data transfer circuit according to claim 4, wherein the DMA data transfer circuit outputs a data read signal.

7. The buffer register—PDC transfer sequence unit (2 1 1 ') determines whether data is being transferred from the buffer register unit (2 3) to the first device (3). The flip-flop circuit shown (22 '>)

In response to the valid Q output of the flip-flop circuit (22 '), each gate (38, 39) of the second gate circuit group receives a signal every one data transfer. And a trigger signal for changing the output state of the flip-flop circuit (24 ') for specifying the transfer register, and applying a trigger signal (BC'). The DMA data transfer circuit according to claim 4, wherein the DMA data transfer circuit outputs a data write signal to the device (3).

8. The DMA transfer control section (2-4, 2-7) is set or reset according to the valid output of the first transfer end gate circuit (27, 27 '). And outputting a DMA transfer request (DRQ) signal to said DMA controller (1). The buffer register is reset or set by a DMA transfer acknowledgment (DACK) signal from the DMA controller (1), and the buffer register—PDC transfer sequence section (2-1, 2—1 ') 6. The DMA data transfer circuit according to claim 5, further comprising a flip-flop circuit (28, 28 ') enabling the operation of the DMA data transfer.