JPH04156656A - Communication method between multi-cpu systems - Google Patents

Abstract

PURPOSE:To save software by permitting CPU to access common RAM so as to realize inter-CPU communication at the time of an allocated time band in one period generated based on the clock of master CPU. CONSTITUTION:A switch control circuit 5 supplies a switch signal which is changed over at the time of the time band when either an address bus or data bus from plural CPU is previously divided and exclusively allocated in one period based on the clock from mater CPU 3 among plural CPU to a switch 4. The switch 4 connects the data bus and the address bus of CPU, which are instructed by the switch signal to common RAM 6, accesses RAM 6 and realizes inter-CPU communication. Thus, speed can be improved and CPU can be connected with simple circuit constitution.

Description

[Detailed Description of the Invention] [Summary] Multi-CP that communicates between multiple CPUs via memory
Regarding the communication method between U systems, each CPU in one period is based on the clock of the master CPU among multiple CPUs.
The purpose is to determine the time period when the common RAM can be accessed by the CPU, and to access the common RAM during this time and communicate between the CPUs.The purpose is to save software labor, speed amplifier, and easily connect multiple CPUs. A common RAM that is accessed by the CPU for inter-CPU communication, a switch that connects either the address bus or data bus from multiple CPUs to the common RAM, and a switching control that generates a switching signal to switch this switch. circuit, and the switching control circuit connects the address bus from the plurality of CPUs based on the clock from the master CPU among the plurality of CPUs;
A switching signal is supplied to the switching device to switch one of the data buses during a pre-allocated time slot in one cycle, and the switching device switches the address bus and data bus of the corresponding CPU to the common RAM. and common RAM
The CPU is configured to access and perform inter-CPU communication.

[Industrial application field]

The present invention relates to a multi-CPU system communication method for communicating between a plurality of CPUs via memory.

[Prior Art and Problems to be Solved by the Invention] Conventionally, in a system using multiple CPUs, for example, as shown in the block diagram of FIG. 5electedl, 2
Control signal lines such as the following are connected between each CPU and the common RAM controller. And the cpu is these 5ele
ctl-3electedl or 5elect2-
The control signal line of 3Iected2 was used to confirm that other CPUs were not using the common RAM, and when the common RAM was not in use, the common RAM was accessed to perform inter-CPU communication. Although this inter-CPU interoperability method hardware can be created relatively easily, the software
There was a problem in that it was necessary to check whether the PU was using the common RAM or not, and the time efficiency of the software was very poor. Further, although a CPU-to-1 hardware circuit can be created relatively easily, there is a problem in that it is difficult to create a 2-to-1 hardware circuit.

The present invention determines a time period in one cycle in which each CPU can access a common RAM based on the clock of a master CPU among a plurality of CPUs, accesses the common RAM during this period, communicates between the CPUs, and software The purpose is to save labor, increase speed, and easily connect multiple CPUs.

[Means to solve the problem]

Means for solving the problem will be explained with reference to FIG.

In FIG. 1, CPUI 2.3 is a CPU that performs inter-CPU communication.

The switch 4 is a switch that connects either an address bus or a data bus from a plurality of CPUs to the common RAM 6.

The switching control circuit 5 generates a switching signal for switching the switch 4.

Common RAM 6 is accessed by multiple CPUs and
This is memory for inter-communication.

[Effect]

As shown in FIG. 1, in the present invention, the switching control circuit 5 switches one of the address buses and data buses from the plurality of CPUs for one cycle based on the clock from the master CPU among the plurality of CPUs. A switching signal is supplied to the switch 4 to switch the data bus and address bus of the CPU designated by this switching signal to the common RAM 6. connect to,
The common RAM 6 is accessed to perform inter-CPU communication.

Therefore, each CPU accesses the common RAM 6 during the allocated time slot of one cycle generated based on the clock of the master CPU among the multiple CPUs, and the CPU
By performing inter-U communication, it becomes possible to save labor and speed up software, and to connect a large number of CPUs with a simple circuit configuration.

〔Example〕

Next, the configuration and operation of the embodiment of the present invention will be explained in detail using FIGS. 1 to 3.

FIG. 1 shows a configuration diagram of one embodiment of the present invention.

In FIG. 1, CPUI 2.3 is a CPU that constitutes a multi-CPU system, which accesses the common RAM 6 and communicates between CPUIs 2.3 and 2.3 to share processing. .

Here, it is assumed that the CPU3 is the master, and the CPUI and CPU2 are the slaves.

The switch 4 connects either the address bus or the data bus from the CPU 2.3 to the common RAM 6, and switches according to a switching signal from the switching control circuit 5.

The switching control circuit 5 generates a switching signal for switching the switching device 4 and a write/read signal to the common RAM 6. The switching control circuit 5 generates switching signals for switching the switching device 4 and write/read signals to the common RAM 6. Exclusively CPUI, 2.
The switch 4 is supplied with a switching signal to be switched during the time slots assigned to the RAM 3, respectively, and the write/read signal is supplied to the common RAM 6.

The common RAM 6 is used by CPU 2.3 to write messages, read messages addressed to itself, and
This is a readable and writable memory for communication between PUs.

Next, the operation of the configuration shown in FIG. 1 will be explained using the time chart shown in FIG.

In FIG. 2, ■The access signal (switching signal) to the common RAM of the CPU 3 is the access signal (write/read signal) supplied to the common RAM 6 by the switching control circuit 5 in FIG. 1 and the switching signal supplied to the switch 4. (L level is active). In response to the CPU 3 inputting an ON write/read signal to the switching control circuit 5, the address bus and data bus are connected to the common RAM 6 when this signal (■) is at L level, and the common RAM 6 is accessed during this time. do.

■The bus connection to the common RAM is made when the access signals (switching signals) of ■, ■, ■ are at L level,
．． 1.2 shows the state in which the address bus and data bus are connected to the common RAM. The CPU 3.1.2 accesses and performs inter-CPU communication during the time period when the address bus and data bus are connected to the common RAM 6.

(2) The clock of the CPU 3 is the clock of the master CPU 3, and based on this clock, time slots in one cycle in which (2), (2), and (2) are at L level are assigned.

■The access signal (switching signal) to the common RAM of the CPU is the access signal (write/read signal) supplied to the common RAM 6 by the switching control circuit 5 shown in FIG.
This is the switching signal supplied to the CPUI ON light/
In response to the input of the read signal to the switching control circuit 5, the address bus and data bus are connected to the common RAM 6 when the signal ① is at the L level, and during this period the common RAM
Access M6.

■The access signal (switching signal) to the common RAM of the CPU 2 is the access signal (write/read signal) supplied to the common RAM 6 by the switching control circuit 5 in FIG.
This is the switching signal supplied to the Light when CPU2 is ON/
In response to inputting the read signal to the switching control circuit 5, the address bus and data bus are connected to the common RAM 6 when the signal (①) is at the L level, and during this period, the common RAM
Access M6.

Through the above operations, the CPU 3.1.2 connects the address bus and data bus to the common RAM 6 and accesses it during the time period assigned to itself within one cycle.
．． Exchange messages between 1 and 2, and C
It becomes possible to perform communication between PUs.

FIG. 3 shows a time chart of a specific example. This is a time chart when three 68000 MPUs manufactured by Motorola are connected as shown in the configuration shown in FIG. CPU
3 as a mask, and using its basic clock and E clock, a predetermined time period in one cycle is set to CPU 3.1.
I am trying to assign each to 2. Here, a time period when the E clock is at the H level is assigned to the mask CPU 3, and a time period corresponding to one clock of the basic clock when the E clock is at the low level is assigned to the other CPUs 2, respectively. This will be explained below.

@CPU3 basic clock is the basic clock of CPU3 of the mask.

The OE clock is the E clock of the CPU 3 of the mask.

(2) Common RAM-5EL is a signal for selecting the common RAM 6 for the CPU 3 of the mask.

Specifically, they are a switching signal for connecting the address bus and data bus of the mask CPU 3 to the common RAM 6, and an access signal for accessing the common RAM 6.

[Phase] READ-Common RAM is a signal for reading and writing the common RAM 6. Here, it is an H bell and is a read signal. On the other hand, L bell is a write signal.

(2) CPU 1-ENB is a signal for selecting the common RAM 6 for the slave CPUI. Specifically, the switching signals for connecting the address bus and data bus of the slave CPU to the common RAM 6 and the common RAM 6
This is an access signal to access. Here, the E clock of the CPU 3 of the mask is set to the L level by one clock of the basic clock of the L level as shown in the figure, and the CPU accesses the common RAM 6 during this time.

@CPU2-ENB is a signal for selecting the common RAM 6 for the slave CPU2. Specifically, the address bus and data bus of slave CPU2 are connected to common R.
These are a switching signal for connecting to AM6 and an access signal for accessing this common RAM6. Here, C of the mask
As shown in the figure, the E clock of the PU 3 is set to the L level by one clock of the basic clock out of the L level, and the CPU 2 accesses the common RAM 6 during this period.

According to the time chart explained above, the CPU of the mask
While the E clock of No. 3 is at the H level, the address bus and data bus of the CPU 3 are connected to the common RAM 6 for access. On the other hand, the slave CPU 1. [By connecting and accessing the address bus and data bus of Jl and 2 to the common RAM 6, it is possible to create a simple hardware circuit without deteriorating software efficiency.
CPU3.1.2 via common RAM6
It becomes possible to communicate between

〔Effect of the invention〕

As explained above, according to the present invention, each CPU accesses the common RAM 6 during the allocated time slot of one cycle generated based on the clock of the mask CPU among the plurality of CPUs, Since it adopts a configuration that performs inter-CPU communication, it is possible to perform inter-CPU communication with less software, a speed amplifier, and a simple circuit configuration.

[Brief explanation of drawings]

11th! FIG. 2 is a time chart of the structure shown in FIG. 1. FIG. 3 is a time chart of a concrete example of the invention. FIG. 4 is a block diagram of a conventional CPU. In the figure, 1.2.3: CPU 4: Switching device (MPX) 5: Switching control circuit 6: Common RAM

Claims (1)

[Claims] Multi-CP that communicates between multiple CPUs via memory
In the U-system communication method, there is a common RAM (6) that is accessed by multiple CPUs for inter-CPU communication, and a switch that connects either the address bus or data bus from the multiple CPUs to this common RAM (6). a switch (4), and a switching control circuit (5) that generates a switching signal to switch the switching device (4), and the switching control circuit (5) generates a switching signal to switch the switching device (4) based on a clock from a master CPU of the plurality of CPUs. ) supplies a switching signal to the switching device (4) to switch one of the address buses and data buses from the plurality of CPUs during a pre-assigned time slot in one cycle, and the switching device The address bus and data bus of the CPU to which (4) applies are connected to common RAM.
(6), access the common RAM (6), and access the common RAM (6).
A communication method between multi-CPU systems, characterized in that the communication method is configured to perform communication between PUs.