JPH0221306A - Programmable controller - Google Patents

Abstract

PURPOSE:To improve the processing speed of the control data by incorporating a dual port memory to which two microprocessors has accesses at one time into a control unit. CONSTITUTION:Plural control units are attached to a base unit 3 having a common bus line and a dual port memory 62a is set at the single side of a control unit 6a which receives data via the common bus line. Then the simultaneous accesses are possible to the memory 62a via a microprocessor 61a contained in each unit 61a. Thus the memory 62a can receive accesses from two processors at one time. As a result, plural microprocessors 61a can have the simultaneous accesses to the memory 62a with no waiting time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a programmable controller, and more particularly to a programmable controller in which a data memory in a control unit constituting the programmable controller is configured with a dual port memory.

(Prior Art) Figure 3 is an overall outline drawing of a conventional programmable controller. In the figure, (1) is a base unit to which each unit is attached, (2) is a power supply unit, (3)
is the sequencer CPU unit, (4) is the input crab unit,
(5) is an output crab unit, and (6) is a special function unit.The special function units can be categorized into positioning units, analog input crab units, analog output crab units,
The units are classified into counter units, display units, etc., and the units are replaced as necessary. In addition, the sequencer CPU unit (1) and special function unit (
6) are coupled via the base unit (1), so the sequencer CPU unit (3) can access the memory (RAM) built in the special function unit (6).

FIG. 4 is a diagram showing the internal configuration of the special function unit (6) and the connection relationship between the special function unit (6) and the sequencer CPU unit (3). The special function unit (6) includes a microprocessor (61), a RAM (62), a selector (63) that selects an access signal for this RAM (62), and a RAM (63) from the microprocessor (61) via the selector (63).
A bus (64) that sends an access signal to the RAM (62), a bus (64) that sends an access signal from the sequencer CPU unit (3) to the RAM (62) via the selector (63)
1).

Next, the operation of the conventional programmable controller will be explained based on the above configuration.

The sequencer CPU unit (3) is a special function unit (
6), the microprocessor (61) in the special function unit (6) has already accessed the RAM (62) via the bus (64).
While the AM (62) is being accessed, the sequencer CPt1 unit (3) is made to wait for the RAM (62) to be accessed. and special function unit (6
) completes accessing the RAM (62), the microprocessor (61) switches the selector (63) so that the bus (31) from the sequencer CPU unit (3) and the bus of the RAM (62) (65) and connect it to the sequencer CPU unit (3).
The RAM (62) in the special function unit (6) can be accessed from.

[Problem to be solved by the invention]

In conventional programmable controllers, the microprocessor of the special function unit has the initiative in accessing the RAM, so when the sequencer CPU unit accesses the RAM of the special function unit, the microprocessor of the special function unit is accessing the RAM. In this case, the sequencer CPU unit is forced to wait for accessing the RAM, and there is a problem in that it takes time to start accessing.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a programmable controller that allows a sequencer CPU unit to access the RAM of a special function unit without waiting time.

[Means to solve the problem]

A programmable controller according to the present invention includes a plurality of control units mounted on a base unit having a common bus line, a dual port memory built in one of the control units that exchanges data via the common bus line, and each control unit The dual-port memory can be accessed simultaneously by the built-in microprocessor.

(Operation) According to the present invention, since the dual port memory can receive access from two processors simultaneously,
Each microprocessor can access dual-port memory simultaneously with no wait time.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows the connection relationship between the special function unit (6a) and the sequencer CPU unit (3) in this embodiment. In the figure, (3) is a sequencer CPU unit;
(31) is a bus line, (6a) is a special function unit,
(61a) is a microprocessor, (82a) is a dual port RAM, and (65a) is a bus line.

FIG. 2 is a diagram showing in detail the configuration of each bus (31) and (65a) shown in FIG. 1. In the figure, (31^) is the dual port R from the sequencer CPU unit (3).
an address bus (31) that outputs a signal specifying an address when accessing a specific address of AM (62a);
0) is a data bus that carries data to be written or read at a specified address, and (31G) is a control bus that includes a chip select signal line that selects the memory, a read signal line that commands data reading, and a data bus. It consists of a write signal line that commands writing. (6
5^) is an address bus on the microprocessor (61a) side, (65D) is a data bus, and (65C) is a control bus. In the programmable controller of this embodiment, the memory access time of the microprocessor (81a) in the special function unit (6a) is faster than the memory access time of the sequencer CPU unit (3). Even if both 6a) and the sequencer CPU unit (3) try to write data to the same address in the dual port RAM (62a) at the same time, a data conflict will occur in the dual port RAM (62a) due to the difference in access time. do not.

Next, the operation will be explained. Microprocessor (61
In order to write data from a) to an address in the dual port RAM (62a), the microprocessor (
81a) first sends the address signal of the address to write data to the dual port RAM (62a) using the address bus (65^), and also sends the chip select signal to the dual port RAM (62a) using the chip select signal line.
M (62a), the address is determined, and then the microprocessor (61a) uses the data bus (65D) to send the write data to the dual port RAM (62a).
) and output a write signal through the write signal line, data can be written to any address of the dual port RAM (62A). Also, from the microprocessor (ATA) to the dual port RAM (62a
), the microprocessor (61a) first uses the address bus (65^) to send the address signal of the address on the dual port RAM (62a) in which the data to be read is stored to the dual port address bus (65^). Dual port R sends a chip select signal to the chip select signal line while sending it to the RAM (62a).
AM (62a), the address is determined, and then the microprocessor (61a) outputs a read signal to the read signal line to read the dual port RAM (82a).
outputs the data stored at the address specified by the address signal to the data bus (65D), so the microprocessor (61a) reads this data.

Similarly to the above microprocessor (61a), the dual port RAM (62) is connected to the sequencer CPU unit (3).
a) When writing data to the programmable controller CPU unit (3), send the address signal of the address at which data is to be written to the sequencer CPU unit (3) via the address bus (31A), and
Data can be written to any address of the dual port RAM (62a) by sending a chip select signal to the chip select signal line, then sending the data to be written to the data bus (310) and sending a write signal to the write signal line. can. In addition, the sequencer CPU unit (3
) to read data stored at an arbitrary address in the dual port RAM (62a), send the address signal to the address bus (31A) and send the chip select signal to the chip select signal line to confirm the address and read. Data stored at any address in the dual port RAM (62a) can be read by issuing a read signal to the signal line.

Now, the microprocessor (61) and the sequencer CPU
If you try to write different data to the same address from unit (3) at the same time, the sequencer CPU unit (
3) Access time from special function unit (6a)
Data contention does not occur within the dual baud 1-RAM (62a) since it takes more time than the built-in microprocessor (61a).

(Effects of the Invention) As described above, according to the present invention, the memory that two control units access each other among the plurality of control units constituting the programmable controller is made into a dual port memory, so that each control unit can communicate with each other. This eliminates the access waiting time of waiting for the completion of the memory access operation before starting the access, and allows each control unit to access the memory at the same time, which has the effect of improving the control data processing speed.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a memory access circuit in a programmable controller according to an embodiment of the present invention, FIG. 2 is a bus connection diagram between a dual port RAM and each unit,
FIG. 3 is an overall configuration diagram of a programmable controller, and FIG. 4 is an internal configuration diagram of a conventional special function unit. In the figure, (3) is a sequence CPU unit, (8
a) is a special function unit, (6ta) is a microprocessor, (62a) is a dual port RAM, (31
), (85a) is a bus. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] Multiple control units with built-in microprocessors,
In a programmable controller attached to a base unit that has a common bus line for each control unit, two
A programmable controller that features a control unit with a built-in dual-port memory that can be accessed simultaneously by two microprocessors.