JP2825914B2 - Communication system between processors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to an inter-processor communication method for performing communication between arbitrary processors in a multiprocessor system.

(Prior Art) FIG. 4 is a block diagram showing a configuration of a conventional interprocessor communication system for performing communication between processors in a multiprocessor system including two processors.
In the figure, a first processor (CPU1) 111 and a second processor (CPU2) 211 are connected to a system bus (SBUS) 1.
They are connected so that they can communicate with each other via 40.

The first processor (CPU 1) 111 includes a first central control unit (MPU 1) 112, a first chip bus (CBUS 1) 113 which is an internal bus of the first processor (CPU 1) 111, Chip bus (CBUS1) 113 and system bus (SBUS) 140
Bus conversion control unit (BC)
1) 115, and a first inter-processor communication control unit (PCTL1) 114 for communication between processors. The first inter-processor communication control unit (PCTL1) 114 stores a first transmission command register (CM
DSR1) 122 and the first transmission command register (CMDSR
1) A first command extraction control unit (CSRS1) 121 for extracting and transmitting a command from the 122, and a first command writing control unit (CSRS1) for writing a command to the first transmission command register (CMDSR1) 122. CSRW1) 123
Indicates whether the transmitted command has been completed normally,
A first flag (ENDF1) 125 that is set to [0] at the time of normal termination, and is set to “1” at the time of abnormal termination, and a first read control unit (READ) for reading from the first flag (ENDF1) 125 EFR1) 124 and a first for writing a flag in the first transmission command register (CMDSR1) 122.
Flag write control unit (EEW1) 126 and a first received command register (CMDRR
1) 128 and the first received command register (CMDRR1)
A first command read control unit (CRRR1) 127 for reading a command from the first 128; a first command write control unit (CRRW1) 129 for writing a command to the first received command register (CMDRR1) 128; It is composed of

The second processor (CPU2) 211 is configured in the same manner as the first processor (CPU1) 111, and the components of the first processor (CPU1) 111 starting from the hundredth are denoted by the second processor (CPU1). In the CPU2) 211, the same reference numerals starting from the 200th generation are indicated by the same reference numerals, and the numbers at the end of the symbols, such as CPU1, also indicate that the component in the first processor (CPU1) 111 is "1". In the second processor (CPU2) 211, the difference is “2”.

FIG. 5 is a diagram showing the flow of signals on the bus for inter-processor communication in FIG. 4. Next, referring to FIG. 5, the first processor (CPU1) 111 to the second processor (CPU
2) The operation when communication is performed with 211 will be described. The fifth
In the figure, thin solid arrows indicate bus access signals, dotted arrows indicate bus access completion signals, thick lines indicate data, and hatched portions indicate bus suspension.

In step 1 of FIG. 5, the first central control unit (MP
As shown by U1) 112, the first chip bus (CBUS1) 11
3 and the first transmission command register (CMDSR1) via the first command writing control unit (CSRW1) 123 of the first interprocessor communication control unit (PCTL1) 114 as indicated by "1". A command for inter-processor communication is written in 122, and the first inter-processor communication control unit (PCTL1) 114 is instructed to execute inter-processor communication. When the command writing is completed, the first inter-processor communication control unit (PCTL1) 114 switches the first central control unit (MPU) as shown in FIG.
1) Notify 112 of the completion of the bus access and release the first chip bus (CBUS1) 113.

Next, in step 2, the first inter-processor communication control unit (PCTL1) 114 secures the first chip bus (CBUS1) 113 as shown by (1), and the first bus conversion control as shown by "2". The contents of the first transmission command register (CMDSR1) 122 are transferred to the second processor (CPU1).
2) Instruct interprocessor communication with 211. Thereafter, the first inter-processor communication control unit (PCTL1) 114 holds the first chip bus (CBUS1) 113.

In step 3, the first bus conversion control unit (BC
1) A system bus (SBUS) 140 is secured as indicated by 115, and a second bus conversion controller (BC) is indicated as indicated by “3”.
2) Transfer the command to the 215, receive the completion of the bus access from the second bus conversion control unit (BC2) 215 as shown in (B), and release the system bus (SBUS) 140.

Further, in step 4, as indicated by the second bus conversion control unit (BC2) 215, the second chip bus (CBUS)
2) Reserve 213 and register the second received command register (CMDRR2) via the second command write control unit (CRRW2) 229 of the second inter-processor communication control unit (PCTL2) 214 as indicated by “4”. ) Write the command to 228. Upon completion of the command writing, the second bus conversion control unit (BC2) 215
Receives the completion of the bus access from the second inter-processor communication control unit (PCTL2) 214 as shown in FIG.
The chip bus (CBUS2) 213 is released. If the command cannot be written, the second bus conversion control unit (BC2) 2
15 receives the abnormal completion of the bus access from the second inter-processor communication control unit (PCTL2) 214 and releases the second chip bus (CBUS2) 213 as shown in FIG.

In step 5, the second bus conversion control unit (BC
2) The system bus (SBUS) 140 is secured as indicated by 215, and the first bus conversion controller (BC) is indicated as indicated by “5”.
1) Writing of commands to 115 ends normally ((C)
(When (C) is abnormal completion) is transferred, and completion of bus access from the first bus conversion control unit (BC1) 115 is received as shown in (D) as shown in (D). Then, the system bus (SBUS) 140 is released.

In step 6, as shown in (E), the first bus conversion control unit (BC1) 115 sends a bus access request to the first inter-processor communication control unit (PCTL1) 114 according to the answer indicated by "5". Notifies normal / abnormal completion. The first inter-processor communication control unit (PCTL1) 114 receives this bus access completion signal and releases the first chip bus (CBUS1) 113. In the first inter-processor communication control unit (PCTL1) 114, via the first flag write control unit (EFW1) 126,
If the inter-processor communication has been completed normally, "0" (normal end flag) is written to the first flag (EMDF1) 125, and if it has ended abnormally, "1" (abnormal end flag) is written. .

FIG. 6 is a flow chart showing the operation at the time of communication between processors in the bus conversion control unit. FIG. 6 (a) shows the bus conversion control unit (BC1, BC1) from the chip buses (CBUS1,2) 113,213.
2) It is a flowchart when there is access to 115 and 215, and FIG. 6 (b) is a flowchart when there is access from the system bus (SBUS) 140 to the bus conversion control units (BC1, 2) 115 and 215.

First, referring to FIG. 6 (a), the chip bus (CBUS1,
2) A case where the bus conversion control units (BC1, 2) 115 and 215 are accessed from 113 and 213 will be described.

When the chip bus (CBUS1,2) 113,213 accesses the bus conversion control unit (BC1,2) 115,215, the chip bus (CB
US1,2) Receives command data from 113,213 (step
510), secure system bus (SBUS) 140 (step)
520). Command data is transferred to the partner bus conversion control units (BC2, 11) 215, 115 (step 530), and a bus access completion signal is waited for from the partner bus conversion control units (BC2, 1) 215, 115 (step 540). SBUS) 140 is released (step 550). The other party's bus conversion control unit (BC2,1) 21
Wait for answer data from 5,115 (step 560), send a bus access completion signal to the other bus conversion control unit (BC2,11) 215,115 (step 570), and send the system bus (S
A bus access completion signal is sent to the (BUS) 140 (step 580).

Next, referring to FIG. 6 (b), the system bus (SBUS)
A case where the bus conversion control units (BC1, 2) 115 and 215 have access from 140 will be described.

From the system bus (SBUS) 140 to the bus conversion controller (BC1,
2) When access is made to 115 and 215, command data is received (step 610), and the other bus conversion control unit (BC2, 1) 21
A bus access completion signal is sent to 5,115 (step 62
0), and secure chip buses (CBUS1,2) 113,213 (step 630). Then, the control unit for communication between processors (PCT
L1, 2) Transfer the command data to 114, 214 (step 64)
0), waits for a bus access completion signal from the inter-processor communication control units (PCTL1, 2) 114, 214 (step 650), and releases the chip buses (CBUS1, 2) 113, 213 (step 660)
A system bus (SBUS) 140 is secured (step 670).
If a normal end is received from the inter-processor communication control units (PCTL1, 2) 114, 214, the process proceeds to step 690, where the normally-completed answer data is transferred to the partner bus conversion control units (BC2, 1) 215, 115; If an abnormal end is received from the interprocessor communication control units (PCTL1,2) 114,214 in step 680, the process proceeds to step 700, and the abnormal end answer data is transferred to the partner bus conversion control units (BC2,1) 215,115. I do. It waits for a bus access completion signal from the partner bus conversion controller (BC2,1) 215,115 (step 710), and releases the system bus (CBUS) 140 (step 720).

(Problems to be Solved by the Invention) As described above, in the conventional inter-processor communication via the interlock type chip bus, due to the characteristics of the chip bus, a response to a command is a response signal and a signal indicating whether or not the command is normal. However, there is a problem that it is not possible to return a plurality of types of responses (for example, communication buffer full, processor stopped, bus failure, etc.) according to the state of the partner processor.

In addition, during the period from issuing a command to receiving an answer, the chip bus of the transmitting processor is suspended and unusable, and devices on the chip bus may perform other processing using the chip bus. There is a problem that can not be.

Furthermore, if the system bus cannot be secured at the time of answer transfer, the receiving processor enters a waiting state until the system bus can be secured, and there is a problem that other processing cannot be performed.

The present invention has been made in view of the above, and an object of the present invention is to provide an inter-processor communication method capable of enabling a plurality of responses according to the state of a partner processor and improving the use efficiency of the processor. Is to provide.

[Configuration of the invention]

(Means for Solving the Problems) In order to achieve the above object, an inter-processor communication system of the present invention provides a multi-processor system that continuously transmits a command and receives an answer to the command on a chip bus which is a bus in the processor. In the system bus which is a bus between the processors, the bus is released once after transmitting the command to transmit the command and receive the answer to the command, and another bus control operation is performed. An inter-processor communication system that has a bus conversion circuit between a chip bus and a system bus and an inter-processor communication circuit on the chip bus, and performs communication between arbitrary processors. When the conversion circuit receives bus access from the chip bus by inter-processor communication, A chip bus releasing means for returning an access completion to the chip bus and releasing the chip bus; an answer holding means provided in the inter-processor communication circuit for holding a plurality of answers to the received command; Reply, release the chip bus, create an answer,
The gist of the present invention is to have an answer registering means for registering the answer in the answer holding means, and a transmitting means for taking out the answer from the answer holding means and transmitting the answer.

(Operation) In the inter-processor communication system of the present invention, when the bus access by the inter-processor communication from the chip bus is received, the access completion is returned to the chip bus to release the chip bus, and an answer provided in the inter-processor communication circuit is provided. The holding means holds a plurality of answers to the received command, returns an access completion upon receiving the command, releases the chip bus, creates an answer, registers the answer in the sending answer holding means, and retrieves the answer from the sending answer holding means. Sending.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of an inter-processor communication system according to an embodiment of the present invention. The inter-processor communication method shown in FIG. 1 is applied to a multiprocessor system including two processors and a common bus connecting the two processors. In the figure, the first processor (CP
The U1) 10 and the second processor (CPU2) 20 are connected so as to be able to communicate with each other via a system bus (SBUS) 30.

The first processor (CPU1) 10 includes a first central control unit (MPU1) 101, a first chip bus (CBUS1) 103 which is an internal bus of the first processor (CPU1) 10, and a first Chip bus (CBUS1) 103 and system bus (SBUS) 30
Bus control unit (XBC1) 10 for controlling connection of a bus between
5 and a first inter-processor communication control unit (PCTL1) 104 for communication between processors. The first inter-processor communication control unit (PCTL1) 104 includes a first transmission command holding queue (CMDSQ1) 142 that holds a plurality of transmission commands, and a first transmission command holding queue (C
MDSQ1) First for extracting and sending commands from 142
Command fetch control unit (CSQS1) 141 and a first command write control unit (CSQW1) 143 for writing a command to the first transmission command holding queue (CMDSQ1) 142
A first received answer holding queue (ANSRQ1) 145 for holding a plurality of answers received in response to the transmission command;
First answer read control unit (ARQR1) 144 for reading an answer from the reception answer holding queue (ANSRQ1) 145
And a second answer writing control unit (ARQW) for writing an answer in the first reception answer holding queue (ANSRQ1) 145.
1) 146, a first received command holding queue (CMDRQ1) 148 that holds a plurality of received commands, and a first answer read control unit (READ) for reading an answer from the first received command holding queue (CMDRQ1) 148. CRQR1) 147 and the first
Answer writing control unit (CRQW1) 149 for writing an answer to the received command holding queue (CMDRQ1) 148
A first transmission answer holding queue (ANSSQ1) 151 for holding a plurality of answers to be transmitted in response to a reception command;
Answer reading control unit (ASQR1) 150 for reading an answer from the transmission answer holding queue (ANSSQ1) 151
And a first answer write control unit (ANQW) for writing an answer to the first transmission answer holding queue (ANSSQ1) 151.
1) 152.

The second processor (CPU2) 20 is configured in the same manner as the first processor (CPU1) 10, and the components of the first processor (CPU1) 10 starting from the hundredth are denoted by the second processor (CPU1). In the CPU 2) 20, the same reference numerals starting from the 200th generation are used, and the numbers at the end of the symbols, such as CPU1, also indicate that the component in the first processor (CPU1) 10 is "1". , The second processor (CPU2)
20 is different in that it is “2”.

FIG. 2 is a diagram showing a signal flow on a bus for inter-processor communication in FIG. 1. Next, referring to FIG. 2, a first processor (CPU1) 10 to a second processor (CPU
2) The operation when communication is performed at 20 will be described. The second
In the figure, thin solid arrows indicate bus access signals, dotted arrows indicate bus access completion signals, thick lines indicate data, and hatched portions indicate bus suspension.

In step 1 of FIG. 2, the first central control unit (MP
U1) As shown by 101, the first chip bus (CBUS1) 10
3 and the first transmission command holding queue (CMDSQ1) 142 via the first command writing control unit (CSQW1) 143 of the first inter-processor communication control unit (PCTL1) 104 as indicated by “1”. A command for inter-processor communication is written in the command line, and the first inter-processor communication control unit (PCTL1) 104 is instructed to execute inter-processor communication. When the command writing is completed, the first inter-processor communication control unit (PCTL1) 104, as shown in FIG.
1) Notify 101 of the completion of the bus access and release the first chip bus (CBUS1) 103.

Next, in step 2, the first inter-processor communication control unit (PCTL1) 104 secures the first chip bus (CBUS1) 103 as shown by (1), and the first bus control unit (2) as shown by (2). (XBC1) 105 stores the first transmission command holding queue (C
MDSQ1) Transfers the contents of 142 to the first processor (CPU1)
Instructs inter-processor communication with 10 and receives the completion of the bus access from the first bus control unit (XCB1) 105 as shown in (B), and releases the first chip bus (CBUS1) 103.

In step 3, the first bus control unit (XBC1) 10
5 secure system bus (SBUS) 30 as shown by
The command is transferred to the second bus control unit (XBC2) 205 as indicated by “3”, and the completion of the bus access from the second bus control unit (XBC2) 205 is received as indicated by (C). ,
Release the system bus (SBUS) 30.

Further, in step 4, the second bus control unit (XBC
2) The second chip bus (CBUS2) 203 as indicated by 205
And the second received command holding queue (CM) via the second answer write control unit (CRQW2) 249 of the second inter-processor communication control unit (PCTL2) 204 as indicated by “4”.
DRQ2) Write the command to 248. When the writing of the command is completed, the second bus control unit (XBC2) 205
As shown in the figure, the second inter-processor communication control unit (PCTL
2) Upon receiving the completion of the bus access from 204, the second chip bus (CBUS2) 203 is released. The second inter-processor communication control unit (PCTL2) 204 generates an answer code according to the state of the second processor (CPU2) 20 at the time of receiving the command, and registers the answer code in the second transmission answer holding queue (ANSSQ2) 251. .

Also, in step 5, the second inter-processor communication control unit (PCTL2) 204 secures the second chip bus (CBUS2) 203 as indicated by the symbol and holds the second transmission answer as indicated by the symbol "5". The answer in the queue (ANSSQ2) 251 is transferred to the second bus control unit (XBC2) 205, and the bus access from the second interprocessor communication control unit (PCTL2) 204 is completed as shown in (E). And the second chip bus (CB
US2) Release 203.

In step 6, the second bus control unit (XBC2) 205
Secure system bus (SBUS) 30 as shown by
The answer is transferred to the first bus control unit (XBC1) 105 as indicated by “6”, and the completion of the bus access from the first bus control unit (XBC1) 105 is received as indicated by (F). Then, the system bus (SBUS) 30 is released.

Further, in step 7, the first bus control unit (XBC
1) The first chip bus (CBUS1) 103 as indicated by 105
And the first reception answer holding queue (ANSR) via the second answer writing control unit (ARQW1) 146 of the first inter-processor communication control unit (PCTL1) 104 as shown by “7”.
Q1) Write an answer to 145, and first answer as shown in (G).
Of the bus access from the inter-processor communication control unit (PCTL1) 104 of the first chip bus (CBUS1) 103
To release.

FIG. 3 is a flowchart showing the operation of the bus control units (XBC1, 2) 105, 205 at the time of communication between the processors. FIG. 3 (a) shows the chip buses (CBUS1, 2) 103, 203 to the bus control units (XBC1, 2). FIG. 3B is a flowchart in the case where access is made to 105 and 205, and FIG.
9 is a flowchart in the case where the US) 30 accesses the bus control units (XBC1, 2) 105 and 205.

First, referring to FIG. 3 (a), the chip bus (CBUS1,
2) The case where the bus control units (XBC1, 2) 105 and 205 are accessed from 103 and 203 will be described.

Bus control unit (XBC) from chip bus (CBUS1,2) 103,203
1,2) When there is access to 105,205, the chip bus (CBUS1,
2) Receiving a command or answer data from 103, 203 (step 310) and sending a bus access completion signal to chip buses (CBUS1, 2) 103, 203 (step 320)
The system bus (SBUS) 30 is secured (step 330).
The command or answer data is transferred to the partner bus control unit (XBC2, 1) 205, 105 (step 340), a bus access completion signal is waited from the partner bus control unit (XBC2, 1) 205, 105 (step 350), and the system bus ( SBUS) 30 is released (step 360).

Next, referring to FIG. 3 (b), the system bus (SBUS)
The case where the bus control units (XBC1, 2) 105, 205 are accessed from 30 will be described.

System bus (SBUS) 30 to bus controller (XBC1, 2) 10
When 5,205 is accessed, a command or answer data is received (step 410), and the other bus control unit (XBC2,
1) Send a bus access completion signal to 205 and 105 (step
420), and secure chip buses (CBUS1, 2) 103, 203 (step 430). Inter-processor communication control unit (PCTL1,2) 10
The command or answer data is transferred to 4,204 (step 440), and the inter-processor communication control units (PCTL1,2) 104,20
4 waits for a bus access completion signal (step 450), and releases the chip buses (CBUS1, 2) 103, 203 (step 46).
0).

In the above embodiment, the case where the number of processors is two has been described. However, the present invention is not limited to this, and it goes without saying that three or more processors can be similarly applied.

〔The invention's effect〕

As described above, according to the present invention, when the bus access by the inter-processor communication from the chip bus is received, the access completion is returned to the chip bus to release the chip bus, and the answer provided in the inter-processor communication circuit is provided. The holding means holds a plurality of answers to the received command, returns an access completion upon receiving the command, releases the chip bus, creates an answer, registers the answer in the sending answer holding means, and retrieves the answer from the sending answer holding means. Because of the transmission, in the inter-processor communication, a plurality of types of responses can be made to the transmitting processor in accordance with the state of the receiving processor, and the transmitting processor transmits the command to the chip bus at the time of transmitting the command. To improve chip bus throughput and processor utilization Rukoto can. Furthermore, the processor on the receiving side can execute the following processing without ending the transmission of the answer when the answer is registered in the answer transmission queue.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an inter-processor communication system according to an embodiment of the present invention, FIG. 2 is a diagram showing a signal flow on a bus for inter-processor communication in FIG. 1, and FIG. Bus control unit (XBC) for inter-processor communication system in Fig. 1
And FIG. 4 is a block diagram showing a configuration of a conventional inter-processor communication system for performing communication between processors in a multiprocessor system including two processors.
FIG. 4 is a diagram showing a signal flow on a bus for inter-processor communication in FIG. 4, and FIG. 6 is a flowchart showing an operation at the time of inter-processor communication in a bus conversion control unit of the inter-processor communication system in FIG. 10,20 Processor (CPU), 30 System bus (SBUS), 101,201 Central control unit (MPU), 103,203 Chip bus (CBUS), 104,204 Communication control unit between processors (PCTL) , 105,205… Bus control unit (XBC), 141, 241… Command fetch control unit (CSQS), 142, 242… Transmission command holding queue (CMDSQ), 143, 243… Command write control unit (CSQW), 144, 244… Answer read control 145,245 ... Reception answer holding queue (ANSRQ), 146,246 ... Answer writing control unit (ARQW), 147,247 ... Answer reading control unit (CRQR), 148,248 ... Reception command holding queue (CMDRQ), 149,249 … Answer writing control unit (CRQW), 150,250… Answer reading control unit (ASQR), 151,251… Transmission answer holding queue (ANSSQ), 152,252… Answer writing control unit (ASQW).

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 15/16

Claims (1)

(57) [Claims] In a multiprocessor system, a chip bus which is a bus in a processor uses an interlock system in which transmission of a command and reception of an answer to the command are performed by a continuous bus control operation, and the system is a bus between processors. In the bus, the command is transmitted and the answer to the command is received. After transmitting the command, the bus is released once, and a separate bus control operation is used.A bus conversion circuit and a bus conversion circuit are provided between the chip bus and the system bus. Having an inter-processor communication circuit on a chip bus,
An inter-processor communication method for performing communication between arbitrary processors, wherein when the bus conversion circuit receives a bus access from the chip bus by inter-processor communication, an access completion is returned to the chip bus and the chip bus is released. A chip bus releasing unit, an answer holding unit provided in the inter-processor communication circuit, for holding a plurality of answers to the received command, returning an access completion upon receiving the command, releasing the chip bus, and creating an answer; Answer registration means for registering in the answer holding means;
Transmitting means for extracting an answer from the answer holding means and transmitting the answer.