JP3351581B2 - Data relay device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data relay device applicable to a LAN connection device and a communication device.

[0002]

2. Description of the Related Art As a conventional LAN connection device, a device having a single microprocessor is known. As shown in FIG. 8, for example, this type of LAN connection device has a bus 83 connected to a microprocessor 81, a reception interface 85, and a transmission interface 84, and the microprocessor 81 has a memory. 82
Is connected. The receiving interface 85 is a LAN
Receiving the frame from A, the microprocessor 8
Interrupt 1 and pass the frame. The microprocessor 81 receives the frame, stores it in the memory 82, determines the type of the frame, checks the validity of the frame, determines the relay destination based on the destination address, and the like, and transmits the interface 84 via the bus 83. To LA
NB.

However, according to the inter-LAN connecting device using a single microprocessor, the reception and processing of the next frame cannot be performed between the reception and transmission of one frame. There was a problem that it did not rise.

Therefore, as shown in FIG.
And a system configuration in which two microprocessors 91 and 92 are connected. In this inter-LAN connecting apparatus, when the receiving interface 93 receives a frame from the LAN-A, it is sent to the microprocessor 91, where processing such as discrimination of the type of the frame and checking of the validity of the frame is performed. Is executed, and the processed frame is stored in the memory 90 under the control of the bus controller 96. Microprocessor 92
Under the control of the bus controller 96,
Is read out, the relay destination is determined from the destination address, etc., and given to the transmission side interface 94 to be transmitted to the LAN-B.

[0005]

In this LAN connection apparatus, two microprocessors are used to determine the type of frame, check the validity of the frame, and determine the relay destination based on the destination address. In terms of sharing and executing, the throughput is improved as compared with the inter-LAN connecting device of FIG. However, even in the LAN connection apparatus using the two microprocessors, the two microprocessors cannot use the bus 95 at the same time, and the adjustment by the control of the bus controller 96 is necessary. The improvement is impeded.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the conventional data relay device, and has as its object to receive a data block, perform a reception process such as a data block validity check, and relay the data block. It is another object of the present invention to provide a data relay device capable of simultaneously performing transmission processing for transmitting data to the second system and transmission of a data block.

[0007]

Therefore, in the present invention, the first invention
A receiving interface for receiving a data block arriving from the system, and a receiving processing unit for performing reception processing on the data block received by the receiving interface;
Transmission processing means for performing transmission processing on the data block for relaying the data block processed by the reception processing means and transmitting the data block to the second system; and transmitting the data block processed by the transmission processing means to the second system. A transmission interface to transmit to the system, the reception interface, the reception processing means, the transmission processing means, buses connected to each of the transmission interfaces, at least as many memories as the number of the buses, the reception interface, Each time the address of the memory was output from each of the reception processing unit, the transmission processing unit, and the transmission interface, the memory was connected to the reception interface, the reception processing unit, the transmission processing unit, and the transmission interface. Bus switching for switching the connection relationship between a bus and the memory To constitute a data relay apparatus by and a stage.

Further, according to the present invention, a memory group composed of four or more memories having pages for storing data blocks related to processing and a data block coming from the first system are received and stored in a predetermined order. A receiving interface for outputting an address specifying a page to be provided, and the receiving interface is provided with page information of a storage destination for the received data block, and an address specifying this page is output and stored in the corresponding page. Receiving processing means for receiving and processing data blocks stored therein, and page information of a storage destination for the data blocks processed by the receiving processing means, and outputting an address designating this page to store the data block in the corresponding page. A transmission process for relaying the data block and transmitting the data block to the second system; Transmission processing means for performing the data processing, and receiving the page information of the storage destination of the data block processed by the transmission processing means, outputting an address designating the page, and outputting the data block stored in the corresponding page to the data block. A transmission interface for transmitting to the second system, the reception interface, the reception processing means, the transmission processing means, a bus connected to each of the transmission interfaces, the reception interface, the reception processing means, the transmission processing means, Each time the address of the memory is output from each of the transmission interfaces,
A data relay device comprising the reception interface, the reception processing unit, the transmission processing unit, and a bus switching unit for switching a connection relationship between a bus connected to each of the transmission interfaces and a memory of the memory group. did.

[0009]

According to the first aspect of the present invention, there are provided a reception interface, a reception processing means, a transmission processing means, a transmission interface, and buses respectively connected thereto, and at least as many memories as the number of the buses. Each time the address of the memory is output from each of the reception interface, the reception processing unit, the transmission processing unit, and the transmission interface, the reception interface, the reception processing unit, the transmission processing unit, and the transmission interface Since the connection relationship between the connected bus and the memory is switched, the reception interface, the reception processing means, the transmission processing means, and the transmission interface are connected to necessary memories one after another only by outputting an address. , Using this memory to receive data blocks, Receiving process validation, etc. of the lock, the transmission process for transmitting by relaying the data block to the second system, the transmission of data blocks, respectively, and capable of performing at the same time.

According to the second invention, the memory to which the reception interface, the reception processing means, the transmission processing means, and the transmission interface are connected via the respective buses has a page, and the page corresponding to the page is provided. Information is sequentially received from the reception interface, reception processing means, transmission processing means,
By being sent to the transmission interface, it is guaranteed that the data blocks are processed and relayed in the order of arrival. Then, each time an address corresponding to the page information of the memory is output from each of the reception interface, the reception processing means, the transmission processing means, and the transmission interface, the reception interface, the reception processing means, the transmission processing Since the connection relationship between the bus and the memory connected to each of the means and the transmission interface is switched, the reception interface, the reception processing means, the transmission processing means, and the transmission interface output an address corresponding to the page information. Only, the required memory (desired page) is connected one after another, and using the page of this memory, the receiving process such as the reception of the data block, the validity check of the data block, the relay of the data block, and the like. The transmission processing and transmission of data blocks for transmission to the It makes it possible to carry out respectively at the same time.

[0011]

Embodiments of the present invention will be described below with reference to the accompanying drawings. Here, an inter-LAN connection device as a data relay device will be described. In each drawing, the same components are denoted by the same reference numerals, and redundant description will be omitted. FIG. 1 illustrates a configuration diagram of the LAN connection apparatus according to the embodiment. In the figure, a receiving interface 3 is connected to LAN-A, and a transmitting interface 8 is connected to LAN-B. Microprocessor 5
Is a processor that executes reception processing such as discrimination of the type (type) of the received frame and checking of the validity of the frame with respect to the received frame.
Is a processor that executes transmission processing such as determination of a relay destination from a destination address. The microprocessors 5 and 7 store programs and data used for the above treatment, respectively, and have a main memory 4 provided with a working area.
6 are connected to each other.

The page information of the storage destination of the received frame is transmitted from the reception interface 3 to the microprocessor 5 via the line 31, and the page information of the storage destination of the received frame is received from the microprocessor 5 to the microprocessor 7. Is sent via the line 51, and the page information of the storage destination of the frame transmitted from the microprocessor 7 to the transmission interface 8 is stored in the line 71.
Sent through. An address bus and a data bus are connected to the reception interface 3, the microprocessor 5, the microprocessor 7, and the transmission interface 8, respectively.
0, and the data buses constitute a data bus group 11. The address bus group 10 and the data bus group 11 extend to two memory blocks 1-1 and 1-2, respectively, and are connected to the reception interface 3, the microprocessor 5, the microprocessor 7, and the transmission interface 8, respectively. A part of the address bus (for example, several bits from the MSB) is connected to the switching control circuit 9. The switching control circuit 9 responds to a signal provided from a part of each address bus connected to the reception interface 3, the microprocessor 5, the microprocessor 7, and the transmission interface 8 in accordance with a signal supplied from the memory blocks 1-1, 1-2. Bus selection signals for switching the connection relationship between the respective memories and the respective address buses and data buses connected to the reception interface 3, the microprocessor 5, the microprocessor 7, and the transmission interface 8, respectively. -2.

FIG. 2 shows a configuration diagram of the memory block 1-1. Here, an example is shown in which the memory block 1-1 includes four data memories DM1 to DM4. Each of the data memories DM1 to DM4 has a plurality of pages 1, page 9, page 17,.
..., page 2, page 10, page 18, ..., page 3, page 11, page 19, ..., page 4, page 12, page 20, ... used. The address bus connected to each of the data memories DM1 to DM4 is a bus switch 2
The data bus connected to the data memory terminal 1-1 and the data memories DM1 to DM4 is connected to the data memory terminal of the bus switch 22-1. The bus changeover switch 21-1 and the bus changeover switch 22-1 perform a switching operation in conjunction with a bus select signal sent from the changeover control circuit 9 to switch between the data memory side terminal and the address bus group 10 side terminal, respectively. Then, the path between the data memory side terminal and the data bus group 11 side terminal is switched.

FIG. 3 shows a configuration diagram of the memory block 1-2. Here, an example is shown in which the memory block 1-2 includes four data memories DM5 to DM8. Each of the data memories DM5 to DM8 has a plurality of page pages 5, page 13, page 2 respectively.
1,..., Page 6, page 14, page 22,.
..., page 7, page 15, page 23, ..., page 8, page 16, page 24, ...
Used in this page unit. Data memory DM5-D
The address bus connected to each of M8 is connected to the data memory side terminal of the bus changeover switch 21-2, and the data bus connected to each of the data memories DM5 to DM8 is connected to the data memory side terminal of the bus changeover switch 22-2. It is connected to the. The bus changeover switch 21-2 and the bus changeover switch 22-2 perform switching operation in conjunction with a bus select signal sent from the changeover control circuit 9,
Respectively, between the data memory side terminal and the address bus group 10 terminal and between the data memory side terminal and the data bus group 11
Switch the path to the side terminal.

With the above configuration, the memory blocks 1-1 and 1-2 are transmitted from the page 1 as shown in FIG. 4 from the reception interface 3, the microprocessor 5, the microprocessor 7, and the transmission interface 8. It can be used as one data memory with page n. The capacity of each page is at least LA
N corresponds to the maximum frame length allowed in N.

FIG. 6 shows a more detailed configuration diagram of the switching control circuit 9. The switching control circuit 9 includes bus select signal generators 91 to 94. The bus select signal generators 91 to 94 respectively include the receiving interface 3,
Some of the addresses from the microprocessor 5, the microprocessor 7, and the transmission interface 8 are given. Each of the bus select signal generators 91 to 94 is constituted by, for example, a decode ROM or the like, and outputs a bus select signal corresponding to a part of the address. That is, when the address corresponds to page 1, page 9, page 17,..., Connection to the circuit that outputs the address (any one of the reception interface 3, the microprocessor 5, the microprocessor 7, and the transmission interface 8) Sends a select signal so that the connected bus is connected to the data memory DM1, and the address is set to page 2,
When it corresponds to page 10, page 18, ...
A select signal is sent out so that the bus connected to the circuit that has output the address is connected to the data memory DM2, and the addresses are page 8, page 16, and page 24. ,..., Send a select signal so that the bus connected to the circuit that has output the address is connected to the data memory DM8.

The operation of the above embodiment will be described below.
It is assumed that a frame as shown in FIG. 5 comes from LAN-A. In the frame of FIG. 5, DA indicates a destination address, SA indicates a source address, and T
YPE (LENGH) is the frame type (frame length)
And DATA indicates data (message) related to transmission. The receiving interface 3 outputs addresses corresponding to the pages in a predetermined order in order to secure a page for storing the frame to be received. Here, for simplicity,
It is assumed that an address is output in order from page 1 for designation.

When the system is started, the receiving interface 3 receives a frame as shown in FIG. 5 from the LAN-A. Next, the receiving interface 3 outputs a corresponding address to secure page 1 for storing the received frame. As a result, the switching control circuit 9 obtains a signal provided from a part of the address bus connected to the reception interface 3, and responds to the signal to each of the data memories DM1 to DM1 in the memory blocks 1-1 and 1-2. A bus select signal for switching the connection relationship between the DM 8 and the respective address buses and data buses connected to the reception interface 3 is transmitted to the memory block 1.
-1 and 1-2. That is, the switching control circuit 9 sends the select signal so that the bus connected to the receiving interface 3 is connected to the data memory DM1 because the address corresponds to page 1. As a result, switching occurs in the bus switch 21-1 and the bus switch 22-1 of the memory block 1-1, and the bus connected to the receiving interface 3 and the data memory DM are switched.
1 is connected. Then, the receiving interface 3 writes the above-mentioned received frame into the page 1 of the data memory DM1, and sends out the page information of the page 1 in which the received frame is written to the microprocessor 5 via the line 31. Next, when receiving the next frame, the receiving interface 3 outputs a corresponding address to secure the page 2, and the same operation is continued thereafter (see FIG. 7).

On the other hand, the microprocessor 5 receiving the page information of the page 1 outputs a corresponding address. As a result, the switching control circuit 9 obtains a signal provided from a part of the address bus connected to the microprocessor 5, and responds to the signal to provide each of the data memories DM1 to DM1 in the memory blocks 1-1 and 1-2. A bus select signal for switching the connection relationship between the DM 8 and the respective address buses and data buses connected to the microprocessor 5 is output to the memory blocks 1-1 and 1-2. That is, since the address corresponds to page 1 in the switching control circuit 9, the bus connected to the microprocessor 5 has the data memory D
A select signal is transmitted so that M1 is connected. As a result, the bus changeover switch 21 of the memory block 1-1
1. Switching occurs in the bus switch 22-1, and the bus connected to the microprocessor 5 is connected to the data memory DM1. Then, the microprocessor 5 reads the received frame from the page 1, executes the receiving process such as discriminating the type of the frame, checking the validity of the frame, and stores the received frame in the microprocessor 7 after the process is completed. The page information of the page 1 is transmitted via the line 51. Next, the microprocessor 5 sequentially sends out the corresponding page information every time the receiving interface 3 receives the next frame and stores it in a predetermined page. And outputs the corresponding address to secure the same, and the same operation is continued thereafter (see FIG. 7).

Next, the microprocessor 7 having received the page information of the page 1 outputs a corresponding address. As a result, the switching control circuit 9 obtains a signal provided from a part of the address bus connected to the microprocessor 7, and responds to this signal to each of the memories DM1 to DM8 in the memory blocks 1-1 and 1-2. And a bus select signal for switching the connection relationship between each of the address buses and the data buses connected to the microprocessor 7 to the memory blocks 1-1 and 1-2. That is, the switching control circuit 9
Sends a select signal so that the bus connected to the microprocessor 7 is connected to the data memory DM1 because the address corresponds to page 1. As a result, the bus switch 21- of the memory block 1-1
1. Switching occurs in the bus switch 22-1, and the bus connected to the microprocessor 7 is connected to the data memory DM1. Therefore, the microprocessor 7 reads out the frame from the page 1 and executes transmission processing such as determination of a relay destination from the destination address. After the processing is completed, the microprocessor 7 reads out the page information of the page 1 in which the transmitted frame is stored in the transmission interface 8. Transmitted via line 51. Next, the microprocessor 7 sequentially sends out the corresponding page information every time the microprocessor 5 finishes the reception processing of the frame stored in the next predetermined page. The corresponding address is output to secure the same, and the same operation is continued thereafter (see FIG. 7).

The transmission interface 8 having received the page information of the page 1 outputs a corresponding address. As a result, the switching control circuit 9 obtains a signal provided from a part of the address bus connected to the transmission interface 8, and responds to the signal to each of the data memories DM1 to DM1 in the memory blocks 1-1 and 1-2. A bus select signal for switching the connection relationship between the DM 8 and the respective address buses and data buses connected to the transmission interface 8 is output to the memory blocks 1-1 and 1-2. That is, since the address corresponds to page 1, the switching control circuit 9 sets the bus connected to the transmission interface 8 to the data memory DM1.
Is transmitted so that the connection is made. As a result, the bus switch 21- of the memory block 1-1
1. Switching occurs in the bus switch 22-1, and the bus connected to the transmission interface 8 is connected to the data memory DM1. Then, the transmission interface 8 reads out the frame from the page 1 and executes the LAN-
B, and waits for page information in which the frame to be transmitted next is stored via line 71 to be transmitted. That is, the transmission interface 8 sequentially sends out the corresponding page information every time the microprocessor 7 finishes the transmission processing of the frame stored in the next predetermined page. The corresponding address is output and the frame is taken out as much as possible, and the same frame transmission operation is continued thereafter (see FIG. 7).

Thus, according to the present embodiment, since the page information is sequentially transmitted from the receiving interface 3 to the microprocessor 5, the microprocessor 7, and the transmitting interface 8, the frames are processed in the order of arrival. It is guaranteed to be relayed. Then, the microprocessor 5, the microprocessor 7,
Since the same data memory is connected in the order of the transmission interface 8 and the eight data memories DM1 to DM8 are used sequentially, at a certain point in time, as is apparent from FIG. , The microprocessor 7 and the transmission interface 8 are connected to different data memories, and the processing can be performed simultaneously, thereby improving the throughput. Since the microprocessor 5, the microprocessor 7, and the transmission interface 8 operate upon receiving the transmitted page information, an attempt is made to access a data memory to which another circuit is connected between them (that is, the microprocessor 5, the microprocessor 7, and the transmission interface 8). However, the receiving interface 3 operates to secure a page every time a frame is received. Therefore, when the data memory is small, the data memory connected to the transmission interface 8 is accessed. Have the possibility to try. Therefore, a necessary number of data memories are prepared in consideration of the arrival interval of the received frame and the processing speed of each unit.

In the embodiment, LAN-A to LAN-A
Although the relay to B has been described, another inter-LAN connecting device having the same configuration as that of the embodiment is prepared, the LAN-B is connected to the receiving interface 3, and the transmitting interface 8 is connected.
By connecting the LAN-A to the LAN, relaying in both directions is possible. Further, although not described in the embodiment, when the destination address of the frame indicates the same LAN, the frame is discarded and is not relayed.

In the embodiment, one data memory is divided into a plurality of pages, but in other embodiments, one data memory has one page. In the embodiment,
Although the page information is sequentially passed, in another embodiment, if it is specified that the pages are used in a predetermined order in the receiving interface 3, the information in the predetermined order is transferred to the other than the receiving interface 3. The microprocessor 5, the microprocessor 7, and the transmission interface 8 are provided so as to notify the end of processing one after another. According to this embodiment, effects similar to those of this embodiment can be expected.

[0025]

As described above, according to the first aspect, the reception interface, the reception processing means, the transmission processing means, the transmission interface and the buses respectively connected thereto, and at least as many memories as the number of the buses are provided. The reception interface, the reception processing unit, and the transmission processing unit are provided each time the address of the memory is output from each of the reception interface, the reception processing unit, the transmission processing unit, and the transmission interface. Since the connection relationship between the bus connected to each of the transmission interfaces and the memory is switched, the reception interface, the reception processing means, the transmission processing means, and the transmission interface need only output an address and have a required memory. Are connected one after another, and using this memory, Click receipt of the reception processing of the validation of the data block, transmitting process for transmitting by relaying the data block to the second system, the transmission of data blocks, it becomes possible to perform each time.

According to the second aspect of the present invention, the memory to which the reception interface, the reception processing means, the transmission processing means, and the transmission interface are connected via their respective buses has a page. Since the page information is sequentially sent from the reception interface to the reception processing means, the transmission processing means, and the transmission interface, it is guaranteed that the data blocks are processed and relayed in the order of arrival.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an inter-LAN connection device according to an embodiment of the present invention.

FIG. 2 is a main part configuration diagram of the LAN connection apparatus according to the embodiment of the present invention.

FIG. 3 is a main part configuration diagram of the LAN connection apparatus according to the embodiment of the present invention.

FIG. 4 is a diagram showing a memory space of a data memory provided by the LAN connection apparatus according to the embodiment of the present invention.

FIG. 5 is a diagram showing a format of a frame received by the LAN connection apparatus according to the embodiment of the present invention.

FIG. 6 is a configuration diagram of a switching control circuit according to a main part of the LAN connection apparatus according to the embodiment of the present invention.

FIG. 7 is a state transition diagram for explaining the operation of the LAN connection apparatus according to the embodiment of the present invention.

FIG. 8 is a configuration diagram of a conventional LAN connection device.

FIG. 9 is a configuration diagram of a conventional LAN connection device.

[Explanation of symbols]

1-1, 1-2 Memory block 3 Reception interface 4, 6 Main memory 5, 7 Microprocessor 8 Transmission interface 9 Switching control circuit 10 Address bus 11 Data bus 21-1, 21-2, 22-1, 22-2 Bus switch 91-94 Bus select signal generator DM1-DM8 Data memory

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 12/46

Claims (2)

(57) [Claims] 1. A receiving interface for receiving a data block arriving from a first system, receiving processing means for performing a receiving process on a data block received by the receiving interface, and receiving the data block processed by the receiving processing means. Transmission processing means for performing transmission processing on the data block for relaying and transmitting the data block to the second system; transmission interface for transmitting the data block processed by the transmission processing means to the second system; An interface, the reception processing means, the transmission processing means, buses connected to the transmission interfaces, at least as many memories as the number of the buses, and the reception interface, the reception processing means, the transmission processing means, The address of the memory from each of the transmission interfaces Every time is output, the reception interface, the reception processing means, the transmission processing means, and a bus switching means for switching a connection relationship between a bus connected to each of the transmission interfaces and the memory. Data relay device. 2. A memory group comprising four or more memories having pages for storing data blocks related to processing, and a page for receiving data blocks coming from a first system and storing them in a predetermined order. A receiving interface for outputting an address to be specified, and a page information of a storage destination of the received data block is given by the receiving interface, and an address for specifying this page is output to output the data block stored in the corresponding page. Receiving processing information for receiving the data block processed by the receiving processing means, receiving the page information of the storage destination, outputting an address designating the page, and retrieving the data block stored in the corresponding page. A transmission process for relaying and transmitting to the second system is performed for the data block. Data processing means, provided with page information of a storage destination for the data block processed by the transmission processing means, outputting an address designating the page, and outputting the data block stored in the page to the second data block. A transmission interface for transmitting data to a system, a bus connected to each of the reception interface, the reception processing unit, the transmission processing unit, and the transmission interface; a reception interface, the reception processing unit, the transmission processing unit, and the transmission Each time an address of the memory is output from each of the interfaces, the connection relationship between the reception interface, the reception processing means, the transmission processing means, the bus connected to each of the transmission interfaces, and the memories of the memory group Bus switching means for switching between Data relay apparatus.