JPH02110783A - Lsi circuit for graphic processing - Google Patents

Abstract

PURPOSE:To improve the processing performance of the whole of a pipeline by sending up an interruption to an MPU when a memory for input becomes full, continuously reading out all the data in the memory for input and saving the data in a built-in RAM by the MPU, and preventing the occurrence of clogging in the preceding step. CONSTITUTION:An interruption control part 16 detects that a full state signal FF is outputted from a memory 12 for input and generates an interruption signal INT. An MPU 11 responds to the interruption signal INT generated by the interruption control pat 16, continuously reads out all the data stored in the memory 12 for input, and executes transfer control for a RAM 14. Consequently, even when surface painting processing is delayed, the delay never gives influence on the processing in the preceding step, and a processing neck in the pipeline can be lightened. Thus, the processing performance of the whole of the pipeline can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a graphic processing LSI circuit that performs graphic processing such as surface painting and clipping in a processing device such as a workstation.

The purpose of this invention is to make it possible to eliminate processing bottlenecks in the one-sided coating processing stage in a pipeline mechanism configured by connecting LSI circuits for graphic processing in multiple stages.

In an LS1 circuit for graphic processing, which includes at least an MPU, a RAM, and an input memory having a plurality of storage stages and having a function of outputting a full status signal when all the storage stages are filled with data. .

An interrupt control section is provided that detects that a full state signal is output from the input memory and generates an interrupt signal.

The MPU was configured to continuously read out all data stored in the input memory and control transfer to the RAM in response to an interrupt signal generated by the 2-interrupt control section.

[Industrial application field]

The present invention relates to a graphic processing LSI circuit that performs graphic processing such as surface painting and clipping in a processing device such as a workstation, and particularly to a graphic processing LSI circuit used in each processing stage in a pipeline configuration graphic processing device.

[Conventional technology]

Generally, figure processing involves fetching drawing orders, coordinate transformation,
Brightness calculation, viewing conversion, clipping, area painting,
It consists of each step of writing drawing data to the frame memory.

Conventionally, in order to execute such graphic processing at high speed, a pipeline mechanism has been developed in which LSI circuits each processing each step are connected in series.

Figure 4 shows an example of a pipeline using such a graphic processing LSI circuit.
are coordinate transformation and brightness calculation, respectively.

This is a processing stage for each step of viewing conversion, clipping, and surface painting, and is connected in series. The drawing order and processing data are sequentially processed through each of these processing stages (.

FIG. 5 shows the graphic processing LS that constitutes each processing stage in FIG.
This figure shows the configuration of the I circuit.

In FIG. 5, 6 is an MPU, 7 is an input memory, 8 is a ROM, 9 is a RAM, and 10 is a bus output section. The input memory 7 is connected to the input bus from the previous stage, and the bus output section 10 is connected to the output bus from the next stage.

The input memory 7 is composed of FIFO and has a plurality of storage stages. Data writing to the input memory 7 is performed by a write control signal W from the previous stage, and data reading is performed by a read control signal R from the MPU 6.

The usage status of each storage stage of the input memory 7 is managed by a flag, and when all the storage stages are filled with data, a full flag signal F F (Pull
Flag) is output to the previous stage, and when there is no data in all storage stages, an empty flag signal E F (Em
pty Flag) to the MPU6.

Problems arose in the processing performance of the pipeline.

It is an object of the present invention to improve the processing performance of the entire pipeline by making it possible to solve the processing bottleneck in the surface painting processing stage in a pipeline mechanism constructed by connecting nine graphic processing LSI circuits in multiple stages.

[Problem to be solved by the invention]

In a conventional pipeline configured by connecting multiple LSI circuits for graphic processing, one built-in R of each LSI circuit for graphic processing is used.
Since there is a limit to the storage capacity of AM, if you try to use a pipeline to perform polygon fill processing.

■ The number of vertices of one polygon is limited.

■ The surface coating process may take a long time, causing the front stage of the pipeline to become clogged.

■ Before reading the information in the input memory, it is necessary to take a step to confirm whether the information in the input memory can be read, which increases processing time.

[Means to solve the problem]

The present invention solves the limitation due to the capacity of the built-in RAM of the LSI circuit for graphic processing, so it is possible to attach an expansion RAM externally, and it also reduces the processing burden of checking the status of the input memory when the MPU reads the input memory. In order to increase the processing efficiency of the MPU, an interrupt is sent to the MPU when the input memory is full.

The MPU continuously reads all data from the input memory and saves it to the built-in RAM or expanded RAM to prevent clogging in the previous stage.

FIG. 1 is a principle diagram of the present invention, showing the block configuration of an improved graphic processing LSI circuit.

In FIG. 1, 11 is an MPU, 12 is an input memory using FIFO, for example, which can sequentially store a plurality of data, 13 is a ROM, and 14 is a RAM.

15 is a bus output section, 16 is an interrupt control section, 17 is an expansion RAM input/output section, 18 is an expansion RAM, and 19 is a bus.

In FIG. 1, elements indicated by 11 to 15 are basic components common to the conventional graphic processing LS1 circuit.

The interrupt control unit 16 turns on the interrupt signal INT when the input memory 12 becomes full and the full flag signal FF turns on, and issues an interrupt request to the MPU II.

The MPU II can be masked against its interrupt requests, and the read control signal R
is turned on, the reading of the input memory 12 is controlled, and
Transfer all data in input memory to RAM14 or expansion R
Continuously read out to AM18. At this time, the 2-interrupt control unit 16 counts the number of times the read control signal R is turned on, and when the number of times the read control signal R is turned on reaches the number of times the entire data is read, the interrupt signal IN
Clear T.

The expansion RAM input/output section 17 has an expansion RAM 18 and a bus 19.
This is an interface that connects the devices, and through which addresses, data, and timing signals are transferred.

[Effect]

In FIG. 1, the MPU II controls the readout of the input memory 12 because the input memory 12 is full of data and the FF is turned on, and the 1 interrupt control unit 16 controls the INT.
This is when you turn it on.

On the other hand, in the conventional case, when the MPU II checks the state of the human memory 12 and confirms that the input memory 12 is ready for reading, that is, there is data waiting to be read in the input memory 12, it turns on R and reads the input memory. It controlled reading. Since this control is performed frequently, the processing load placed on the MPU is quite large.

In contrast, in the case of the present invention, the MPU II can perform other processing until the input memory becomes full and an interrupt request is received, and this interrupt occurs only when the input memory 12 becomes full. Therefore, the frequency of this decreases as the capacity of the input memory 12 increases.Reading is performed continuously on all data in the input memory 12 at once, and the read data is temporarily RAM1
4 or stored in the expansion RAM 18.

As a result of the above, the processing efficiency of MPU II has been improved, the processing time for surface painting processing, which requires a large amount of calculation, has been shortened, and even if surface painting processing takes a long time, it does not affect the previous processing, and processing in the pipeline This reduces bottlenecks and improves the processing performance of the entire pipeline.

Furthermore, by using the expanded RAM, a large work area can be secured, so that it is possible to fill the entire surface of a polygon with a large number of vertices.

〔Example〕

The present invention will be explained in detail with reference to FIGS. 2 and 3.

FIG. 2 shows one of the interrupt control units 16 shown in FIG.
This is a circuit diagram of the embodiment, and FIG. 3 is a signal timing diagram thereof.

In FIG. 2, 20 and 21 are AND circuits.

22 is a flip-flop on J-, and 23 is a counter.

24 is a NANDAND circuit.

When the clock and full flag signal FF both become a1'', the AND circuit 20 sets the CLK terminal of the flip-flop 22 to "1" at J-.

The J- terminal of the flip-flop 22 is connected to the ζ terminal, and "0" is applied to the J- terminal. For this reason, Q
-When the CLK terminal becomes 1 in the reset state of “1”,
The flip-flop 22 is turned on at J-, and the Q terminal is “
1”.The “1” of this Q terminal is the 2nd interrupt signal IN.
T is turned on and added to MPU II (FIG. 1).

AND circuit 21 is an arrow reset signal or NAND circuit 2
When either or both of the output signals of 4 are “θ”, “
0'' to reset the flip-flop 22 to J-.

The counter 23 is reset by the X reset signal, inputs the read control signal R to the CLK terminal, and receives the R-"1
When the counter 23 counts up to the number of storage stages of the input memory 12 (FIG. 1), that is, the maximum number of writable data, the counter 23 sets the carry terminal to "1".
”

The NAND circuit 24 outputs "0" when both the read control signal R and the carry become 1".

The output of the AND circuit 21 is set to "0" and the flip-flop 22 is reset to J-. In other words, input memory 1
When all the data are read out from 2 (FIG. 1), the carry of the counter 23 becomes "1", and the flip-flop 22 is turned off at J- to clear the interrupt signal INT.

Note that when the J terminal and the terminal of the flip-flop 22 at J- are both "0", the previous state is maintained as is even if the CLK terminal becomes "1" (meaning that a clock is input).

Next, the overall flow of operation of the circuits shown in FIGS. 1 and 2 will be explained with reference to the signal timing diagram shown in FIG. For convenience, it is assumed that the input memory 12 is composed of 16 stages of FiFO. Therefore, the counter 23 outputs a carry "1" when the count value reaches "16".

In Figure 3, the clock in (a) is continuously supplied, and the ≠ reset signal in Figure 3 (b) is initially "0".
It's on the level. The reset signal is t. Then, the write control signal W in FIG.
16 pieces are given from to t2.

At t2, the full signal output from the input memory 12
The flag signal FF becomes "1" as shown in FIG. 3 (d+). As a result, the output (FF/clock) of the AND circuit 20 of the interrupt control section 16 becomes "1" as shown in FIG. 3 (e). 1", thereby turning on the JK flip-flop 22 and setting the interrupt signal INT to "1" as shown in FIG. 3 (fl).

In response to this interrupt signal, the MPU II outputs 16 read control signals R between t3 and t4, as shown in FIG.

The input memory 12 resets the full flag signal FF shown in FIG. 3(d) to "0" by reading the first data at +j3.

When the counter 23 counts 16 read control signals R, the counter 23 outputs a carry “1” as shown in FIG. 3 (hl).
, and outputs the NAND circuit 24 as shown in FIG.
The output (carry R) changes from 1'' to 0''.

As a result, the flip-flop 22 is reset to J-, and the interrupt signal INT shown in FIG. 3(f) is reset to "0".

〔Effect of the invention〕

According to the present invention, the burden of controlling the readout of the input memory on the MPU is reduced, and even if the input memory becomes full, it is immediately saved to the RAM, so data can be smoothly transferred from the previous stage. Furthermore, since the RAM can be expanded, the ability to process polygons with a large number of vertices is improved, and the performance of the entire pipeline is significantly improved.

[Brief explanation of the drawing]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a circuit diagram of an interrupt control section according to an embodiment of the invention, Fig. 3 is a signal timing diagram of the embodiment circuit of Fig. 2, and Fig. 4 is a diagram of the conventional circuit. L for graphic processing
A block diagram of a pipeline mechanism using an S1 circuit, and FIG. 5 is a block diagram of a conventional graphic processing LSI circuit. In Figure 1. 11: MPU 12: Input memory 13: ROM 14: RAM 15: Bus output section 16: Interrupt control section 17: Expansion RAM input/output section 18: Expansion RAM 19: Bus

Claims (1)

[Claims] (1) It has an MPU (11), a RAM (14), and a plurality of storage stages, and outputs a full status signal (FF) when all the storage stages are filled with data. In a graphic processing LSI circuit that is equipped with at least a functional input memory (12), an interrupt signal (INT) is generated upon detecting that a full state signal (FF) is output from the input memory (12). An interrupt control unit (16) that generates an interrupt signal (INT) is provided, and the MPU (11) responds to an interrupt signal (INT) generated by the interrupt control unit (16) to generate an input memory (16).
2) Continuously read all data stored in R
A graphic processing LSI circuit characterized by controlling transfer to an AM (14).