JPS60246464A - Data transferring system of buffer memory - Google Patents

Abstract

PURPOSE:To execute directly a transfer of data between an input/output port and a buffer memory without being inputted to a register of an MPU by outputting automatically a mode switching signal by using an address space of the buffer memory. CONSTITUTION:When it is supposed that an MPU2 has outputted a write instruction by designating an address having a data storing area 22, a buffer memory 3 which has received it knows that this address is a virtual address, namely, an extended mode, by its built-in decoder, and converts this logical address to a real address. Subsequently, an extended signal EXA1 is outputted, and a tri-state bus driver 6 is inhibited through an NOR circuit 9 and an NAND circuit 10. The MPU2 executes the write instruction, and stores directly data of an input port 1 onto the address of the buffer memory 3 without transferring it to a register.

Description

[Detailed description of the invention] [Technical field of invention] The present invention is a one-buffer memory data transfer method.

In particular, data transfer between the input/output board and the buffer memory is performed directly without going through the registers in the MPU.
The present invention relates to a buffer memory data transfer method that reduces data transfer processing time.

[Background of the invention and problems]

Conventionally, when an MPU transfers data between an input/output board and a buffer memory, data is transferred to the MPU via a data bus by a read command issued by the MPU, and then transferred to the MPU by a write command issued by the MPU. The data transferred to the bus had to be written to the printer memory or output port, which required two bus cycles.

FIG. 3 shows a circuit configuration according to a conventional system. The data transfer according to this conventional method is as follows (that is, data is transferred from the main body 9 to the input port 1, the MPU reads the data, and once loads it into the register of the MPtJ2).

The data stored in the register of this MPL 12 is stored on the designated address of the buffer memory 3. Data from the human-powered boat 1 was sequentially transferred to the buffer memory 3 by repeating such a cycle. For example, when printing.

The data stored in the buffer memory 3 is temporarily transferred to the MPU 2.
The data loaded into the register of the MPU 2 is then transferred to the output port 4 connected to the print driver, repeating the cycle to transfer 5 data.

Therefore, as explained above, two bus cycles are used for data transfer in the buffer memory 3.

There was a drawback that data transfer could not be made faster.

In FIG. 3, reference numeral 5 is a ROM, 6 is a tri-state bus driver, and 7 is a data bus.

8 represents an address bus.

Further, FIG. 4 shows an example of the address map of a conventional buffer memory, and reference numeral 24 indicates the address map of a conventional buffer memory.
Area 25 represents a program area, and 26 represents an unused area.

[Object and structure of the invention]

The present invention aims to solve the above-mentioned drawbacks,
By adding simple hardware to the conventional circuit configuration,
The purpose is to provide a buffer memory data transfer method that allows data transfer to be performed more efficiently. Therefore, the data transfer method of the buffer memory of the present invention has one input port that receives data sent from the main device.

Equipped with a buffer memory that temporarily stores the data, an output port that sequentially sets the data stored in the buffer memory, and an MPU that controls data transfer, and outputs the data of the input port via the buffer memory. In the buffer memory data transfer method for transferring data to a port, when the MPU accesses the buffer memory using a virtual address, it outputs an extended mode signal and directly executes data transfer between the input/output port and the buffer memory. The present invention is characterized in that a mode switching circuit is provided to switch the mode in response to the appearance of the extended mode signal, thereby making it possible to directly transfer data between the input/output board and the buffer memory. This will be explained below with reference to the drawings.

[Embodiments of the invention]

FIG. 1 shows a circuit configuration of an embodiment of the buffer memory data transfer method according to the present invention, and FIG. 2 shows an example of an address map of the buffer memory in the buffer memory data transfer method according to the present invention. There is.

In FIG. 1, numerals 1 to 8 correspond to those in FIG. 3 described above. Reference numeral 9 represents a negative logic NAND circuit, 10 represents a negative logic NAND circuit, 11 represents a negative logic NOR circuit, 12 represents an inverter circuit, and 13 represents a negative logic NAND circuit. These gate circuits allow high-speed data transfer. The mode switching circuit is configured to enable high-speed data transfer processing using the extended mode signal described below.

Next, the address map shown in FIG. 2 will be explained.

The buffer memory shown with respect to buffer memory 3
The physical address space of the area 21 is set to hide 8, and the address space is further expanded to allocate the primary 8 bytes to the data storage area 22, and the next 8 bytes to the data transfer area 23. The data storage area 22 of these expanded logical address spaces is called a first extended area (EXAl), and the data transfer area 23 is called a second extended area (EXA2). These expanded logical address spaces become the virtual address spaces of the buffer memory 3.

Note that 26 is an unused area, and 25 is a program area.

For example, if the MPU 2 issues a write command by specifying the address (2000+α) of the second data storage area 22, the buffer memory η3 that received the address <2000+α) will be processed by the built-in decoder. Knowing that this address (2000+α) is a virtual address, that is, in extension mode, it converts this logical address into a real address α and outputs an extension signal EXA1. This EXA 1 is input to a negative logic NOR circuit 9 and a negative logic NAND circuit 10.

Set the tri-state path driver 6 to inhibit mode.

The MPU 2 executes the write command and writes the data directly onto the address α of the buffer memory 3 (address α on the buffer memory area 21 shown in FIG. 2) without transferring the data of the input port 1 to the register of the MPU 2. Store. In this way, when the MPU 2 executes a write instruction at an address in the data storage area 22, the expansion mode (data storage in this case) is determined based on the address different from the address in the buffer memory area 21, that is, the virtual address. , EXAI signals are output, and data at input port 1 is directly transferred to buffer memory 3.

On the other hand, if the MPU 2 specifies a certain address (4000+α) in the third data transfer area 23 and issues a read command, the buffer memory 3 that received the address (4000+α) As a result, it knows that this address (4000+α) is also a virtual address, that is, it is in extended mode, and converts this logical address into a real address α.

Outputs an extended signal EXA2. This EXA2 is input to a negative logic NOR circuit 9 and a negative logic NAND circuit 10. M
The PU2 executes the read command and reads the address α of the buffer memory 3 (buffer memory area 21 shown in FIG.
Read the data at address α) above. This read data is directly transferred by the EXA 2 to the output port 4 which has become ready to accept. At this time, since the tristate bus driver 6 is not in the inhibited state, the information is also stored in the register of the MPU 2 as required.

In this way, when the MPU 2 executes a read command at an address in the data transfer area 23, the extended mode (data transfer in this case) is determined based on an address different from the address in the buffer memory area 21, that is, a virtual address. The EXA2 signal will be output.

Data read from buffer memory 3 is transferred directly to output port 4.

Note that when the MPU 2 specifies a real address in the buffer memory area 21 and executes a read or write command, the data storage area 22 and the data transfer area 2
Since EXAI does not encode the virtual address of 3, it is set to the extended mode described above.

EXA2 signal is not generated. So in this case.

A normal mode is entered in which data is temporarily stored in the register of the MPU 2, which is exactly the same as the conventional one shown in FIG. 3, and then transferred.

In the above explanation, all of the EXAI and EXA2 signals for switching to the extended mode are output from the decoder of the buffer memory 3, but they may be generated from other circuits to effect mode switching.

〔Effect of the invention〕

As explained above, according to the third invention, a simple circuit is added and a mode switching signal is automatically issued using the address space of the buffer memory.

Transfer of data between input/output board and buffer memory is M
Data transfer efficiency has improved because it can now be performed directly without importing it to the PU register.

Data transfer processing time is reduced.

[Brief explanation of drawings]

FIG. 1 shows a circuit configuration of an embodiment of the buffer memory data transfer method according to the present invention, and FIG. 2 shows an example address map of the buffer memory in which the buffer memory data transfer method according to the present invention is applied. Figure 3 shows the conventional buffer
An example of a configuration of a memory data transfer method, FIG. 4 shows a buffer memory in a conventional buffer memory data transfer method.
An example of a memory address map is shown. In the figure, 1 is an input port, 2 is an MPo, 3 is a buffer memory, 4 is an output port, 5 is a ROM, 6 is a tri-state bus driver, 7 is a data buzz, 8 is an address bus, and 9 is a negative logic Noah circuit. 10 is a negative logic NAND circuit, 11 is a negative logic NOR circuit,
12 is an inverter circuit, 13 is a negative logic NAND circuit, 2
1 is a buffer memory area, 22 is a data storage area, 23 is a data transfer area, 24 is a buffer memory area, 25 is a program area, and 26 is an unused area.

Claims (1)

[Claims] An input port that receives data sent from the main unit, a buffer memory that temporarily stores the data, an output port that sequentially sends the data stored in the buffer memory, and In a buffer memory data transfer method that includes an MPU that controls data transfer and transfers data from an input port to an output port via a buffer memory. When the MPU accesses the buffer memory using a virtual address, a mode switching circuit is provided that outputs an expansion mode signal and directly executes data transfer between the input/output board and the buffer memory.9 The appearance of the expansion mode signal described above. The mode is switched by . A data transfer method for a buffer memory, characterized in that data can be transferred directly between a human output boat and the buffer memory.