JPH01126744A - Data processor - Google Patents

Abstract

PURPOSE:To eliminate a try-state-buffer by executing the writing of data from a data bus to a RAM circuit through a logical LSI provided with a register which selects the data and temporarily stores them. CONSTITUTION:When the data are written to a RAM circuit 2, at first, the writing data are fetched through a bidirectional buffer 11 into a selecting circuit 12 and a logic circuit 15. At such a time, '1' is inputted from the logic circuit 15 to the selecting circuit 12 and the writing data are stored to a register 13 and after that, sent through a bidirectional buffer 14 to a RAM circuit 12. On the other hand, when the data are read from the RAM circuit 2, the reading data are sent through the bidirectional buffer 14 to the selecting circuit 12. At such a time, '0' is outputted for a selecting signal from the logic circuit 15 and the reading data are fetched through a signal line 131 into the logic circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a data processing device, and in particular to a logic [Sl (l
large-scale integration) and RAM (randone-access memory
) circuit.

BACKGROUND TECHNOLOGY Conventionally, as shown in FIG. 2, in this type of data processing device, a RAM circuit 2 that can be written and read freely is connected to a data bus 101 and is connected to the RAM circuit 2 via a bidirectional data line 102. It is composed of a logic LSI 3 that is connected to control the RAM circuit 2, and a tristate buffer 4 that inputs data from a data bus 101 and outputs data to the RAM circuit 2 via a data line 102. 2 is connected to the data bus 1 via this buffer 4.
It was configured to be directly connected to 01.

When writing data to RAM circuit 2, data bus 1
The data from 01 is input to the tristate buffer 4, and the data is written from the tristate buffer 4 to the RAM circuit 2 via the data line 102. Also, RAM
When reading data from the circuit 2, the data read from the RAM circuit 2 is transferred to the logic LSI via the data line 102.
3 is input.

In such a conventional data processing device, the data bus 10
Data bus 1 is used to write data 1 to RAM circuit 2.
A tri-state buffer 4 is provided between 01 and the RAM circuit 2.
The disadvantage is that there are many hardware parts because it is necessary to connect the

However, in order to do this, it is necessary to increase the number of input/output terminals of the logic LSI 3, and the purpose of the invention is to increase the number of input/output terminals of the logic LSI 3. To provide a data processing device that can reduce the number of hardware parts by writing data from a data bus to a RAM circuit via a logic LSI without increasing the number of input/output terminals. With the goal.

Structure of the Invention A data processing device according to the present invention is a logic circuit device having a storage means that can be written and read freely, a data bus for transferring data written to the storage means, and a register for temporarily storing data read from the storage means. a data processing device comprising: a selection means for selecting one of the write data and the read data and storing the selected data in the register; The write data is selected by the selection means at the time of writing, temporarily stored in the register, and written from the register to the storage means.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a data processing device according to an embodiment of the present invention includes a logic LS 11, a RAM circuit 2, and a data bus 1.
01.

The logic LSII includes bidirectional buffers 11.14, a selection circuit 12 that selects one of the data from each of the bidirectional buffers 11.14, and a register 13 that stores the data selected by the selection circuit 12, and the overall operation. a logic circuit 15 that controls the , a bidirectional terminal 16.17, and an output terminal 18.1
9.

When the output control signal from the logic circuit 15 sent via the signal line 151 is "1", the bidirectional buffer 11
Data sent from the logic circuit 15 via the signal line 152 is output to the signal line 112, and this output control signal is 0''.
At this time, data sent via the signal line 152 is not output to the signal line 112.

The selection circuit 12 selects the signal line 141 when the selection signal from the logic circuit 15 sent via the signal line 153 is 0''.
The selected read data sent from the bidirectional buffer 14 via the signal line 121 is sent to the register 13 via the signal line 121. When this selection signal is "1", the signal line 111
The selected data sent from the bidirectional buffer 11 via the signal line 121 is sent to the register 13 via the signal line 121.

When the output control signal from the logic circuit 15 sent via the signal line 155 is "1", the bidirectional buffer 14
The data sent from the register 13 via the signal line 131 is output to the signal line 142, and this output control signal is set to “0”.
'', the data sent from the register 13 via the signal line 131 is not output to the signal line 142.

When writing data to the RAM circuit 2, first, write data to be written to the RAM circuit 2 from the data bus 101 is taken into the logic LS 11 via the bidirectional terminal 16.

The write data input from the bidirectional terminal 16 is sent to the signal line 1.
The data input to the bidirectional buffer 11 is sent to the selection circuit 12 and the logic circuit 15 via the signal line 111.

At this time, since data is written to the RAM circuit 2, 1'' is input to the selection circuit 12 as a selection signal from the logic circuit 15, and the write data input via the signal line 111 is selected and the signal It is sent to the register 13 via the line 121. The write data selected by the selection circuit 12 is stored in the register 13 in accordance with the register storage control signal sent from the logic circuit 15 via the signal line 154. The write data stored in register 13 is sent to bidirectional buffer 14 and logic circuit 15 via signal line 131.

Since "1" is input as the output control signal from the logic circuit 15 to the bidirectional buffer 14, the write data sent from the register 13 is output to the signal line 142. The write data output to the signal line 142 is transferred to the bidirectional terminal 17.
and is sent to the RAM circuit 2 via the data line 102.

In the RAM circuit 2, when the write control signal sent from the logic circuit 15 via the signal line 156, the output terminal 18, and the signal line 103 is 1'', the signal from the logic circuit 15 to the signal line 15 is
The write data sent via the data line 102 is written to the address of the RAM circuit 2 corresponding to the address data sent via the output terminal 7, the output terminal 19, and the signal line 104.

When reading data from the RAM circuit 2, the signal line 10
The write control signal from the logic circuit 15 sent via the signal line 104 becomes "0", and the RAM corresponding to the address data from the logic circuit 15 sent via the signal line 104 becomes "0".
Read data is read from the address of circuit 2 and sent to data line 102.

The read data sent to the data line 102 is input to the bidirectional buffer 14 via the bidirectional terminal 17 and the signal line 142, and the read data input to the bidirectional buffer 14 is input to the selection circuit 12 via the signal line 141. Sent out.

At this time, since data is being read from the RAM circuit 2, O'' is input to the selection circuit 12 as a selection signal from the logic circuit 15, and the read data input via the signal line 141 is selected. It is sent to the register 13 via the signal line 121.

In the register 13, the read data selected by the selection circuit 12 is stored in accordance with the register storage control signal from the logic circuit 15 sent via the signal line 154, and the read data is stored in the register 13.
31 to the logic circuit 15.

In this way, one of the write data to the RAM circuit 2 and the read data from the RAM circuit 2 is transferred to the logic LSII.
The selected data is selected by a selection circuit 12 provided in the internal memory, and the selected data is transferred to a register 13 which is used to temporarily store read data from the RAM circuit 2 in conventional logic LSIs.
When the write data is written to the RAM circuit 2, the selection circuit 12 selects the write data and writes it to the RAM circuit 2 via the register 13. The write data from the data bus 101 to the RAM circuit 2 can be sent to the RAM circuit 2 via the logic LS11 without increasing the amount of data. Therefore, the tristate buffer that is required when connecting the RAM circuit 2 and the data bus 101 can be eliminated, and the number of hardware components can be reduced.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described in detail, one of the data written to the RAM circuit and the data read from the RAM circuit is selected to temporarily store the data read from the RAM circuit. The selection means stored in the register is set to logic L.
The input/output of the logic LSI is provided in the SI, and when the write data is written to the RAM circuit, the write data is selected by the selection means and stored in the register, and the write data is written from this register to the RAM circuit. The tri-state buffer that was conventionally required can be omitted without increasing the number of terminals, and the number of hardware components can therefore be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a block diagram showing the configuration of a conventional example. Explanation of symbols of main parts 1...Logic LSI 2...RAM circuit 11.14...Bidirectional buffer 12...
・Selection circuit 13...Register

Claims (1)

[Claims] A data processing device including a storage means that can be written and read freely, a data bus for transferring write data to the storage means, and a logic circuit device having a register for temporarily storing data read from the storage means, the data processing device comprising: Provided in the logic circuit device is selection means for selecting one of the write data and the read data and storing it in the register,
A data processing device characterized in that, when writing the write data to the storage means, the selection means selects the write data and temporarily stores it in the register, and writes the write data from the register to the storage means.