JPH0561809A - Memory control circuit for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To separate the internal data bus of LSI incorporating a memory for an external part and an internal processing function at the time of external access and to execute a parallel processing so as to realize a high speed processing. CONSTITUTION:The data bus 3 and the data bus 3a are separated by a separation circuit 7 at the time of external data bus access. Data access between the memory 1 and the external part is executed by using the data bus 3a. At that time, the separated data bus 3 is used at the internal part of LSI irrespective of an external access operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit memory control circuit, and more particularly to a memory control circuit requiring an interface with the outside.

[0002]

2. Description of the Related Art Advances in integrated circuits have complicated the amount of data to be handled and the method of accessing the data. Conventionally, such an integrated circuit has a data bus structure as shown in FIG. Inside the integrated circuit, the data to be handled is transferred to each processing unit via the internal data bus 53. Therefore, the internal data bus 53 is connected to the memory 51 as shown in FIG. 5 and also connected to the external terminal 54.

Next, the data flow will be described with reference to FIG.

A series of data to be processed is fetched from the external terminal 54 into the integrated circuit and stored in the memory 51 via the internal data bus 53. At this time, the address of the memory 51 is designated by the address register 52. When the data stored in the memory 51 is used for calculation or the like, necessary data is transferred to the calculation unit or registers via the internal data bus 53. The processed data is again stored in the memory 51 via the internal data bus 53. Further, the processed series of data is output from the memory 51 via the internal data bus 53 to the outside of the integrated circuit from the external terminal 54.

As described above, inside the integrated circuit, input of data from the outside, storage of data in the memory 51, transfer of data to the arithmetic unit, etc. are all performed via the internal data bus 53. Become. In addition, transfer of data such as input and output to registers other than the memory and each processing unit also uses the internal data bus.

[0006]

However, in the above-described conventional example, since data transfer is performed via the internal data bus 53 at the interface with the inside and outside of the integrated circuit, the processing using the internal data bus 53 is performed. Cannot be processed in parallel. For example, while the data stored in the memory is being output to the outside, the data cannot be transferred between other processing units such as the arithmetic unit and the register.

This is a serious drawback because the high speed is hindered in an integrated circuit having an arithmetic circuit or the like which requires high speed processing.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a memory control circuit of a semiconductor integrated circuit capable of high-speed processing.

[0009]

According to another aspect of the present invention, there is provided a memory control circuit for a semiconductor integrated circuit, comprising: an address register for storing an address of the memory; An address input terminal for inputting address data, a multiplexer for selecting any one of the address input from the address input terminal and the address of the address register and outputting it as the address of the memory, and data input from outside the integrated circuit. A data input terminal, a first data bus connected to the data input terminal and the memory, a second data bus for handling internal data inside the integrated circuit, the first data bus and the second data And a separation circuit for connecting to or disconnecting from the bus.

[0010]

According to the present invention, when the external data bus is accessed through the address input terminal, the separation circuit separates the first data bus and the second data bus. The first data bus is used for data access between the memory and the outside, and the second data bus is used inside the integrated circuit regardless of the external access operation. Therefore, parallel operation is possible and high-speed processing can be performed.

[0011]

Embodiments of the present invention will now be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a memory control circuit according to an embodiment of the present invention. The present invention relates to any one of a memory 1 for storing data, an address register 2 for storing an internal address of the memory 1, an address terminal 4 for inputting an address from outside the integrated circuit, and data of the address register 2 and the address terminal 4. A multiplexer 6 that selects one of them and outputs it to the memory 1 as its address, a data terminal 5 that takes a data interface with the outside, an internal data bus 3 that handles the data of each processing unit, a memory 1 and a data terminal 5. Internal data bus 3a connected
And a gate circuit 7 for separating the internal data bus 3. The gate circuit 7 is composed of a transfer gate as shown in FIG.

Next, the operation of this embodiment will be described.

In the data transfer between the memory 1 and each processing unit inside the integrated circuit, first, the necessary address data is input from the address register 2 to the multiplexer 6, and in the multiplexer 6, the address data of the address register 2 is input. Is output as the address of the memory 1. Data access to the memory cell of this address is performed with the internal data bus 3. At this time, the separation circuit 7
Connects the data bus for the memory 1 and the data bus of each processing unit.

Next, the operation of the gate circuit 7 will be described.

As an example, consider an internal data bus with a data bus width of 8 bits. When the data bus 3a of the memory 1 and the data bus 3 of each processing unit are connected,
The separation signal a becomes active (= 1), the transfer gates 21, 22 and 23 are turned on, and the internal data bus 3 and the internal data bus 3a are connected.

When data is transferred between the memory 1 and the outside of the integrated circuit, the address data input from the address bus terminal 4 is input to the multiplexer 6.
It indicates the address of the memory 1. The data of the memory cell indicated by this address is interfaced with the outside through the internal data bus 3a and the data bus terminal 5. At this time, in the gate circuit 7, the separation signal a becomes inactive (= 0), the transfer gates 21, 22 and 23 are turned off, and the internal data bus 3 and the internal data bus 3a are separated. As a result, in this embodiment, during the period in which the data stored in the memory 1 is being output to the outside, data transfer and the like can be performed in parallel via the data bus 3 in the arithmetic unit and other processing units. Therefore, high speed processing is achieved.

Next, referring to FIG. 3 which is similar to another embodiment of the present invention.
And shown in FIG.

In this embodiment, a memory 1 for storing data
An address register 2 for storing an internal address of the memory 1, an address terminal 4 for inputting an address outside the integrated circuit, a multiplexer 6 for selecting one of the data in the address register 2 and the address terminal 4, and an external device. A data terminal 5 for data interface with
An internal data bus 3 that handles data of each processing unit, and an internal data bus 3a connected to the memory 1 and the data terminal 5
And a buffer circuit 8 for separating the internal data buses 3 and 3a. The buffer circuit 8 is configured by a tri-state buffer as shown in FIG.

Next, the operation of this embodiment will be described.

In the data transfer between the memory 1 and each processing unit inside the integrated circuit, first, necessary address data is input from the address register 2 to the multiplexer 6,
The multiplexer 6 outputs the address data of the address register 2 as the address of the memory 1. Data access to the memory cell of this address is performed with the internal data bus 3. At this time, the buffer circuit 8 connects the data bus 3a for the memory 1 and the data bus 3 of each processing unit.

Next, the operation of the buffer circuit 8 will be described with reference to FIG.

Similar to the first embodiment, an internal data bus having a data bus width of 8 bits will be taken as an example. The data bus 3a of the memory 1 and the data bus 3 of each processing unit described above.
, Are connected, the control signal b of the tri-state buffer becomes active (= 1), the tri-state buffers 31, 32, ..., 36 become conductive,
The internal data bus 3 and the internal data bus 3a are connected.

When data is transferred between the memory 1 and the outside of the integrated circuit, the address data input from the address bus terminal 4 is input to the multiplexer 6.
It indicates the address of the memory 1. The data in the memory cell indicated by this address is interfaced with the outside through the internal data bus 3a and the data bus terminal 5. At this time, in the buffer circuit 8, the control signal b becomes inactive (= 0), the tri-state buffers 31, 32, ..., 36 become non-conductive, and the internal data bus 3 and the internal data bus 3a are separated. To be done.

[0025]

According to the present invention, data can be transferred in parallel in the arithmetic unit and other processing units while the data stored in the memory is being output to the outside. The speed can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a memory control circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a gate circuit used in this embodiment.

FIG. 3 is a block diagram showing a memory control circuit according to another embodiment of the present invention.

FIG. 4 is a circuit diagram showing a buffer circuit used in this embodiment.

FIG. 5 is a circuit diagram showing a conventional memory control circuit.

[Explanation of symbols]

 1, 51; memory 2, 52; address register 3, 3a, 53; data bus 4; address terminal 5, 54; data terminal 6; multiplexer 7; gate circuit 8; buffer circuits 21-23; transfer gates 31-36; Tri-state buffer a, b; control signal

Claims (1)

[Claims] 1. In a memory control circuit of a semiconductor integrated circuit having a built-in memory, an address register for storing an address of the memory, an address input terminal for inputting address data from the outside of the integrated circuit, and an input from this address input terminal. A selected address or an address of the address register and outputs it as an address of the memory, a data input terminal for inputting data from the outside of the integrated circuit, a data input terminal and a memory connected to the memory. One data bus, a second data bus that handles internal data inside the integrated circuit, and a separation circuit that connects or disconnects the first data bus and the second data bus. Control circuit for semiconductor integrated circuit.