KR101285883B1 - signal processing method and apparatus for transmitting multiful processor signals to a shared memory - Google Patents

Abstract

The present invention relates to a memory that can be shared by two processors in a platform structure of a system on chip (SOC) having two or more processors, and a memory controller capable of controlling the memory. In particular, the present invention relates to a memory and a memory control unit in which two processors share a memory with each other, thereby reducing data transmission / reception time between the two processors so that each processor can be efficiently used.

SDRAM, memory transfer signal control, standby signal, PIN

Description

Signal processing method and apparatus for transmitting multiful processor signals to a shared memory

1 is a block diagram illustrating a prior art.

2 is a block diagram according to an embodiment of the present invention.

3 is a flowchart for explaining an embodiment of the present invention.

4 is a flowchart for explaining another embodiment of the present invention.

The present invention relates to signal processing, and more particularly, to a signal processing method and apparatus for transmitting a plurality of processor signals to one memory.

1 is a block diagram illustrating a prior art. Hereinafter, a method of processing an SDRAM transmission signal when a conventional memory is an SDRAM will be described with reference to FIG. 1.

The digital device includes at least two processors. Conventionally, SDRAMs and SDRAM controllers for controlling signals transmitted to the SDRAMs are allocated to each processor. That is, the first processor 100, the second processor 102, the first SDRAM controller 101, the second SDRAM controller 103, the first SDRAM 104, and the second SDRAM 105 are included. It is done by

Referring to the operation of the prior art using the above components, one processor is stored in its assigned DRAM through the SDRAM control unit connected to each processor. That is, the first processor accesses the first SDRAM through the first SDRAM controller, and the second processor accesses the second SDRAM through the second SDRAM controller. When two processors exchange data, they transmit and receive data using a bus.

When the first processor intends to transfer data to the second processor, the first processor stores the data in the first SDRAM through the first SDRAM controller. The second processor takes the stored data through the bus connection and stores the data in the second SDRAM allocated to the second SDRAM controller. Alternatively, when the first processor accesses the second SDRAM controller via a bus and stores data in the second SDRAM, the second processor reads data recorded by the first processor through the second SDRAM controller.

According to the prior art, when the first processor writes data to the second memory via the bus and the second processor reads the data again, or the data stored in the first SDRAM is read by the second processor via the bus connection. In the case of a small amount of data, it ends in a short time, but a large amount of data takes a lot of time. Therefore, the efficiency of each processor may be degraded and the performance of the overall system may be degraded. The system on a chip (SOC) may be increased due to an increase in the number of pins coming from the two memory controllers along with an increase in the cost of components according to two memories. There is also a problem that increases the production cost.

The present invention has been made to solve the problems of the prior art as described above, an object of the present invention is to provide a signal processing method for efficient data transmission and reception between processors. It also provides a way to improve overall system performance and reduce cost and volume.

In one aspect of the present invention, a signal processing apparatus for transmitting a plurality of processor transmission signals to one memory includes a memory transfer that receives signals directed to a memory and delivers the received signals to the memory sequentially in correspondence with the received order. And a memory configured to receive a signal from the signal controller and the memory transfer signal controller through one memory interface group and process the received signal.

In another aspect of the present invention, a signal processing apparatus for transmitting a plurality of processor transmission signals to one memory receives signals destined for a memory from at least two processors and transfers the received signals to the memory according to a memory transmission format. And a memory configured to receive a signal from the memory transfer signal controller and a memory interface group from the memory transfer signal controller.

In still another aspect of the present invention, a signal processing method for transmitting a plurality of processor transmission signals to a memory includes: receiving signals from a plurality of processors; And transmitting the received signals to the memory sequentially in the order in which they are received, and transmitting each received signal through the same memory interface.

In still another aspect of the present invention, a signal processing method for transmitting a plurality of processor transmission signals to one memory includes receiving and transmitting a first processor signal to a memory, receiving a standby signal from the memory; Storing the second processor signal and transmitting the standby signal to a controller of the second processor when receiving a second processor signal and transmitting the stored second processor signal to the first processor after a predetermined time according to the standby signal; And transmitting to the memory via a memory interface group to which a signal is transmitted.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following detailed description, together with the accompanying drawings, is intended to illustrate exemplary embodiments of the invention and is not intended to represent the only embodiments in which the invention may be practiced.

In the embodiments described below, the memory used in each processor system is a synchronous dynamic RAM (SDRAM) capable of operating at high speed by directly receiving and operating a main clock used by a central processing unit (CPU). Explain what was applied in the case. That is, in the case of the SDRAM, since the processor and the memory proceed in synchronization, the processor does not need a waiting time for accessing the memory, thereby allowing the processor to access the memory at high speed. However, it is obvious that the technical idea of the present invention can be applied to various cases as well as the case of using the SDRAM.

2 is a block diagram according to an embodiment of the present invention. 2, a digital device according to the present invention includes a first processor 200, a second processor 202, a first SDRAM controller 201, a second SDRAM controller 203, and a memory transmission signal controller 204. ), The SDRAM 205 and the memory interface group 206. Although FIG. 1 illustrates the case of including two processors, it is obvious that the present invention may be applied to a case including three or more processors.

Each of the SDRAM controllers 201 and 203 performs a function for storing a signal transmitted from the processors 200 and 202 connected to the SDRAM 205. That is, control information such as position information about the SDRAM 205, clock information for adjusting the operation clock of the SDRAM 205, and write or read data information are transmitted to the SDRAM 205.

The memory transfer signal controller 204 receives a signal from an SDRAM controller connected to each processor and transmits the signal to the one of the SDRAMs 205. That is, when the first processor signal and the second processor signal are sequentially transmitted, the memory transfer signal controller transfers the received signals to the SDRAM 205 according to the transmitted order. In addition, the SDRAM 205 performs a function of transmitting a signal transmitted to the processor side.

In this case, the SDRAM 205 may be required to transmit a signal according to a predetermined SDRAM transmission protocol. For example, whether the write signal or the read signal for the SDRAM is used, row and column information of each signal may be sequentially transmitted to process the signals normally received in the SDRAM. In this case, the memory transfer signal control unit transmits the received signals to the SDRAM so that the information about the row can be transmitted after the information about the column according to an example of the transmission protocol. The memory transfer signal controller may be configured as a separate function module, or may be implemented in a form in which a function is added to an existing controller.

The SDRAM 205 is not provided for each processor as in the related art, but is an SDRAM shared by a plurality of processors. By using the shared SDRAM, the volume of the digital device can be reduced. In addition, the speed of processing a large amount of data transmitted between the processors can be improved than when using a plurality of SDRAM.

The SDRAM 205 may transmit a wait signal to prevent simultaneous access when the transmission protocol described above is set. When the signal transmitted to the SDRAM 205 is a specific signal, it indicates that a connection process (for example, a recording process, a reading process, etc.) is in progress in the SDRAM 205. The wait signal may be transmitted to the memory transfer signal controller 204. That is, for example, when information on a column of position information is received by the SDRAM 205, the SDRAM 205 transmits the standby signal to the memory transfer signal controller. Thus, the memory transfer signal controller 204 may be prevented from transmitting another column information. In addition, the standby signals may be transmitted to the SDRAM controllers 201 and 202 so that the SDRAM controllers 201 and 202 may proceed without a series of errors. In order to transmit the standby signal to the memory transfer signal controller, a separate memory interface may be provided. That is, the standby signal may be transmitted by providing a pin for transmitting the standby signal.

A memory interface group 206 may be provided between the memory transfer signal controller 204 and the SDRAM 205 to move data and control signals. That is, the memory interface group 206 is used to transmit a signal from the memory transfer signal controller 204 to the SDRAM 205. The memory interface group 206 includes at least one memory interface. The memory interface may be classified according to a function. That is, the memory interface may be classified into a memory interface for transmitting data, a memory interface for transmitting a control signal, a memory interface for transmitting position information about the SDRAM, and the like.

In the case of SDRAM to which a plurality of processor signals are transmitted, each memory interface group may be allocated to each processor. In addition, the memory transfer signal controller may be provided between the processor and the SDRAM to arrange, ie, control, a plurality of processor signals into one signal and transmit the plurality of processor signals to the SDRAM through one interface group. have.

According to the present invention, the memory transfer signal controller 204 or a function thereof may be provided to provide the memory interface group 206 regardless of the number of processors in the device. That is, since the signals transmitted from the SDRAM controller connected to each processor are transmitted to the SDRAM 205 via the memory transfer signal controller 204, the SDRAM ( The number of memory interface groups 206 connected to 205 can be greatly reduced. An example in which the memory interface may be implemented is a pin mounted to transmit and receive data with the SDRAM. The number of pins connected to the SDRAM is a cost and volume sensitive part. Therefore, if the number of pins to connect with the SDRAM can be reduced, it can have a quite advantageous effect.

3 is a flowchart for explaining an embodiment of the present invention. Referring to FIG. 3, a method of reading data written by a first processor using a single SDRAM in a second processor will be described. Although FIG. 3 illustrates a memory controller and a memory, a case in which the memory is applied to an SDRAM which is an example of a memory will be described. That is, the memory controller of FIG. 3 is referred to as an SDRAM controller, and a memory is referred to as an SDRAM. However, it is obvious that the technical idea of the present invention is not limited to this. This also applies to the case of FIG. 4 below.

The first processor attempts to store data in the SDRAM. Therefore, the data signal is transmitted to the first SDRAM controller. The first SDRAM controller performs signal processing for receiving the data signal lamp and transmitting the same to the SDRAM. In order to store the data in the SDRAM, clock information for matching with an SDRAM clock, information about a storage location of the SDRAM, data information to be stored in the SDRAM, etc. should be transmitted to the SDRAM. The first SDRAM controller first transmits first location information to the memory transfer signal controller (S30). The first location information is information for indicating a storage location of the SDRAM, and may include information about a row or information about a column, and information about a column is generally transmitted first. In addition, each transmission signal may be transmitted to know whether it is a signal for recording, that is, a signal for storing or a reading. That is, in the case of the first location information, the first location information may be indicated as the first location information for recording and transmitted.

The memory transfer signal controller which has received the position information for recording transmits the received first position information to the SDRAM (S31). Upon receiving the position information on the column, the SDRAM transmits a standby signal to the memory transfer signal controller. This is to ensure signal transmission in accordance with the SDRAM transmission protocol. The first SDRAM controller transmits a signal including second position information, that is, information about a row and data information to be recorded, to the memory transfer signal controller (S33). The memory transfer signal controller receives the signal and transfers the signal to the SDRAM (34). Upon receiving the column and row position information and the data information through the above process, the SDRAM stores the received data information at a corresponding position according to the received position information (S35). As described above, when each location information is transmitted to the memory transmission signal control unit, the location information may be directly transferred to the memory one by one. Alternatively, the location information and data information may be transmitted to the memory transmission signal control unit before the reception information may be transmitted to the memory. have.

After the SDRAM stores data, the second processor attempts to read the stored signal. The second processor may know that data to be read and stored by transmitting and receiving simple information through a bus connected between the first processor and the second processor is stored in any position of the SDRAM, or by setting a predetermined transmission protocol and reading the read data. You can also know in advance the timing or location to try. At this time, even in the case of transmitting and receiving information through the bus as in the former case, since the amount of data transmitted and received is not a large amount of time in terms of time is not a big burden on the system.

The second SDRAM controller first transmits first location information to read the data stored in the SDRAM to be read by the second processor (S36). In this case, the first location information is also generally information about a column of the SDRAM location information. When the first position information for reading is transmitted to the memory transfer signal controller, the memory transfer signal controller transfers the first position information to the SDRAM (S37). In operation S38, second position information for reading, that is, information about a row, is transmitted to the memory transfer signal controller. The memory transfer signal controller which receives the second location information transfers the second location information to the SDRAM (S39). In this case, even when the signal transmitted from the second SDRAM controller is transmitted, the memory transfer signal controller may transmit the same signal through the same memory interface group as the signal transmitted from the first SDRAM controller. That is, in one embodiment of the present invention, not only a method of storing and reading a signal in the SDRAM through each memory interface per processor signal, but also a method of transmitting and receiving a plurality of processor signals to and from the SDRAM through one memory interface. Can also be used. Thus, according to the latter method, the number of memory interfaces (pins) can be reduced by half.

The SDRAM which has received the location information to be read in the above manner enables the second processor, that is, the second SDRAM controller to read the signal stored at the location corresponding to the location information (S40).

In the above embodiment, the case in which data is to be transmitted from the first processor to the second processor has been described. In the opposite case, the data may be stored in the SDRAM in the first processor and the first processor may read the stored data. You can also ship. In addition, the second processor may store data in the SDRAM and read the stored data again in the second processor.

4 is a flowchart for explaining another embodiment of the present invention. Referring to FIG. 4, the data written by the first processor is read by the second processor using one SDRAM, and is transmitted by the SDRAM to prevent simultaneous access or to guarantee signal transmission according to the SDRAM transmission protocol. A method of using a wait signal will be described.

The first processor attempts to write data in a predetermined area of the SDRAM through the first SDRAM control unit, and the second processor attempts to read data in a predetermined area of the SDRAM through the second SDRAM control unit. The first processor issues a write command to the first SDRAM controller, and the second processor issues a read command to the second SDRAM controller.

Each of the SDRAM controllers transmits an SDRAM access signal to the memory transfer signal controller according to an instruction sent from each processor (S50 and S53). The memory transfer signal controller sequentially transmits access signals transmitted from the two SDRAM controllers to the SDRAM (S51). The SDRAM processes the signals sequentially transmitted by two SDRAM controllers to perform a data write operation and a data read operation. In order to explain this embodiment, it is assumed that both the position information and the data to be recorded for the first processor signal are transmitted to the memory so that the read signal is transmitted from the second processor before the recording is completed.

At this time, when the current operation is not finished (data write operation sent by the first SDRAM controller) and another access signal comes in (data read access signal sent by the second SDRAM controller), the signal is stored in the memory transfer signal controller. The memory transfer signal controller informs the SDRAM controller to wait by transmitting a wait signal.

That is, the SDRAM, for example, transmits a standby signal to the memory transfer signal controller when the location information for recording is received from the first processor, thereby informing that the writing process is in progress. The wait signal may include information on an expected timing at which the recording process is completed. Therefore, when the read signal is transmitted before the one write process is completed, the memory transfer signal controller receiving the wait signal transmits the wait signal to the processor that transmitted the read signal so that an error does not occur in the read process. You can do that. Such a function of the SDRAM may be referred to as a pipeline function. The pipeline function is a storage device, for example, if a read or write command is received while performing a read or write command operation in a storage device, for example, if the read or write command is received, the current operation is continuously stored and then executed. It means the function to perform the stored command operations after this completion.

When a read signal of the second processor is transmitted to the memory transfer signal controller when the writing process of the first processor is transferred to the SDRAM and the wait signal is transmitted to the memory transfer signal controller, the memory transfer signal controller The read signal of the second processor is not directly transmitted to the SDRAM but stored in the memory transfer signal controller (S54). The wait signal received from the SDRAM is transferred to the second SDRAM controller on the second processor side so that the second processor may attempt to read at an appropriate timing (S56). When the current operation (data write operation) is completed, the changed standby signal may be transmitted again to indicate that the work is finished.

When the recording process of the first processor may be terminated or the reading process of the second processor may proceed after a predetermined time according to the wait signal, the memory transfer signal controller transmits the stored position from the second SDRAM controller. The information is transmitted to the SDRAM (S57). The second processor may read data stored at the location according to the location information.

Even in this embodiment, the signal for the first processor and the signal for the second processor may be transmitted through the same memory interface group. Thus, the number of pins can be reduced.

The first processor can write data to the memory and the second processor can read the data from the memory and vice versa. This means that one processor can be shared by two processors, eliminating the need to transfer data between two processors by using a bus, reducing the time required to transfer data between two processors, and in some cases, a bus interface between two processors. You can also remove the logic for the interface.

The first processor may write data to the memory and then perform another operation, and the second processor may directly read data stored by the first processor from the memory, thereby increasing efficiency of each processor.

In addition, since the memory is reduced from two to one, the area occupied by the memory is reduced, and the number of pins for accessing the memory can be reduced by half, thereby reducing the cost.

 The present invention described above may be included or used in a digital device. Examples of the digital devices include mobile terminals, personal digital assistants (PDAs), portable multimedia players (PMPs), and the like. The memory may be not only the above-described SDRAM but also an SRAM, a PSRAM, and the like.

Those skilled in the art to which the present invention described above belongs will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. It is therefore to be understood that the embodiments described above are in all respects illustrative and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and from the same concept are to be construed as being included in the scope of the present invention will be.

According to the present invention, signal processing for efficient data transmission and reception between processors can be performed. It can also improve the performance of the overall system, reducing cost and volume. In addition, there is an effect that multiple processors can use one memory.

Claims (20)

A memory transfer signal controller configured to receive signals destined for a memory and transfer the received signals to the memory sequentially in a received order; And And a memory configured to receive a signal from the memory transfer signal controller through one memory interface group and process the received signal. The memory transmits a standby signal to the memory transfer signal control unit after receiving a specific signal among the received signals, wherein the specific signal is row information of information on a storage location of the memory, Signal processing apparatus for transmitting a plurality of processor transmission signals to one memory. delete delete The memory transfer signal control unit of claim 1, wherein when the memory transfer signal control unit receives a signal to be transmitted to the memory without conforming to a memory transfer protocol, Transfer the standby signal to the side that has transmitted the signal to be transmitted to the memory, in accordance with the memory transfer protocol; Store a signal to be transmitted to the memory inconsistent with the memory transfer protocol, And transmitting the stored signals to the memory after a predetermined time according to the standby signal. A memory transfer signal controller configured to receive signals destined for a memory from at least two processors and transfer the received signals to the memory according to a memory transfer format; And And a memory configured to receive a signal from the memory transfer signal controller through one memory interface group. The memory transmits a plurality of processor transmission signals to one memory when the received signal is row information among row information of the storage location of the memory. Signal processing device for. delete The method of claim 5, wherein the memory transfer signal controller, when receiving a signal for row information transmitted from another processor within a predetermined time according to the wait signal, stores the signal transmitted from the other processor. And a plurality of processor transmission signals to one memory, wherein the standby signal is transmitted to the other processor. The method of claim 7, wherein the memory transfer signal controller transmits a plurality of processor transmission signals to one memory after a predetermined time according to the standby signal. Signal processing device for transmission. 6. A signal according to any one of the preceding claims, wherein the signals directed to the memory are for writing predetermined information into the memory and for reading out predetermined information stored in the memory. Signal processing apparatus for transmitting a plurality of processor transmission signals to one memory, characterized in that. 10. The signal of claim 9, wherein each signal includes at least one of column information for the memory and data information for writing. Processing unit. The memory transfer signal control unit according to any one of claims 1 to 5, wherein the memory transfer signal control unit corresponds to the delayed time when data corresponding to a read from the memory is transmitted later than an expected time according to a memory transfer protocol. The signal processing device for transmitting a plurality of processor transmission signals to one memory, characterized in that for receiving a standby signal and transmitting to the processor. In the signal processing method for transmitting a plurality of processor transmission signals to one memory, Receiving signals from a plurality of processors; Transmitting the received signals to the memory in sequential order corresponding to the received order, and transmitting each received signal through the same memory interface; And Receiving a standby signal from the memory in response to a specific signal of the received signal, And the specific signal is row information among information on a storage location of the memory. delete The method of claim 12, wherein when the received signal is a signal to be transmitted to the memory that does not conform to the transfer protocol of the memory, Transmitting the standby signal to a side that has transmitted a signal to be transmitted to the memory inconsistent with the memory transmission protocol; Storing a signal to be transmitted to the memory inconsistent with the memory transfer protocol; And And transmitting the stored signal to the memory after a predetermined time according to the standby signal. delete delete delete delete delete delete

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