JPS57176463A - Data processor - Google Patents

Data processor

Info

Publication number
JPS57176463A
JPS57176463A JP6117981A JP6117981A JPS57176463A JP S57176463 A JPS57176463 A JP S57176463A JP 6117981 A JP6117981 A JP 6117981A JP 6117981 A JP6117981 A JP 6117981A JP S57176463 A JPS57176463 A JP S57176463A
Authority
JP
Japan
Prior art keywords
storage device
auxiliary storage
memory access
main storage
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6117981A
Other languages
Japanese (ja)
Inventor
Seiji Izumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6117981A priority Critical patent/JPS57176463A/en
Publication of JPS57176463A publication Critical patent/JPS57176463A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Abstract

PURPOSE:To obtain high performance and excellent cost to performance ratio, by using a high speed device such as semiconductor memory element as an auxiliary storage device. CONSTITUTION:A main storage device 19 and an auxiliary storage device 21 asynchronizingly perform data transmission with a central processing unit 1 at each memory cycle. Between the main storage device 19 and the auxiliary storage device 21, the memory access of the main storage device 19 is started in synchronizing with and following to the memory access of the auxiliary storage device 21 for data transfer. In data transfer between the main storage device and the auxiliary storage device 21, the memory access of the device 19 is synchronized with and followed to that of the auxiliary storage device 21 for starting, and data are mutually converted within one memory access between both the devices.
JP6117981A 1981-04-24 1981-04-24 Data processor Pending JPS57176463A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6117981A JPS57176463A (en) 1981-04-24 1981-04-24 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6117981A JPS57176463A (en) 1981-04-24 1981-04-24 Data processor

Publications (1)

Publication Number Publication Date
JPS57176463A true JPS57176463A (en) 1982-10-29

Family

ID=13163668

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6117981A Pending JPS57176463A (en) 1981-04-24 1981-04-24 Data processor

Country Status (1)

Country Link
JP (1) JPS57176463A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5255449A (en) * 1975-10-31 1977-05-06 Toshiba Corp Microprocessor
JPS52122436A (en) * 1976-04-07 1977-10-14 Fuji Electric Co Ltd Data transfer control system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5255449A (en) * 1975-10-31 1977-05-06 Toshiba Corp Microprocessor
JPS52122436A (en) * 1976-04-07 1977-10-14 Fuji Electric Co Ltd Data transfer control system

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