JPS5668829A - Queuing control system - Google Patents

Queuing control system

Info

Publication number
JPS5668829A
JPS5668829A JP14594879A JP14594879A JPS5668829A JP S5668829 A JPS5668829 A JP S5668829A JP 14594879 A JP14594879 A JP 14594879A JP 14594879 A JP14594879 A JP 14594879A JP S5668829 A JPS5668829 A JP S5668829A
Authority
JP
Japan
Prior art keywords
queuing
bus
time
cpu
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14594879A
Other languages
Japanese (ja)
Other versions
JPS6221149B2 (en
Inventor
Mitsuo Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14594879A priority Critical patent/JPS5668829A/en
Publication of JPS5668829A publication Critical patent/JPS5668829A/en
Publication of JPS6221149B2 publication Critical patent/JPS6221149B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
  • Exchange Systems With Centralized Control (AREA)

Abstract

PURPOSE: To increase the process efficiency of the CPU for the data transfer queuing control system for an electronic exchange unit, by setting the queuing time in accordance with the transmission delay time between the CPU and each terminal unit and thus decreasing the ineffective time.
CONSTITUTION: The returning bus 16 is provided between the CPU2 and each of the terminal units 31W3n. In other words, the address transmitted to the address bus 6 when the in-instruction is transmitted is collated at each of the terminal units 31W3n. The terminal unit having a coincidence of collation knows that it has been selected, and then transmits the coincidence signal to the bus 16 via the bus driver e.g. 151. When the signal 16 is detected at the CPU2, the queuing signal is cancelled. Accordingly, the queuing time can be made different with every terminal unit. As a result, the ineffective time can be reduced to increase the process efficiency of the CPU.
COPYRIGHT: (C)1981,JPO&Japio
JP14594879A 1979-11-09 1979-11-09 Queuing control system Granted JPS5668829A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14594879A JPS5668829A (en) 1979-11-09 1979-11-09 Queuing control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14594879A JPS5668829A (en) 1979-11-09 1979-11-09 Queuing control system

Publications (2)

Publication Number Publication Date
JPS5668829A true JPS5668829A (en) 1981-06-09
JPS6221149B2 JPS6221149B2 (en) 1987-05-11

Family

ID=15396735

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14594879A Granted JPS5668829A (en) 1979-11-09 1979-11-09 Queuing control system

Country Status (1)

Country Link
JP (1) JPS5668829A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6389152U (en) * 1986-11-27 1988-06-10

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6389152U (en) * 1986-11-27 1988-06-10
JPH0530198Y2 (en) * 1986-11-27 1993-08-02

Also Published As

Publication number Publication date
JPS6221149B2 (en) 1987-05-11

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