JPS57111725A - Data transmission control system - Google Patents

Data transmission control system

Info

Publication number
JPS57111725A
JPS57111725A JP18778480A JP18778480A JPS57111725A JP S57111725 A JPS57111725 A JP S57111725A JP 18778480 A JP18778480 A JP 18778480A JP 18778480 A JP18778480 A JP 18778480A JP S57111725 A JPS57111725 A JP S57111725A
Authority
JP
Japan
Prior art keywords
register
command
bus
data
status
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18778480A
Other languages
Japanese (ja)
Inventor
Noboru Yamamoto
Toshiaki Ii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18778480A priority Critical patent/JPS57111725A/en
Publication of JPS57111725A publication Critical patent/JPS57111725A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Abstract

PURPOSE:To effectively transfer and process a data, by providing a status register on a channel device, and easily setting a command or a status in a main storage. CONSTITUTION:A channel device 5 is connected to a main processing device 1 through a common bus 3, and in accordance with control of the device 5, a data in a main storage device 2 is transferred to a subchannel device 11. Between a subcommon bus 10 connected to a subprocessing device 13 of this device 5, and the common bus 3, a status register 15 is provided. Also, a head address stored in the device 2 is set to an interface register 16 of the device 5, and a start request is set to the register 15. Subsequently, the head address of the command set to the register 16 is detected by the control processing device 13, a DMA controlling circuit 6 is started, the command on the bus 3 is read, and the register 15 is reset, by which a data transfer to the device 11 is executed effectively.
JP18778480A 1980-12-29 1980-12-29 Data transmission control system Pending JPS57111725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18778480A JPS57111725A (en) 1980-12-29 1980-12-29 Data transmission control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18778480A JPS57111725A (en) 1980-12-29 1980-12-29 Data transmission control system

Publications (1)

Publication Number Publication Date
JPS57111725A true JPS57111725A (en) 1982-07-12

Family

ID=16212156

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18778480A Pending JPS57111725A (en) 1980-12-29 1980-12-29 Data transmission control system

Country Status (1)

Country Link
JP (1) JPS57111725A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63279351A (en) * 1987-05-12 1988-11-16 Fujitsu Ltd Dma transfer controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63279351A (en) * 1987-05-12 1988-11-16 Fujitsu Ltd Dma transfer controller
JPH0568731B2 (en) * 1987-05-12 1993-09-29 Fujitsu Ltd

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