JPS56149660A - Composite computer system - Google Patents

Composite computer system

Info

Publication number
JPS56149660A
JPS56149660A JP5288580A JP5288580A JPS56149660A JP S56149660 A JPS56149660 A JP S56149660A JP 5288580 A JP5288580 A JP 5288580A JP 5288580 A JP5288580 A JP 5288580A JP S56149660 A JPS56149660 A JP S56149660A
Authority
JP
Japan
Prior art keywords
idle
data
processors
idle state
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5288580A
Other languages
Japanese (ja)
Other versions
JPS5826057B2 (en
Inventor
Hideo Uruga
Hiroo Takenouchi
Minoru Hatada
Kunio Hiyama
Isao Shimizu
Akira Toda
Mitsuru Imai
Hisayoshi Inamori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Hitachi Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Nippon Telegraph and Telephone Corp filed Critical Hitachi Ltd
Priority to JP5288580A priority Critical patent/JPS5826057B2/en
Publication of JPS56149660A publication Critical patent/JPS56149660A/en
Publication of JPS5826057B2 publication Critical patent/JPS5826057B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system

Abstract

PURPOSE:To shorten the queuing time for use of data bus, by detecting at a high- speed the fact that all processors are idle through a simple constitution. CONSTITUTION:Plural processors P0-Pn are connected to the common data bus D via the communication devices C0-Cn, and a communication of data a given among the processors. The processor P consists of the communication device C, idle control flip-flop FF, OR circuit and open collector gate G. The device C corresponding to the receiving processor P sets the idle control FF when the reception of data starts to cancel an idle state, and the receiver side is set under the idle state when the transmission of data is over. Thus an idle control is possible for the system as a whole. In such way, the idle state is detected with a simple constitution of the circuit.
JP5288580A 1980-04-23 1980-04-23 complex computer system Expired JPS5826057B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5288580A JPS5826057B2 (en) 1980-04-23 1980-04-23 complex computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5288580A JPS5826057B2 (en) 1980-04-23 1980-04-23 complex computer system

Publications (2)

Publication Number Publication Date
JPS56149660A true JPS56149660A (en) 1981-11-19
JPS5826057B2 JPS5826057B2 (en) 1983-05-31

Family

ID=12927324

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5288580A Expired JPS5826057B2 (en) 1980-04-23 1980-04-23 complex computer system

Country Status (1)

Country Link
JP (1) JPS5826057B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083143A (en) * 1983-10-14 1985-05-11 Nec Corp Synchronizing start circuit
JPS6083145A (en) * 1983-10-14 1985-05-11 Nec Corp Emulator reset system of microcomputer
JPS6083144A (en) * 1983-10-14 1985-05-11 Nec Corp Synchronizing break circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6083143A (en) * 1983-10-14 1985-05-11 Nec Corp Synchronizing start circuit
JPS6083145A (en) * 1983-10-14 1985-05-11 Nec Corp Emulator reset system of microcomputer
JPS6083144A (en) * 1983-10-14 1985-05-11 Nec Corp Synchronizing break circuit
JPH044614B2 (en) * 1983-10-14 1992-01-28
JPH044615B2 (en) * 1983-10-14 1992-01-28

Also Published As

Publication number Publication date
JPS5826057B2 (en) 1983-05-31

Similar Documents

Publication Publication Date Title
JPS54145406A (en) Packet transmission system
ES8501189A1 (en) Teletext device with reduced page-access time.
JPS56149660A (en) Composite computer system
JPS561642A (en) Transmission error generating device
JPS5723166A (en) Parallel data processing system driven by tree structure data
JPS5441602A (en) Loop type data delivery system
JPS5410601A (en) Representative address control system for loop communication system
JPS5671358A (en) Control system for button telephone
JPS55107358A (en) Data transmission system
JPS5297603A (en) Reception system for interface signal
JPS5534522A (en) Time sheaking multiple control system
JPS5368103A (en) Data transmission system
JPS5333011A (en) Information processing console unit
JPS5514742A (en) Circuit multiplication system
JPS57212850A (en) Data transmitter
JPS57138240A (en) Hairpin network
JPS54105902A (en) Communication control device
JPS5294716A (en) Control system for facsimile communication, etc.
JPS52154981A (en) Remote monitoring control system
JPS57111155A (en) Data transmission and receiving system
JPS56120242A (en) Checking system for transmission data
JPS5313818A (en) Signal transmission system
JPS5476032A (en) Communication control system
JPS5676661A (en) Data transmission control circuit
JPS5768950A (en) Storage type data transfer system