JPS6083143A - Synchronizing start circuit - Google Patents

Abstract

PURPOSE:To use simultaneously plural emulators which are so far used individually by using a signal which supplies a desired program to a developing device of a prototype system and discriminating an execution period from a non-execution period. CONSTITUTION:A terminal (c) is connected to a terminal equivalent to the terminal (c) having the same type of a synchronizing start circuit. A switch SW turns on only one of emulators constituting a multi-emulator. Other emulators constituting said multi-emulator emulate a desired program by a buffer circuit serving as the logical circuit of an open collector type. Then an emulation signal is outputted to discriminate an execution period from a non-execution period of programs. At the same time, the emulation signals sent from other emulators are inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a broad type system development device (hereinafter referred to as an emulator) using a microcomputer.

The present invention provides a device that allows a plurality of emulators, which were conventionally used individually, to be used simultaneously, and each emulator can be started in synchronization with one emulator.

The present invention is a system in which multiple emulators are used at the same time (hereinafter referred to as multi-emulator), and is realized by synchronizing each emulator with one emulator and starting all emulators. This is a synchronous start circuit that allows a computer (hereinafter simply referred to as an emulation CPU) to delay its own operating functions.

The present invention uses the C terminal of FIG. 1 by connecting it to a terminal equivalent to the C terminal of FIG. 1 of a synchronous start circuit having the same type as the present invention. Further, the SW has a configuration in which only one emulator constituting the multi-emulator is turned on. Buffer (Bu) is an open collector type logic circuit.
ffer ) circuit outputs a signal (hereinafter referred to as emulation signal) to other emulators that make up the multi-emulator, distinguishing between a period in which the target program is run on the emulator (hereinafter referred to as emulation) and a period in which it is not possible to execute it (hereinafter referred to as emulation). This format allows input of emulation signals from other emulators as well as input signals from other emulators.

The present invention uses an open collector type logic gate circuit to wire the emulation signal (
The basic operating principle is that it can be connected (wired).

The present invention will be described below with reference to FIG. 1, which is an embodiment.

When performing emulation by configuring the emulator as a multi-emulator, the logic of the C terminal is affected by the status of other emulators that make up the f/lz emulator, and when all emulators that make up the multi-emulator are in the emulation state, the logic of ``l'', otherwise, the logic is ``0'' when at least one of the emulators constituting the multi-emulator is not in the emulation state. However, the emulation signal is active High and logic 1. Now, if we apply the signals of the a, b, and C terminals in Figure 2 to the a, b, and C terminals of the circuit in Figure 1, respectively, when the b terminal changes from 0 to 1, the emulator with this circuit emulates However, since other emulators have not yet entered the emulation state, the C terminal is
The period tl-t2 is n0. Therefore, the inputs of 05 are both 1, and the output is 0. This 05 output signal is G2
Through the AND circuit, Jl is activated and M is placed in a waiting state. However, M is active Low. Then, all emulators that make up the multi-emulator enter the emulation state (t2C) [continued from previous @,
At the moment when t2 arrives, the C terminal becomes l, and one of the inputs of 05 becomes 0 due to the inverter circuit of G4, and the output of G5 changes from 0 to 1, passing through G2 and turning gl. is set to 1 to release M from the waiting state and start emulation.

When t2 elapses, the wait signal from the C terminal is validated by the zero logic circuit of Gl, activates A'l through the AND circuit of j9G2, and inputs the wait signal to M, thereby operating the emulator y7 properly.

When performing Emmy V-version with a single emulator having this circuit without configuring it as a multi-emulator, the C terminal is used in an open state, so the signal level of the C terminal depends on the emulation signal of this emulation at the b terminal. One of the inputs of G5 is always logic 0, so the output of 05 is 1.9. The output of G5 does not activate l, Jl is only activated by the signal from a, and it can be made valid only for the emitter rate N/period by the zero circuit of Gl. .

According to the present invention, as described above, if the emulation CPU has a function that can delay its functions, it is possible to perform synchronous startup according to the present invention.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a synchronous start circuit according to the present invention, and FIG. 2 is a drawing for explaining the operation of the circuit shown in FIG. 1. Gl...(JR circuit, G2...AND
Circuit, G3...Open collector type buffer circuit, Ga---INV'ERTER circuit,
G 5--・-NAND circuit, M... Micro converter with a function to wait for operation, 几...
...Resistor, SW...Switch. The input line of the terminal that controls the function of waiting fc for the operation of l...M in FIGS. 1 and 2 and the signal on that line, a... in FIGS. 1 and 2. ...The input terminal for the wait signal of the target system and its signal, b in Figs. 1 and 2......The emulation signal input terminal and its signal, C in Figs. 1 and 2... ...Output of emulation signals to other emulators, input terminals from other emulators, and their signals.

Claims (1)

[Claims] When using multiple development devices for a broad-type system using microcomputers, a signal is used to distinguish between a period in which the target program is executed by the development device and a period in which it is not executed. Synchronous start circuit connected to other broad type system development equipment through logic gate circuit.