JPH01241665A - Reset system for multi-processor system - Google Patents

Abstract

PURPOSE:To easily reset a multi-processor system by causing the whole system to be a reset condition when the reset switches of respective processors are operated more than a set number within a constant time and causing only the correspondent processor to be the reset condition when the switches are operated less than the set number. CONSTITUTION:A means is provided to convert the condition of a reset switch 17 to an electric signal and to detect the number for the reset switch 17 to be operated within the constant time. When it is detected by this detecting means that the reset switch 17 is operated less than the set number, the reset operation of a correspondent processor 1 (2, 3) is executed. Then, when it is detected by the detecting means that the switch is operated more than the set number, the reset operation is executed to the whole system. Thus, when one reset switch 17 is operated, the reset for the unit of the processors and the reset of the whole system can be executed.

Description

Detailed Description of the Invention "Field of Industrial Application" The present invention is a multiprocessor system in which when the reset switch is operated more than a set number of times within a certain period of time, the entire system is reset, and the The present invention relates to a reset method for a multiprocessor system in which a reset operation is performed in units of processors when a reset switch is operated less than the number of times.

"Prior Art" When resetting a multiprocessor system in which a plurality of processors exist, there are cases where only each processor is reset, and cases where all processors are reset simultaneously.

That is, when each processor is returned to its initial state, only each processor is reset, and when the system is returned to its initial state and started at the same time, the entire system is reset.

In order to cope with these problems, in the conventional technology, a switch for resetting each processor and a switch for resetting the entire system are provided separately, and these switches are operated as appropriate.

"Problem to be Solved by the Invention" In the conventional technology, as mentioned above, it is necessary to separately provide a switch for resetting each processor and a switch for resetting the entire system. The conventional method was to install a switch for resetting the entire system, or to add a separate unit and provide a switch for resetting the entire system, and for the processor to provide a switch for resetting each processor. Therefore, in the former method, the number of switches increases, and there is a risk of erroneous operation, such as resetting the entire system due to the selection method of the switches, even though the intention was to perform an individual reset. Furthermore, the latter method has the disadvantage of increasing hardware.

The present invention solves the above-mentioned drawbacks of the prior art, and provides a reset system that can reset each processor and the entire system by operating a 1gA reset switch in a multiprocessor system. The purpose is to provide a method.

"Means for Solving the Problem" In a multiprocessor system equipped with multiple processors, a 1g reset switch is provided for each processor, and each processor's reset switch is activated a set number of times or more within a certain period of time. When operated, the entire system is reset, and when operated less than the set number of times, only the processor concerned is reset.

"Function" A means is provided to convert the state of the reset switch into an electrical signal and detect the number of times the reset switch has been operated within a certain period of time, and this detection means detects that the reset switch has been operated less than the set number of times. When it is detected that the processor has been operated a set number of times or more, a reset operation is performed for the entire system when the detection means detects that the processor has been operated a set number of times or more.

Embodiment FIG. 1 is a diagram showing an example of a multiprocessor system to which the present invention is applied. In Figure 1, 1.2.3
represents the processor, 4.5.6 represents each processor 1.2.
3 shows the reset circuit mounted on the main unit. Each of the reset circuits 4, 5, and 6 is provided with a reset switch 17, which will be described later. In addition, each reset circuit 4
．． 5.6 is a system reset means that resets the entire system when each of the reset switches 17 is operated a set number of times or more within a certain period of time; When operated, the corresponding processor 1, 2, or 3
and means for setting only the reset state.

Although the number of times the reset switch 17 is set is arbitrary, the following explanation will be made assuming that the number of times the reset switch 17 is set is two times.

7.8.9 connects the internal bus of each processor 1.2.3 to 1
0.11.12 connects the reset signal line to 13.14.1
5 indicates a system reset signal line, and 16 indicates a system bus. The reset signal RESET* is a signal that resets each processor 1.2.3, and the system reset signal 5YSRESET* is a signal that resets the entire system.
SRESET* can be output from the reset circuit 4.5.6 of any processor 1.2.3.

FIG. 2 is a circuit diagram of the reset circuit 4, and FIG. 3 is a circuit diagram of the reset circuit 4.
It is a figure which shows the waveform of each part of a figure. Note that the reset circuit 5
．． Since reset circuit 6 is configured exactly the same as reset circuit 4, its explanation will be omitted.

In FIG. 2, 17 is a reset switch, 18.1
9 is a pull-up resistor, 20.21 is an AND circuit, 2
2 is a pro-assembly resistor, 23 is a shift register, 24.
25 is a delay, 26.27 is a Schmitt trigger type inverter, 28 is a negative logic OR circuit, 29.30 is an inverter, 3 is a negative logic OR circuit, 32 is a negative logic AN
D circuits are shown respectively.

The reset switch 17 is a non-locking type having two poles, one normally open and one normally closed. Resistor 18, resistor 19 and NAND circuit 20, N
The AND circuit 21 constitutes a chattering removal circuit. The resistor 22, shift register 23, delay 24, delay 25, Schmitt trigger inverter 26, Schmitt trigger inverter 27, negative logic OR circuit 28, and negative logic AND circuit 32 constitute a timing control section. . The negative logic OR circuit 31 has a function of converting the 5YSRESET* signal inputted from the outside into a RESET signal.

FIG. 3 is a diagram showing waveforms of various parts of the circuit of FIG. 2.

(A> is the output of the chattering removal circuit, (B) is the output of QA of the shift register 23, (C) is the output of the shift register 2
(D> is the output of the Schmitt trigger type inverter 26, (E) is the output of the Schmitt trigger type inverter 27, (F) is the clear input of the shift register 23, (G) is the negative logic This is the output of the AND circuit 32.

Next, the operation of the above embodiment will be explained. When the reset switch 17 is pressed, the output (At) of the chattering removal circuit becomes H, and the shift register 23 is operated. Then,
The output (B) of the shift register 23 becomes H, and the signal passes through the inverter 29 and the negative logic OR circuit 31, and is sent to the RE.
Set the SET* signal to the operating value of L. At the same time, after the output (B) of the shift register 23 becomes H, the delay 24
During the set time t1, the input of the shift register 23 (A>
is monitored, and if the reset switch] 7 is not pressed during that time, the negative logic AND signal (G) of the output (D) of the Schmitt trigger type inverter 26 and the output (C) of the shift register 23 is output. Then, the clear signal (F) of the shift register 23 becomes clear, so the shift register 23 is cleared and RESET* returns to H.

If the reset switch is further pressed while the input of the shift register 23 (A>) is being monitored, the output (C) of the shift register 23 becomes H, and the signal passes through the inverter 30 and sets 5YSRESET* to the operating value. The output (C) of the shift register is the set time of delay 25 ↑2t
fr! ! After that, the signal (E) is passed through a delay 25 and a Schmitt trigger type inverter 27. Then,
The clear signal (F) of the shift register 23 becomes L, the shift register 23 is cleared, and the RESE * signal, 5
Both YSRESET* signals return to H.

When the external 5YSRESET* signal reaches the operating value of L,
The signal passes through a negative logic OR circuit 31, making the RESET* signal the predetermined operating value.

Now, when the reset switch 17 of the processor 1 is pressed once, as described above, a reset signal is output to the internal bus 7, and the processor 1 is reset within a certain period of time. If pressed again, a system reset signal is output that resets the entire system. Upon receiving the system reset signal, the reset circuit 5.6 of the processor 2.3 outputs the reset signal to the internal bus 8.9, putting each processor 2.3 in a reset state. Similarly, when the reset switch 1 to 17 of the processor 2.3 is operated, if it is pressed once, only processor 2 or processor 3 is reset, and if it is pressed again within a certain period of time, will reset the entire system.

"Effects of the Invention" As is clear from the above description, according to the present invention, it is easy to reset a multiprocessor system, and the number of switches can be reduced to 1/2. This can prevent erroneous operations such as pressing the system reset button by mistake.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing an example of a multiprocessor system to which the present invention is applied, Fig. 2 is a circuit diagram of the main part of the embodiment of the present invention, and Fig. 3 is a diagram showing waveforms of each part of Fig. 2. It is. In the figure, 1.2.3 is the processor 4.5.6 is the reset circuit 7.8.9 is the internal bus 10.11.12 is the reset signal line 13.14.15 is the system reset signal line 1G is the system bus 17 The reset switch 18.19 is a resistor 20.21 is NANDAND.The D circuit resistor 23 is a shift register 24.25 is a delay 26.27 is a Schmitt trigger type inverter 28 is a negative logic OR circuit 29.30 is an inverter 31 is a negative logic The logical OR circuit 32 is a negative logic AND circuit.

Claims (1)

[Claims] In a multiprocessor system including a plurality of processors, each processor is provided with a reset switch, and each processor is provided with a reset switch.
a system reset means that resets the entire system when the switch is operated more than a set number of times within a certain period of time, and resets only the corresponding processor when the reset switch is operated less than the set number of times; 1. A reset method for a multiprocessor system, characterized by comprising means for: