SU924699A1 - Computer - Google Patents

Description

(54) COMPUTATIONAL DEVICE

The invention relates to computing and can be used in arithmetic devices of electronic computers.

A computing device is known that contains units of alali units and zeros, a block of equivalence, triggers for the prohibition of the analysis of units and nil. lei, groups of elements AND, forming differences by non-coincidence and equality, groups of elements OR, elements AND, OR, inverters, trigger 1.

 However, the known device is characterized by a large volume of heating and a low speed.

The closest to the present invention is a device for determining the difference of two numbers, comprising a pulse generator connected to the first input of the first element I, the second input of which is connected to the zero output of the RS flip-flop, R is the input, the last is connected to the recording bus of the second number, the first and the second counters, the installation inputs of which are connected respectively to the recording buses of the first and second, numbers, the second element is AND, the element or, the counting trigger, whose zero input is connected to the inverse output of the RS flip-flop, and the counting input from to by the element OR, the inputs of which are connected respectively to the outputs of the first and second counters, and the direct output of the counting trigger is connected to the S input of the trigger H8 and to the first input of the second element I, the second input of which is connected to the pulse generator, and the output to the output bus device, the output of the first element And is connected to the counting inputs of the counters 2.

15

The purpose of the invention is to expand the functionality of the device, which consists in the possibility of the simultaneous determination by the device of both the difference and the sum of two

20 binary numbers.

The goal is achieved by the fact that a computing device containing a pulse generator, two And elements, two counters, an RS flip-flop

25 and a counting trigger, with the output of the pulse generator connected to the first input of the first element I, the installation inputs of the first and second counters are connected to the recording buses of the first and second number of the device. respectively, the output of the second element AND is connected to the output of the device difference, contains the elements OR NOT, I-NB, the switch, the first and second D-flip-flops, 0 whose inputs are connected to the device mode setting bus, the synchronous input of the first D-flip-flop is connected to the output of the pulse generator, and the output with the second input of the first element and, the third input of which is connected to the output of the element NAND, and the output to the counting input of the counting trigger and the first information input of the switch, the second information input of which is connected to the output of the counting trigger the trigger, the synchronous input of the second D-flip-flop, the counting inputs of the first and second counters and the first input of the second element I, the second input of a koporo is connected to the inverse output of the RS-trigger and the first control input of the switch, the second control input of which is connected to the output of the second D- the trigger, and the third control input of the switch is connected to the direct output of the RS flip-flop, the S input of which is connected to the input bus of the initial setup and the inputs of the initial setup of the second D-flip-flop, counting trigger, first and second counters, the second counter is connected to the first inputs of the elements AND-NOT and OR-NOT; the output of the second counter is connected to the second inputs of the elements AND-NOT and OR-NOT; The output of the element OR-NB is connected to the R input of the RS flip-flop, the output of the second element AND connected to the output of the difference device, the output of the switch is connected to the output of the sum of the device. Figure 1 shows the functional diagram of the computing device f in figure 2 - the timing diagram of the operation of the device. The device includes a pulse generator 1, the first counter 2 the second counter 3, the first element I 4, the counting trigger 5, the element OR-H 6, the switch 7 RS-flip-flop 8, the first D-flip-flop 9, the second D-flip-flop l the second element And 11, the element IS-NOT 12, the input bus of the initial installation 13, the Zina 14 recording of the first number, the bus 15 recording the second number, the bus 16 setting the mode, the output of the sum 17, the output of the difference 18, the output control bus 19. The device operates as follows at once. Bus 13 is given a pulse of the initial setting of negative polarity, which sets the RS flip-flop 8 to 1, and the second D flip-flop 10, the counting flip-flop 5, the counters 2 and 3 to zero. The output of the second D-flip-flop 10 prohibits the passage of pulses through switch 7. On the write buses 14 and 15, respectively, the inverse values of the first and second numbers are received, which are recorded in the corresponding (and these counters (except for the higher bits on which the transfer is formed)). is fed to bus 16. Counting pulses from the output of the pulse generator are fed to the C input of the first D-flip-flop 9 and the information on the D-input, in this case that permits the passage of counting pulses, is written to it on the positive front. in through the element 4. The counting pulses from the output of the logical element I 4 are fed to the first information input of the switch 7 and to the counting input of the counting trigger 5, on which the frequency is divided by 2 on the negative front. The pulses from the output of the counting trigger 5 arrive at the counting inputs counters 2 and 3 (which operate on the negative -frontage), on the second information input of the switch 7, on the second input of the And 11 element and on the C input of the second D-flip-flop 10. On the negative front, a logical one is written to the second D-flip-flop 10 at the presence of a signal Work), which arrives at the second control input of switch 7 and permits the passage of pulses through it from the first input. After one of the counters has overflowed, at the output of the OR-NOT element b, a logical zero signal appears that goes to the RS input of the RS flip-flop, the latter is set to allow the passage of pulses through and ii and switches switch 7 to in which the pulses from the output of the counting rigger 5 arrive at its output. Overflow of the next counter results in the signal End of Work (output control bus 19) at the input of the IS-NOT element 12, which prohibits the passage of counting pulses through the element And 4. Thus, at the output of the element 11 and 11 (at the output of the difference 18), pulses appear, the number of which is 7 equal to the difference of two numbers, in that counter (which filled before (it corresponds to the fact that it contains a smaller number) is written parallel code difference of two numbers, and at the output of the switch 7 (the output of the sum 17) there are pulses, the number of which is equal to the sum of two numbers.

If we assume that counter 2 is decremented, and counter 3 is deductible, then the difference will be positive when counter 3 is first filled. If counter 2 is first filled, decreasing, then the difference of numbers in the parallel course is recorded in decreasing counter 2 and this corresponds to a negative difference .

If you compare your numbers to be equal, the overflow signals from the outputs of counters 2 and 3 are set on the same counting pulse. In this case, at the output of the element IS-NOT 12, a signal appears prohibiting the passage of pulses through the element 4.

Figure 2 shows the timing diagram of the device for the case when the first number is 3 and the second 2.

The application of the proposed device allows to simplify the operation of the device with the equality of two numbers, to expand its functionality due to the possibility of simultaneous determination of the sum and the difference by one device.

Claims (1)

Invention Formula A computing device containing a pulse generator, two elements And, two counters, 1W-trigger and counting trigger, the output of the pulse generator connected to nepsiM input of the first element And the installation inputs of the first and second counters connected to the write tires of the first and second number of the device, respectively, output the second element And is connected to the output of the difference of the device, differently from the fact that, in order to extend the functionality by simultaneously obtaining the sum and differences of two binary numbers, it contains the elements: YLI-NOT, AND-NONE, the switch, the first and second D-triggers, the D-inputs of which are connected to the device mode setting bus,. the sync input of the first D-flip-flop is connected to the output of the pulse generator, the av-output - with the second input of the first element I, the third input of which is connected to the output of the IEE element, and the output - with the countable input of the counting trigger and the first information input 4 of the switch, the second information input which is connected to the output of the counting trigger, the synchronous input of the second D-flip-flop, the counting inputs of the first and second counters and the first input of the second element and the second input of which is connected to the inverse output RS flip-flop and first control the input of the switch, the second control input of which is connected to the output of the second D-flip-flop, and the third control input of the switch is connected to the direct output of the RS-flip-flop, the S-input of which is connected to the input bus of the initial installation and the inputs of the initial installation of the second D-flip-flop, counting trigger, the first and second counters, the output of the first counter is connected to the first inputs of the elements AND-NOT and OR NOT, the output of the second counter is connected to the second inputs of the elements AND-NOT and OR NOT, the output of the element OR is NOT connected to to-input 4 NC trigger, the output of the second element And is connected to the output of the difference device, the switch output is connected to the output of the sum of the device. SOURCES of information taken into account in the examination 1, Copyright Certificate CCCf 408306, cl. G 06 F 7/385, 1973. 2, USSR Author's Certificate 434410, cl. G 06 F 7/385, 1974. JlJlJ JTJljriJlJlJTJ LJnJPLLJTJTJlJT f719 rLJlJTTLJTT m.2