JPS592101A - Misoperation preventing circuit - Google Patents

Abstract

PURPOSE:To prevent a misoperation without damaging operability, by providing a switch for executing an operation and a switch for releasing a misoperation, on a panel switch of an information processing device, etc. CONSTITUTION:When a switch 1 is operated, an output of a detecting circuit 2 becomes a waveform of the left end side of a signal line 21, an AND gate 6 becomes on, an FF5 is set by the trailing edge of its output 61, and its output 51 becomes a waveform of the left side of the output 51. In this case, an alarming circuit 10 informs this state, therefore, when the switch 1 is operated again, an AND gate 9 becomes on by the output (the second waveform of the signal line 21) of the detecting circuit 21 and the Q output 51 of the FF, and for the first time, the operation of the switch 1 becomes effective at this time point. On the other hand, and output 71 of an AND gate 7 also becomes on, the FF 5 is reset by the trailing edge of an output 81 of an OR gate 8 and it is returned to its initial state. In case when said alarm is raised due to an operator's misoperation, the second operation is inhibited because of calling his attention, and the misoperation is prevented. In this case, a switch 3 is operated and it is regarded as the switch operation has not been executed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an erroneous operation prevention circuit suitable for a panel switch of an information processing device or the like.

Conventionally, as a means to prevent panel switches from malfunctioning, (1) attaching a protective cover to the front of the switch (2)
A method has been adopted in which an enable switch is provided separately from the switch to enable the switch (3) Two switches are provided and the two switches are operated simultaneously to enable the switch.

However, all of these methods have drawbacks such as (1) poor operability, and (2) if an operator makes an erroneous operation, it is impossible to restore the state to the state before the operation even if the operator notices it immediately.

An object of the present invention is to provide an erroneous operation prevention circuit that solves the above drawbacks by adding a relatively simple circuit.

In order to achieve the above object, the erroneous operation prevention circuit according to the present invention includes a first switch, a first detection circuit that detects the operation of the fang 1 switch, a second switch, and a second switch.
A second detection circuit detects the operation of the switch of the fang 1, and when it is not set, it is set by the output trailing edge of the first detection circuit, and when it is set, it is set by the output trailing edge of the detection circuit of the fang 1 or the fang 1. a flip-flop that is reset by the output of the detection circuit of No. 2, an alarm circuit that issues an alarm while the flip-flop is set, and an AND circuit whose inputs are the output of the detection circuit of the fang 1 and the output of the flip-flop. The first switch operation causes the alarm circuit to output an alarm, and the second first switch operation causes the AND circuit to output a signal indicating that the first switch operation is valid. It is composed of:

According to the above configuration, since the same switch has to be operated twice in succession, the ease of operation can be improved, and even if a malfunction occurs, the alarm circuit will notify you, so it is easy to operate the second switch. can be restored to its original state, and the purpose of the present invention is fully achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of a malfunction prevention circuit according to the present invention.

A first switch 1 for operation and a second switch 3 for canceling a malfunction are provided. 1st, 2nd
A first detection circuit 2 and a second detection circuit 3 are connected to the switches, respectively, for detecting switch operations.

The output of the first detection circuit 2 is connected to one input terminal of the AND gate 6.7.9.

On the other hand, the output of the detection circuit 3 of the fang 2 is connected to the - input terminal of the OR gate 8. Furthermore, the output of the AND gate 6 is connected to the set terminal (S) of the flip-flop 50, and the Q terminal of the flip-flop 5 is connected to another input terminal of the output of the AND gate 6.

The AND gate 7 output is the OR gate 80 input, and the input of the OR gate 8 is also connected to the output of the second detection circuit 4 and the output of the first initial setting circuit 11, and one of these inputs is Otherwise, reset the 7 lip-flop 5.

The initial setting circuit 11 initializes one circuit when the power is turned on. Q output of flip-flop 5 is alarm circuit 1
0, and also serves as the other input of AND gate 9.

When the Q output 51 of the flip-flop 5 is on, the alarm circuit 10 issues an alarm using, for example, a buzzer, lamp, or audio output.

When the power is turned on, the flip-flop 5 is put into a reset state by the action of the initial setting circuit 11.

FIG. 2 is a waveform diagram of each part showing the case where this malfunction prevention circuit operates due to normal operation and the case where it malfunctions and is corrected.

The part indicated by A indicates normal operation, and the part indicated by 1B indicates correction of malfunction.

Assume that the first switch 1 is now operated.

The output 21 of the first detection circuit 2 is the second number #1l (21
) is the leftmost waveform.

The AND gate 6 is turned on, and the trailing edge of its output 61 sets the flip-flop 5, and its output 51 becomes the waveform on the left side of the output (51) in FIG.

At this time, the alarm circuit 10 notifies 1 of this state, so when the switch 1 of fang 1 is operated again, the output 21 of the detection circuit 2
(the second waveform of the second numbered line (21)) and the Q output 51 of the flip-flop turn on the AND gate 9 (the waveform of FIG. 2 (91)), and at this point the first
The operation of the switch becomes effective.

On the other hand, the output cuff 1 of the AND gate 7 is also turned on, and the flip-flop 5 is reset at the trailing edge of the output 81 of the OR gate 80 and returns to the initial state.

If the above-mentioned f-alarm is issued due to an operator's incorrect operation, a second operation will be inhibited because it will arouse negligence.
Misoperation is prevented.

In this case, operate the second switch meter as shown in Figure 2 (41).
) is output and the flip-flop 5 is reset, returning to the initial state and it is assumed that no switch operation has been performed.

As described in detail above, according to the present invention, by adding a relatively simple circuit, it is possible to provide an erroneous operation prevention circuit that can prevent erroneous operations without comparably impairing operability.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the erroneous operation prevention circuit according to the present invention, and FIG. 2 is a time chart of each signal line in the circuit of FIG. 1... First switch 2... First detection circuit 3.
...Second switch 4...Second detection circuit 5...
Solitub flop 6.7.9...And gate 8...Or gate 10...Alarm circuit 11...
・Initial setting circuit 21.41.51.52.61.71S8119】-1
111...Signal line

Claims (1)

[Claims] A first switch, a first detection circuit that detects the operation of the first switch, a second detection circuit that detects the operation of the second switch of the fang 2 switch, and a set of If not, it is set at the trailing edge of the detection circuit output,
a flip-flop that is reset by the trailing edge of the output of the first detection circuit or the output of the second detection circuit when set; an alarm circuit that issues an alarm while the flip-flop is set; It includes an AND circuit whose input is the output of the detection circuit of 1. An erroneous operation prevention circuit configured to output a signal indicating that switch operation No. 1 is valid.