JPS58203548A - Switching device - Google Patents

Abstract

PURPOSE:To prevent a switching board from malfunction, by suppressing an output from an operation switch for a fixed period after depressing the operation switch to forcedly prepare the time to check the effectiveness of the depressed switch. CONSTITUTION:Output signals from operation switches (SWs) 1-1-1-n, a cancell SW2 which cancels the registration of the depression of the operation SWs and an enable SW3 which makes the outputs of the operation SWs available are respectively applied to filter circuits 4-1-4-n, 42, 43 to convert these output signals into logical levels. If the SW1-1 is closed, a square wave SW signal (a) through the circuit 4-1 is inputted to a storage circuit 6-1 and a timer circuit 7-1. When the circuits 6-1, 7-1 are raised at the trailing edge of the signal (a), a signal (b) and a signal (c) having prescribed time width are outputted respectively and the signal (b) is interrupted by a gate 8-1 during the operation period of the signal (c). After completing the operation of the signal (c), the remaining component of the signal (b) closes the SW3 through the gate 8-1, and a signal (f) which is applied with AND gate 9-1 by signal (e) through a circuit 43 drives a driving circuit 11-1. At that time, a detecting circuit 10-1 detects the trailing edge of the sigal (f), resets the circuit 6-1 through the gate 5-1 and raises the signal (b).

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a switch device for preventing erroneous switch operations on a control panel of an information processing device or the like.

BACKGROUND ART Conventionally, as a method for preventing erroneous operation of an operation panel, there is a method of covering an operation switch with a cover to prevent accidental operation. This method allows each switch to be covered individually so that only the switches υ can be operated consciously, but the cover must be operated each time, and it is not aesthetically pleasing. Another method is to provide an auxiliary switch that enables or disables the operation of the operation switch, and outputs the logical product of the switch and the operation switch. Similar to the switch cover described above, this method aims to operate the auxiliary switch consciously, confirm that it is effective, and then operate the switch to accomplish the purpose. The effectiveness tends to decrease. In other words, if you press down the operation switch while holding down the auxiliary switch, the effect will be halved.

OBJECTS OF THE INVENTION The purpose of the present invention is to suppress the output for a certain period of time after pressing down the operation switch, and to forcefully provide a time to confirm the effectiveness of the pressed switch, thereby eliminating the drawbacks of the conventional method.
The aim is to provide reliable switch operation throughout.

SUMMARY OF THE INVENTION According to the present invention, a rectangular wave switch signal is generated from the operation switch means during the period of pressing, and a memory is set by the rectangular wave switch signal to indicate that the operation switch means has been operated! A timer circuit that responds to the trailing edge of the rectangular wave switch signal generates a rectangular wave timer signal with a constant time width, and the period of this rectangular wave timer signal is stored 1i. The signal is suppressed by the suppression circuit, and a second rectangular wave switch signal can be generated from the auxiliary switch means, and the remaining components of the storage signal after the suppression operation of the suppression circuit, the second rectangular wave switch signal, and the entire logic circuit are The configuration is such that the logical product output t- is outputted, and the trailing edge of this logical product output is detected by the entire detection circuit to set the memory circuit t-IJ''+. This device includes a reset signal generating means for generating a reset signal, and a drive circuit that uses an AND output as a control output.

Embodiments of the Invention Next rc1 An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing an embodiment of the switch device of the present invention. In this circuit configuration, the operation switches 1-1 to 1-n are operated normally and are the objects of operation,
There are three types of switches, including a cancel switch 2 that cancels the registration of pressing of these operation switches, and an enable switch 3 that enables the output of the operation switches, which are closed only during the period in which they are pressed. Each of the switches 11 generated from these switches is applied to filter circuits 4-1 to 4-n+ 42.43 for converting to a logic level. Each output terminal of the filters 4-1 to 4-n serves as an input to a memory circuit 6-1 to 6-o consisting of a bistable circuit such as a flip-flop that registers and stores the depression of the operation switch 1-1 to 1-n. It is connected to the terminal S and also to timer circuits 7-1 to 7-n for generating a signal for a certain period of time.

Memory circuits 6-, ~6-n and timer circuits 7-1~7-n
Each output terminal of the AND gates 8-1 to 8-
Connected to the input terminal of o. Gate s-1~8-o
and the output terminal of the filter circuit 43 are connected to the input terminals of the AND gates 9-1 to 9-n, so that respective AND outputs can be obtained. The output terminals of the AND gates 9-1 to 9-n are respectively connected to drive circuits 11-1 to 11-1 for outputting the switch signals as external control outputs.
11-0, and also connected to detection circuits 10-i to 10-n K for detecting the trailing edge of the switch signal. The output terminals of the detection circuits 10-1 to 10-0 are the OR gates 5-
It is used as one of the input terminals 1 to 5-n. The output terminal of the filter 42 is connected to the other input terminals of the OR gates 5-1 to s-n, and the logical sum output is the memory circuit 6-
, ~6-n are configured to be connected to the reset terminals R of 6-n.

The operation of the circuit arrangement shown in FIG. 1 will be explained with reference to the time chart 1) in FIG. 2. For example, when the operation switch 1-1k is closed, the filter circuit 4-1t-
Through this, the rectangular wave switch signal a is input to the memory circuit 11 and the timer circuit 7-1.

The trailing edge of No. 16a causes the memory circuit W&6-t to output a rising memory signal S. Further, the timer circuit 7- is triggered by the trailing edge of the signal a and outputs a rectangular wave timer signal C having a predetermined time width.

The gate s, which operates as a rectangular wave timer No. 1j C(f) MA suppression circuit, cuts off and suppresses the storage signal b'l. After completion of the signal C, the remaining component of the signal S is obtained as the output of the gate 8-1 and becomes the input of the AND gate 11.

When the enable switch 3 is closed in this state, a rectangular wave switch signal 4e is obtained via the filter 43.

AND gate 9-1 outputs the logical product of signals d and e, ft-
Drive circuit 11-. The output of the drive circuit 11 is given by the operation switch 11 and used as a control # signal. Also, at this time, the detection circuit 10-1 detects the trailing edge of the AND output signal f, and uses the detected output to
5-1 'fr to set the memory circuit 6-xk'). This causes the memory signal to fall. Furthermore, if you want to reset the memory circuit at any time during the process, 1. By pressing the cancel switch 42, a reset signal is taken out from the filter circuit 42 and the OR gate 45
It is only necessary to apply the signal to the memory circuit 6-1 and the paste terminal R through the terminal R. Below, other operation switches 1-2 to x-
It is easy to understand that the operation of n operates in the same way.As I have explained in detail about the invention, 1. If you use the switch circuit of the present invention, you will not have to press the enable switch after pressing down the switch you want to operate. This gives you time to check whether all the valves of the target switch have been lowered, and has the effect of eliminating mistakes in pressing the switch due to easy operation. Furthermore, even if the enable switch is handled incorrectly, that is, even if the enable switch is pressed down first and then the operation switch is pressed down, the switch signal will not be output for a predetermined period of time due to the function of the timer circuit. This gives you more time to check the details, and can greatly reduce erroneous operations on the control panel.

[Brief explanation of the drawing]

i@1 FIG. 1 is a block circuit diagram showing an embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the circuit shown in FIG. 1. 1-, ~l-o・Old・・Operation switch % 2・・Old・・Cancel switch, 3・・・・Enable full switch s 4-1～4−, . 42.43...Group/filter circuit, 5-, ~5-n...OR gate h 6-
1 to 6-, ... memory circuit, 7-1 to 7-n...
...Timer circuit, 8-1 to 8-n, 9-1 to 9-n
・・・・・・ Ant game-hlO-1~10-, ・dan・
mmow! . 1t-i-11-n...Drive circuit. Agent Patent Attorney Kuri 1) Yushi Haru!

Claims (1)

[Claims] Operation switch means 1-1 = 1-n, 4-1 to 4-, which generates a rectangular wave switch signal corresponding to the period during which it is pressed.
storage circuits 6-1 to 6- that are set by the rectangular wave switch signal and output until the storage signal tU is set and indicates that the operation switch means has been operated t-1;
n, and timer circuits 7-1 to 7-1 for generating a rectangular wave timer signal with a constant time width in response to the trailing edge of the rectangular wave switch signal.
7-n, suppression circuits 8-1 to 8-n that suppress the storage signal for a period of the square wave timer signal, and an auxiliary circuit that generates a second square wave switch signal corresponding to the period of pressing. Switch means 3.43 and the suppression circuits 8-1 to 8
-n residual components of the storage signal after the suppression operation and the second
Logic circuit 1 to obtain the eyelid product output with the square wave switch signal
1 to 9-n and the trailing edge of the AND output is detected and the memory circuits 6-1 to 6n-, t-! Detection circuits 10-1 to 10-n that take out reset signals set on J, and the memory circuit'
a reset signal generating means 2.42 that generates a second reset signal for arbitrarily resetting Nr 6-1 to 6-n; and a drive port 'N that uses the AND output as a control output.
A switch device comprising: r 11-s to 11-.