JPS62190533A - Interrupt mask control system - Google Patents

Abstract

PURPOSE:To facilitate correcting errors to reduce the correction cost and improve the reliability of a device by checking states of interrupt masks with a prescribed instruction or the like and generating a prescribed interrupt in case there is an interrupt mask which is set to suppress interrupt. CONSTITUTION:At the time of the instruction which terminates the execution of a program is executed in this executing program, an interrupt control part 2 receives the end report signal from a signal line 4. Then, the control part 2 checks an interrupt mask part 1 to discriminate whether there is the interrupt mask which is set to suppress an interrupt request (for example, turned off) or not. If the interrupt mask in the turn-off state is detected, an interrupt request to a specific interrupt level is generated internally and is reported to an execution control part 3. The control part 3 starts a program prepared for processing of error of failure in interrupt mask release. This program outputs information indicating the interrupt level or the like of the program, which does not release the interrupt mask, to a proper output device to report the existence of error.

Description

[Detailed Description of the Invention] [Summary] Control method for detecting interrupt mask release failure in an interrupt-driven information processing device with multiple interrupt levels, instructions for terminating program execution at a certain level, etc. The state of the interrupt mask is checked, and if any interrupts are inhibited, a predetermined interrupt is generated. By directly detecting omission of interrupt mask release by a program driven by this interrupt, errors in interrupt mask control can be detected at an early stage.

[Industrial application field]

The present invention relates to an interrupt mask control method for an information processing device,
In particular, the present invention relates to a method for detecting interrupt mask cancellation in an interrupt-driven information processing device having multiple interrupt levels.

2. Description of the Related Art A so-called interrupt-driven information processing device, which has multiple interrupt levels and configures all processing by processing provided corresponding to each interrupt level, can be seen in the configuration of, for example, a communication control processing device.

In such processing devices, a program at a certain level may need to prevent interrupts at a certain interrupt level from occurring during a certain process, and sets an interrupt mask for that level to prevent errors. If the process is terminated as it is, the process corresponding to that interrupt level will not be started after that, which may cause a serious failure, so it is desirable to detect such errors early and correct them. It will be done.

[Prior art and problems to be solved by the invention] FIG. 2 is a block diagram showing an example of the configuration of a processing device.

Interrupt request signals of each interrupt level generated by various interrupt factors are input to the interrupt control section 2 through the interrupt mask section l.

The interrupt mask unit 1 sets gates corresponding to each interrupt level to
Each interrupt request signal is passed or suppressed by controlling according to the state of an interrupt mask set by a signal from the execution control unit 3.

The interrupt control unit 2 selects the input interrupt request signal by predetermined priority control, and notifies the execution control unit 3 of the interrupt request information of the selected one interrupt level. The execution control unit 3 starts executing the program corresponding to the program.

The interrupt control unit 2 stores the selected interrupt level, and performs control so as not to select an interrupt request with an interrupt level lower in priority than that level while the program at the selected level is being executed.

Each program executed by the execution control unit 3 notifies the interrupt control unit 2 of the termination via the signal line 4 by executing an instruction to terminate program execution.

The interrupt control unit 2 receives the termination notification signal via the signal line 4.
Erases the memory of the interrupt level that is currently being executed, returns to a state that allows interrupts with a lower priority than that level, selects the interrupt level to be executed next, and sends it to the execution control unit 3. Notice.

Furthermore, when an interrupt request with a higher priority level than the interrupt level being executed occurs, the request is immediately selected and notified to the execution control unit 3. In this case, the execution control unit 3:
Interrupts the current process and starts executing a high-priority program.

In this way, when a certain program executed in the execution control unit 3 performs a process including referencing/updating a storage area shared with other programs, the corresponding process is executed for a certain period. Unless the state of the storage area is changed by the execution of other programs,
It is well known that contradictory processing results can occur.

Such a situation can occur, for example, when a program with a certain interrupt level performs processing related to a shared area with a program with a higher priority interrupt level, and the higher priority interrupt occurs. , this is the case when the program updates its shared area.

Therefore, in the case where there is a possibility as described above, an interrupt mask is set so as to suppress an interrupt request of a desired interrupt level before starting the corresponding process, such as accessing the common 81. The program is configured to execute an instruction to set an interrupt mask in part 1, and when related processing is completed, to execute an instruction to cancel the set mask.

In such a program, if the interrupt mask release process is missed due to a writing error, the corresponding interrupt level is placed in a state where interrupt requests are suppressed, and the corresponding process is not executed. It turns out.

As a result, an inconvenient situation occurs because the necessary processing is not carried out, and it is detected as some kind of abnormal condition, but it is necessary to search for the original cause from such indirectly constituted phenomena. is generally extremely difficult and requires a large amount of cost to eliminate errors.

[Means for solving problems]

FIG. 1 is a flowchart of the process of the present invention.

The figure shows the flow of processing in the interrupt control section 2 when the execution control section 3 of FIG. 2 executes a predetermined instruction to end program execution.

[Function] When the execution control unit 3 notifies execution of a predetermined command, the interrupt control unit 2 erases the memory of the interrupt level currently being executed in processing step 10, and returns from that level. Return to a state where lower priority interrupts are enabled.

In the next processing step ll, the interrupt mask section 1 is inspected,
Identify whether there is an interrupt mask set to suppress interrupt requests.

If there is no interrupt mask set, in processing step 13, the highest priority interrupt request is selected as in the prior art, and the execution control unit 3 is notified of the interrupt information.

If an interrupt mask set to the interrupt request inhibit state is detected in processing step 11, an interrupt request for a specific interrupt level is internally generated in processing step 12, and then processing step 13 is performed. Proceed to.

The interrupt mask canceling board can handle errors by activating an appropriate program in response to this specific interrupt level.

〔Example〕

Similarly to the above, when the program at each interrupt level finishes processing at that level and reaches a processing stage where switching to another level is possible, the program executes an instruction to end program execution and ends the processing.

Upon execution of the instruction to end program execution, the interrupt control unit 2 receives an end notification signal via the signal line 4.

At processing step 10, the interrupt control unit 2 erases the record tα of the interrupt level currently being executed, and returns to the state in which interrupts with a priority lower than that level are enabled, as in the conventional case.

However, information indicating the interrupt level being executed is separately stored as information for an interrupt that may be internally generated according to the present invention and will be described later.

In the next processing step 11, the interrupt mask section 1 is inspected,
The presence or absence of an interrupt mask that is set to suppress interrupt requests (for example, turned off) is determined.

If no interrupt mask is set to OFF, that is, if interrupt requests of all interrupt levels are allowed to pass, in processing step 13, as in the past, the highest request A priority interrupt request is selected and the execution control unit 3 is notified of the interrupt information.

If an interrupt mask in the OFF state is detected in processing step 11, an interrupt request for a specific interrupt level is internally generated in processing step 12, and then processing proceeds to processing step 13.

In this case, if the specific interrupt level is, for example, the interrupt level with the highest priority among all the levels, processing will start immediately after this.

When the above-mentioned internally generated interrupt request is selected and notified to the execution control unit 3 in the selection of processing step 13, the execution control unit 3 prepares the interrupt mask release board for error processing. Start the program.

This program notifies the user of the existence of an error by outputting information indicating, for example, the interrupt level of the program that did not cancel the interrupt mask, to an appropriate output device.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in an interrupt-driven information processing device, an error is directly detected in the interrupt mask release processing wave that suppresses an interrupt, so that the error can be corrected. This has significant industrial effects in that it facilitates modification, reduces modification costs, and improves the reliability of information processing equipment.

[Brief explanation of drawings]

FIG. 1 is a flowchart of processing according to the present invention, and FIG. 2 is a block diagram of an example configuration of an information processing apparatus. In the figure, 2 indicates an interrupt mask section, 2 indicates an interrupt control section, 3 indicates an execution control section, and 10 to 13 indicate processing steps.

Claims (1)

[Claims] It has a plurality of interrupt levels with different priorities and a program corresponding to each interrupt level, and among the interrupt levels at which an interrupt request has occurred, the interrupt level with the highest priority is selected. The information processing device is configured to execute the program at the interrupt level, and each interrupt level has an interrupt mask for controlling the occurrence of an interrupt. When the instruction to terminate is executed, if there is an interrupt level whose occurrence is suppressed by the interrupt mask, the interrupt is configured to generate an interrupt of a predetermined interrupt level. An interrupt mask control method characterized by: