JPH0290238A - High load testing system - Google Patents

Abstract

PURPOSE:To improve test accuracy without correcting a test program by automatically correcting influence due to a physical element inherent in a device. CONSTITUTION:The test program 2 has a function for automatically correcting a test condition based upon the comparing check of a competition state by receiving the competition state held in a device state holding part 12 of a device 1 to be tested. Thereby, the state of the device 1 being tested is read out by the program 2 and fed back to the test condition to automatically correct the state and the test condition appropriate for the device 1 is automatically formed to suppress the physical influence inherent in the device. Consequently, the test accuracy can be improved without changing the program 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-load verification method, and particularly to a verification method suitable for performing functional verification of a device in a high-load state.

[Conventional technology]

Conventionally, when a system is configured by connecting various devices that have been determined to be normal through individual product inspections, such as a processing device or multiple input/output devices, the functions of each device may not function properly. It is necessary to verify the operation of such a system under high loads. This operation verification under high load is performed by executing the verification program 3 on the verification target function 11 of the device under verification 1, as shown in FIG. This verification program 3 executes verification in a verification execution unit 32 according to predetermined verification conditions 31 (for example, startup time of I10 instruction and CPU instruction, data length, instruction type, etc.). For example, if the device is started with the I10 command,
CPU instructions are executed at certain time intervals. Then, the result evaluation section 33 performs evaluation based on the execution results.

The result evaluation unit 33 assumes that the verification execution unit 32 is functioning normally if the results are as expected.

Note that this type of device is disclosed in Japanese Patent Application Laid-Open No. 62-171047.
Publication No.

[Problem to be solved by the invention]

In the above conventional technology, if the result of executing a verification program is that it is working normally, it is assumed that it is working correctly, but it is difficult to guarantee that the state targeted for verification has occurred. There was a problem with verification accuracy. In addition, even if measurement equipment is added to improve verification accuracy and optimal verification conditions (for example, timing data) are set, when multiple devices are targeted, the verification conditions may vary slightly for each device. Because they are different, it is necessary to change the program for each device. For this reason, there was a problem in dealing with adaptive devices.

An object of the present invention is to provide a high-load verification method that solves these conventional problems and improves verification accuracy without changing the verification program.

[Means to solve the problem]

In order to achieve the above object, the high load verification method of the present invention
In a high-load verification system having a means for verifying a function to be verified of a device under verification, a means for holding an operating state of the device under test, a means for reading the operating state from a program, and a means for feeding the operating state back into verification conditions. The feature is that a correction means is provided.

[Effect]

In the present invention, a program for verifying operation under a high load state is greatly influenced by device-specific factors such as instruction execution time and logical time delay. Therefore, it is required to guarantee stable accuracy without being affected by factors specific to the device. Therefore, it is possible for the verification program to read the state of the device under test during verification and automatically modify the verification conditions by feedback (for example, change the time interval or data length). As a result, the verification program automatically creates verification conditions suitable for the device to be verified, suppresses physical effects specific to the device, and improves verification accuracy.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a functional configuration diagram of a high-load verification system showing an embodiment of the present invention.

In FIG. 1, 1 is a device to be verified, 2 is a verification program for performing operation verification in a high load state, 11 is a function to be verified of the device to be verified 1, which is the target of operation verification, and 12 is an operational status of the device. 21 is an initial setting section that sets the initial value of the verification conditions; 22 is the device state holding section that stores the operating state of the device (
23 is a verification execution unit that performs verification execution based on the automatically corrected verification conditions; 24 is a verification result that performs verification evaluation based on the verification execution results. This is the evaluation department.

Whereas the conventional verification program 3 only performed verification according to preset verification conditions (it was necessary to change the program depending on the device to be verified), the verification program 2 of this embodiment differs in that it has a function to automatically correct the verification conditions by comparing and checking the conflict status in response to the conflict status held in the device status holding unit 12 of the device under verification 1, thereby automatically correcting the high load state of the device. It was created in an effort to improve verification accuracy. The race condition mentioned here may be inside the processor, inside the channel, inside the I10, or the like. That is, in the case of internal processors (including some channels): (1) Shared memory in multi-CPU configuration, conflict due to communication command collision, (2) Buffer memory registration.

Cancellation of registration of address translation information, conflict with eviction,
■CPU in a specific area within memory or buffer memory,
Conflict between read and rewrite operations from channels, ■CPU,
This includes conflicts due to conflicts between CPU internal fault processing and normal processing. Also, in the case of internal channels: (1) Conflict between control signals when multiple I10s are operated under the same channel.

(2) Competition with the CPU in channel control memory, etc. Furthermore, in the case of internal I10, ■Conflict within the Ilo control unit shared by multiple systems or channels (asynchronous interrupts from devices during I10 data processing, etc.), ■Failure processing within I10. This may be a conflict in failure processing during I10 startup or T2O operation. These race conditions are simply referred to as "race conditions."

FIG. 2 is a diagram showing an example of the configuration of the device state holding section 12 in FIG. 1.

The device state holding unit 12 includes a gate 112 that receives a state output signal of each function of the device to be verified 1, and a register 111 that records and holds the signal that is the gate output. Gate 112 samples the status output signal from each function with the device under test busy signal. The register 111 is reset when the device under verification is started, and the register 111 is reset by the verification program 2.
The verification result evaluation unit 24 reads out the verification result.

FIG. 3 is a diagram showing an example of the verification target function 11 in FIG. 1. Here, 121 is a function A, 122 is a gate that outputs a status output signal (signal indicating a conflicting state of function A), 123 is a function B that uses function A after a certain period of time has elapsed,
124 indicates function C which immediately uses function A.

Further, function A is activated and used in common by functions B and C.

Originally, as described above, function C has a higher priority than function B, but when function B (123) and function C (124) are activated from the verification program 2.

Functions B and C commonly activate and use function A.

At this time, the gate 122 detects that the activation requests conflict, and outputs the conflict state as a status output signal.

FIG. 4 is a flowchart of the processing operation of the initial setting section 21 in FIG. 1. The initial setting operation will be explained below according to the flow shown in FIG.

The initial setting section 21 sets initial values for the verification condition comparison and correction section 22 . First, an initial value T (T indicates the activation interval of function B and function C in the verification execution unit 23) is set (step 401). Next is area T of memory (not shown). The lower limit value of T at which a race condition occurs is stored as a verification condition. An upper limit value of T at which a conflict condition occurs is stored as a verification condition in an area child of a memory (not shown). An area S of a memory (not shown) stores the device state after the verification has been executed. Each area T0. T and S are cleared (step 402). A value of +α is set in the area Ta at the time of initial setting (step 403).

Here, area T is an area for storing correction values of verification conditions, and a value of +α or -α is set therein.

FIG. 5 is a flowchart of the processing operation of the verification condition comparison and correction section 22 in FIG. Hereinafter, the verification condition comparison and correction process will be explained according to the flow shown in FIG.

The verification conditions are corrected by varying the value of T depending on the device state. The device status is determined by comparing and checking the contents of S (step 501) to see if a conflict condition has occurred. If no conflict has occurred, the correction value of area T is checked (step 502) and the direction of correction is determined. However, at the start of correction, correction is performed in an increasing direction until a conflict condition occurs. Whether or not a conflict has occurred at this time is determined by T
Determine whether o is determined (step 503
). However, if the value of T continues to increase, the verification conditions will deviate from the optimal state and no conflicts will occur. This state is confirmed by checking whether the value of area T0 has been determined (step 503), and if the competition condition is passed, the correction value is changed in the decreasing direction (step 504). Further, if the correction is continued in the decreasing direction, the verification conditions will deviate from the optimal state as in the case of increasing, but the correction values will become inconsistent (step 502), and the correction value will be changed again in the increasing direction (step 502). 505). The value of T is corrected by adding the correction value T4 to T after determining the correction value (step 511).

By checking the contents of the device status S (step 5o1),
If a race condition is occurring, check the correction value (step 506).
) L, T of the lower limit of T. Then, the upper limit value of T1, T1, is set. When a race condition occurs for the first time (step 507), the area T0 is set to store the value of T at that time (step 507).
Step 508). When a conflict condition occurs for the first time due to the correction in the decreasing direction (step 509), the value of T at that time is stored and set in the area child factory (step 510).

By performing this correction process, it is possible to always set the value of the verification condition T within the range of the optimal state where competition occurs. Also,
Although the values of areas T and T are not directly used in the processing flow shown, by keeping records, it is possible to have a learning function as the initial value when restarting the verification program. Become.

FIG. 6 is a flowchart of the processing operation of the verification execution unit 23 in FIG. 1. The verification execution process will be described below according to the flow shown in FIG.

Verification is performed by starting and operating functions B and C at specific time intervals T. First, 1 function A, B, and C are initialized by setting data that determines the operation of the device, and clearing the execution result storage area of 1 function B and C for setting commands (step 601). Next, function C is activated by executing a command for starting the operation of function C (step 602). Corrected nine T values between 2
A time interval is determined until function B is activated (step 603). Next, function B is activated by executing a command for starting the operation of function B (step 604). It is expected that the activation of function B will cause a conflict with the operation of function C. Then, it waits until there is a completion report obtained as a result of operating functions B and C (step 605).

FIG. 7 is a flowchart of the processing operation of the verification result evaluation section 24 in FIG. 1. The verification result evaluation process will be described below according to the flow shown in FIG.

The evaluation takes in the execution results of functions B and C (step 70
2) Comparison (step 703) is performed by checking whether the value matches the expected value. The result is displayed as an error only when it does not match the expected value (step 704). The device state at the time of verification execution is read from the device state holding section 12, stored in area S (step 701), and passed to the verification condition comparison and correction section 22.

〔Effect of the invention〕

As described above, according to one aspect of the present invention, it is possible to automatically correct the influence caused by physical factors specific to conventional devices, thereby improving verification accuracy.

Furthermore, automatic correction enables verification even for devices with different performance, and there is no need to modify the verification program, so maintainability and productivity of the program can be improved.

[Brief explanation of drawings]

FIG. 1 is a functional configuration block diagram of a high-load verification system showing an embodiment of the present invention, FIG. 2 is a diagram showing the device state holding unit in FIG. 1, and FIG. 3 is a block diagram showing an example of a verification target. , FIG. 4 is a processing flowchart of the initial setting section in FIG. 1, FIG. 5 is a processing operation flowchart of the verification condition comparison and correction section in FIG. 1, and FIG. 6 is a processing flowchart of the verification execution section in FIG. 1. FIG. 7 is a processing flowchart of the verification result evaluation section in FIG. 1, and FIG. 8 is a block diagram showing a conventional verification function configuration. 1: Verification device, 2: Verification program, 12: Device status holding unit, 21: Initial setting unit, 22: Verification condition comparison and correction unit, 23: Verification execution unit, 24: Verification result evaluation unit. Patent applicant: Hitachi, Ltd.

Claims (1)

[Claims] 1. In a high-load verification system having means for verifying a function to be verified of a device to be verified, a means for retaining the operating state of the device to be verified, a means for reading the operating state from a program, and a means for using the operating state as a verification condition. A high-load verification method characterized by providing a means for feedback correction.