JPH0381834A - Interruption control device - Google Patents

Abstract

PURPOSE:To make it possible to simultaneously output an interruption signal to plural necessary processor by providing the interruption control device with a means for selecting plural practical output destinations by external setting and a means for holding response states from the output destinations in each processor. CONSTITUTION:The processors 11 to 13 are connected to a common memory 3 through a common bus 2. The interruption control device 4 is also connected to the bus 2 and a register 42 to be an interrupted destination selecting means can be accessed from respective processors. When an input interruption signal to the device 4 is regarded as the counter-processor interruption signal of a processor 13, the signal distribution range of the device 4 is the interruption range of all other processors. When the processor 13 previously sets up a processor to be transmitted in the register 42 through the bus 2 and executes the counter-processor interruption output, an interruption signal is outputted to respective set processors by an interruption status register 41 for holding the response status of each processor at the time of capable of receiving the response status. Consequently, the interruption signal can be simultaneously outputted to plural necessary processors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for controlling external interrupt signals in a computer system, and particularly to an interrupt control device.

[Conventional technology]

Conventional interrupt control devices either notify one fixed processing destination for one input or notify a processing destination that can be set from the outside, and in the latter case, one
One interrupt is notified to only one processing destination.

[Problem to be solved by the invention]

The above-mentioned conventional interrupt control device has the disadvantage that, for example, in a multiprocessor system, it is not possible to simultaneously notify one interrupt signal to multiple processors, but it is necessary to notify the processors in turn, resulting in a time difference. There is.

[Means to solve the problem]

The interrupt control device of the present invention has an interrupt destination selection means that can be set from the outside, and a means for holding a response from the interrupt destination. When the target interrupt signal is input, first, the response state holding means accepts the response if responses have been returned from all output destinations, otherwise the input is held on hold until the response is returned.The input of a 0 interrupt signal. is accepted,
An interrupt signal is output to the processor set as the interrupt destination selection means, and the response state holding means is reset according to the output destination. When a response is returned from the output destination, the response status holding means is updated for the response source processor.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram of an embodiment of the present invention in which the present invention is implemented in a common interrupt control device for controlling inter-processor interrupt signals in a multiprocessor system.

This embodiment is a system in which a plurality of processors 11, 12, 13 are connected to a shared memory 3 via a shared bus 2, and an interrupt controller 4 is also connected to the shared bus to control the interrupt light of the components of the present invention. The register 42 corresponding to selection means can be accessed from each processor. The input interrupt signal to the device 4 is the processor-related interrupt output of the processor 13, and the signal distribution range of the device 4 is the interrupt input of all other processors. The processor 13 registers the processors to which communication is required in advance through the shared bus 2 in the register 42.
, and when outputting an interrupt to a processor is executed, the register 41 that holds the response state will output an interrupt signal to each set processor if acceptance is possible.

〔Effect of the invention〕

As described above, the present invention includes output destination selection means that allows one interrupt signal to be set from the outside, so that one interrupt signal can be simultaneously output to necessary processors. Also,
The same effect as the conventional output destination processor switching means can also be obtained by limiting the output destination to one.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram of an embodiment of the present invention. 11.12.13... Processor, 2... Shared bus, 3... Shared memory, 4... Interrupt control means, 41
... Interrupt status register, 42... Interrupt light selection register.

Claims (1)

[Claims] In a multiprocessor type computer system, means for distributing one interrupt signal to multiple processors and selecting multiple actual output destinations based on external settings;
An interrupt control device having means for holding a response state from an output destination for each target processor and suspending the next input signal until all responses are returned.