JPS63282855A - Multi-cpu controller - Google Patents

Abstract

PURPOSE:To improve the efficiency of debugging by using a part of a monitor CPU as address spaces of a mapping memory and a microinstruction memory. CONSTITUTION:An address space A1 for a monitor CPU program is an area storing a program for operating a CPU itself and an address space A2 for monitor CPU data is an area to the used as a buffer at the time of loading data from a host CPU 1. A mapping memory address space A3 and a microinstruction memory address space A4 are respective areas for the mapping memory 8 and the microinstruction memory 10 in a CPU emulation device 22. The monitor CPU 4 extracts data from the address space A2 and transfers the data of the necessary number of bytes to the address spaces A3, A4. Consequently, emulation can be easily executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to multi-CPtJ emulation control of a CPU emulation device used as a debugging device for software development.

``Prior Art'' Conventional emulation is an air simulator or similar emulator device that analyzes actual CPU instructions one by one on a host such as a workstation, and is provided for each target CPU.

[Problem to be solved by the invention] A software simulator (or similar emulation device) is required for each target CPU;
In addition to being extremely expensive, a new software simulator (or similar emulation device) must be created each time a new CPU is targeted, making it extremely difficult to respond in a short period of time. It is.

"Means for Solving Problems" In order to enable CPU emulation for various purposes by changing the data stored in the mapping memory and micro-instruction memory of the CPtJ emulation device, we have developed the water control 6TL device. A monitor CPU that controls the entire system, a memory that stores and covers programs and data for the monitor CPLI connected to the bus, and a bus that is connected to the monitor CPU bus and controls the connection between that bus and the mapping memory and micro-instruction memory. The connection circuit is connected to the bus of the monitor CPU and starts the CPU emulation device.
Bus connection that controls the stop and as a result controls the bus connection circuit by the acknowledge signal output from the micro-instruction memory ↓ Control circuit, connected to the bus of the monitor CPU and hosts the data stored in the mapping memory and micro-instruction memory The address space of the mapping memory and micro-instruction memory uses part of the address space of the monitor CPU.

"Example" Next, the present invention will be explained in detail with reference to FIG. 1 and subsequent figures.

FIG. 1 shows a configuration diagram of the multi-CPU control device 21, and also shows the relationship between the multi-CPU control device 21, the CPU emulation device 22, and the host CPU 1.

FIG. 2 shows an example of address space allocation required when controlling a multi-CPU controller.

In FIG. 1, data to be stored in a mapping memory 8 and a micro-instruction memory 10 are loaded into a memory 3 by a host CPU 1 via a host interface 2 under the control of a monitor CPU 4. The address space for loading is the monitor CPU shown in Figure 2.
Required for data address space A2.

In FIG. 2, a monitor CPtJ program address space A1 is an area for storing a program for the monitor CPU itself to operate, a monitor CPU data address space A2 is an area used as a buffer when loading from the host i to CPU1, The mapping memory address space A3 and the micro-instruction memory address space A4 are areas for the mapping memory 8 and micro-instruction memory 10, respectively, of the CPtJ emulation device 22.

The monitor CPU 4 shown in FIG. 1 outputs a stop signal to the sequencer 9 of the CPU emulation device 22 via the bus connection control circuit 7.

When the CPU emulation device 22 stops, the micro-instruction memory 10 outputs an acknowledge signal E (stop), and when this signal is input to the bus connection circuits 5 and 6, the three buses of the monitor CPU 4, B, and
C (A is used as an address bus, B is used as a data bus, and C is used as a control bus), mapping memory 8, and microinstruction memory 10 are connected.

When the monitor CPU 4 recognizes the acknowledge signal E (stop) via the bus connection control circuit 7, the monitor CPU 4
extracts data from address space A2 for monitor CPU data in Figure 2 and transfers it to address space A3 for mapping memory.
and transfer the required number of bytes of data to the micro instruction memory address space A4.

After the data transfer is completed, the monitor CPU 4 outputs a star I signal to the sequencer 9 of the CPU emulation device 22 via the bus connection control circuit 7. C.P.
When the U emulation device 22 starts operating, an acknowledge signal E (start) is output from the micro instruction memory 10, and this signal is sent to the bus connection circuit 5.
and 6, the three buses (address bus A, data bus B, and control bus C) of the monitor CPU 4, the mapping memory 8, and the microinstruction memory 10 are separated, and the CPU emulation device 22 becomes independent. The monitor CPU 4 recognizes the acknowledge signal E (start) via the bus connection control circuit 7, and the series of operations ends.

Multi-CPU emulation control becomes possible by changing the data loaded from the host CPU 1 to data for various target CPUs to be emulated and repeating the above operations.

"Effects of the Invention" According to the present invention, it becomes possible to easily emulate various target CPUs (commercially available CPUs, custom CPUs, etc.) using a 1g CPU emulation device.

In other words, for a new target CPU, just create generation data and load it from the host CPU, and if multiple people are emulating different CPUs, each generation data can be downloaded from the host CPU. You can respond to any situation immediately by simply loading it each time.

Therefore, the cost of emulation tools is greatly reduced and debugging efficiency is dramatically improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multi-CPU control device, and FIG. 2 is a diagram showing an example of address space allocation. In the figure, 1 is a host CPU, 2 is a host interface, 3 is a memory 4 is a monitor CPU, 5.6 is a bus connection circuit 7 is a bus connection control circuit 8 is a mapping memory 9 is a sequencer □) 10 is a micro instruction memory 22
In the CPU emulation devices A, B, and C, buses A1, A2, A3, and A4 are address spaces. Patent applicant: Takatake Manufacturing Co., Ltd. sZ diagram

Claims (1)

[Claims] A monitor CPU that controls the entire control device,
A memory that stores programs and data for the monitor CPU that is connected to the bus, a bus connection circuit that is connected to the bus of the monitor CPU, and that controls the connection between that bus and the mapping memory and micro-instruction memory; A bus connection control circuit that controls the start and stop of the connected CPU emulation device and, as a result, controls the bus connection circuit by an acknowledge signal output from the micro instruction memory. The present invention is characterized in that it includes a host interface for loading data to be stored in the instruction memory from the host CPU, and that the address space of the mapping memory and the micro-instruction memory uses a part of the address space of the monitor CPU. Multi-CPU control device.