JPH0697435B2 - Variation chip - Google Patents

Description

The present invention relates to an variation chip, and more particularly to an variation chip capable of emulating a product group including different peripheral functions.

[Conventional technology]

2. Description of the Related Art In recent years, as the range of applications of microcomputers (hereinafter referred to as “microcomputers”) has expanded, the development of microcomputers suitable for various application fields has been carried out.

Generally, a microcomputer is composed of a central processing unit (CPU) that controls its basic operation and peripheral circuits that execute specific functions. The optimum application field of the microcomputer is determined by the functions and types that the peripheral circuits incorporate. In many cases.

Therefore, we are developing the optimum microcomputer by incorporating the peripheral circuit corresponding to the application field using the same CPU.

Evolution chip (hereinafter referred to as "evaluation chip")
Is a chip developed for emulating the user system and debugging the user program. It has a function to emulate the operation of an actual microcomputer chip (hereinafter referred to as "target chip") by outputting internal information to the outside of the evaluation chip while executing the program under development.

Generally, when developing a product of a single-chip microcomputer, the CPU that controls the execution of the user program is common, and the product is developed by changing its built-in peripheral functions.

Therefore, originally, an evaluation chip should be developed for each product, but development costs and man-hours increase, so it is not actually developed for each product, and the same CPU and CPU as the target chip are used. By developing an evaluation chip that contains only the functions required for emulation, an integrated circuit that contains only each peripheral function (hereinafter referred to as "peripheral chip") separately, and newly developing only the peripheral chip according to each product. This chip is emulated by combining an evaluation chip and a peripheral chip.

As an evaluation chip developed according to the emulation method as described above, there is the μPD78209 manufactured by NEC.

The configuration and operation of the evaluation chip will be described below with reference to FIG.

FIG. 5 is a configuration diagram of emulation using the μPD78209, and the evaluation chip 11 is an evaluation chip having the same CPU as this chip and a function necessary for emulation.

The peripheral chips 3 and 4 are integrated circuits incorporating peripheral functions corresponding to the respective products, and the evaluation chip 1 is accessed via the peripheral control signals 5 and 6 and the emulation bus 5.

The program memory 2 is a memory for storing a program under development, and the evaluation chip 1 makes access through the program address bus 7 and the program data bus 8.

The evaluation chip 1 accesses the peripheral chip 3 by the emulation bus 5 and the peripheral control signal 6 when accessing the peripheral chip 3 in accordance with the instruction etched from the program memory 2.

As described above, the target chip is emulated by the evaluation chip 1 that emulates the CPU function and the peripheral chips 3 and 4 that emulate the peripheral functions.

[Problems to be Solved by the Invention]

As described above, in the evaluation chip that emulates only the CPU function without embedding the peripheral function, the evaluation chip and the peripheral chip with the peripheral function are combined to emulate the target chip, so a peripheral chip is developed for each product. However, since a new peripheral chip must be developed each time a new product is developed, there is a drawback that the development cost and the man-hours for development increase.

[Means for Solving the Problems]

The configuration of the variation chip of the present invention is such that, in an emulation chip having a central processing unit and an emulation control circuit for controlling emulation operation, one or more peripheral circuits, a mode register for designating the operation of the emulation chip, A peripheral control signal generating means for switching the operation state of the peripheral circuit according to the data of the mode register is provided, and an external terminal for outputting the peripheral control signal to the outside of the variation chip and a peripheral for accessing the peripheral circuit. It is characterized in that it has a bus signal generating means and an external terminal for inputting and outputting a peripheral bus signal to the outside of the variation chip, and the central processing unit also accesses the outside of the variation chip.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a first embodiment of an evaluation chip according to the present invention.

FIG. 1 shows an emulation control circuit 20 including a CPU 10 and a mode register 21, peripheral circuits 30 and 31 mapped to specific areas of an address space, and buffers 40 and 41.
, Internal bus 50, peripheral bus 51, peripheral control signals 60, 61
It is composed of.

The mode register 21 is a register for designating the operation of the evaluation chip, and is composed of a plurality of bits.

The peripheral selection signals 60 and 61 are signals for selecting the peripheral circuits 30 and 31, respectively, according to the setting of the mode register 21.

FIG. 2 shows the configuration of the mode register 21 and the peripheral selection signals 60,6.
It is a relationship diagram with 1.

When the first bit of the mode register is set to "1",
The peripheral selection signal 60 is set to "1" and the peripheral circuit 30 is selected.

Conversely, when the first bit of the mode register is reset to "0", the peripheral selection signal 60 becomes "0" and the peripheral circuit 30 is not selected.

Similarly, when the second bit of the mode register is set, the peripheral selection signal 61 becomes "1" and the peripheral circuit 31 is selected.

When the second bit of the mode register is reset to "0", the peripheral selection signal 61 becomes "0" and the peripheral circuit 31 is not selected.

Generally, when multiple products can be emulated with a single evaluation chip, the memory capacity and operation mode are set according to the target product before emulation of the user program (hereinafter referred to as "emulation mode setting"). However, the mode register 21 is set when the emulation mode is set.

Next, the operation of the first embodiment of the evaluation chip according to the present invention will be described with reference to FIG.

A case where the peripheral circuit 30 has a built-in peripheral circuit 31 but the peripheral circuit 31 does not have a built-in peripheral circuit will be described.

Immediately after the power supply voltage is supplied to the evaluation chip 1, both the first and second bits of the mode register are set to "0" and the peripheral circuits 30 and 31 are not selected. Therefore, when the emulation mode is set, the mode register 21 is set such that the first bit of the mode register is "1" and the second bit of the mode register is "0". At this time, the peripheral selection signal 60 becomes "1", the peripheral selection signal 61 becomes "0", the peripheral circuit 30 is selected, and the peripheral circuit 31 is not selected.

In this way, the peripheral circuit 30 is built in, but the peripheral circuit 31
Can be set to emulate non-embedded products.

Similarly, if the mode register 21 is set so that the first bit of the mode flag is "0" and the second bit is "1", the peripheral circuit 30 is not built-in but the peripheral circuit 31 is built-in. If the mode register 21 is set so that the first bit of the mode flag is set to "1" and the second bit is set to "1", the peripheral circuit 30 and peripheral circuit 31 You can make settings to emulate the products that are built in.

As described above, since the target chip can be emulated with only a single chip, there is no need to develop a peripheral chip, so development costs and man-hours can be reduced, and the emulation device This has the effect of reducing the mounting area of the emulation chip.

In the first embodiment, an example in which two peripheral circuits are incorporated has been described. However, when one peripheral circuit is incorporated and two or more peripheral circuits are provided by increasing the number of bits forming the mode register. It can also be applied to the case of incorporating internal organs.

FIG. 3 shows an emulation configuration example of a target chip using the second embodiment of the evaluation chip according to the present invention.
The program memory 2, the program address bus 7, the program data bus 8 and the emulation bus 5 are the fifth
This is similar to the conventional example shown in the figure.

The peripheral chip 80 is an integrated circuit having a function different from that of the peripheral circuits 30 and 31, and the evaluation chip 1 can be accessed through the emulation bus 5.

FIG. 4 is a block diagram of a second embodiment of the evaluation chip according to the present invention, which includes a CPU 10 and an emulation control circuit 20.
, Mode register 21, peripheral circuits 30, 31, and buffer 4
0, 41, internal bus 50, peripheral bus 51, peripheral selection signal 6
0 and 61 are the same as in the first embodiment. FIG. 4 shows a configuration in which external terminals 70, 71, 72 are added to FIG.

The external terminal 70 is a terminal for outputting the peripheral selection signal 60 to the outside, and is externally connected to the peripheral control signal 90. External terminal
Reference numeral 71 denotes a terminal for outputting the peripheral selection signal 61 to the outside, which is externally connected to the peripheral control signal 91. External terminal 72 is a peripheral bus
This is a terminal for inputting and outputting 51 to the outside, and is externally connected to the emulation bus 5.

Next, the operation of the second embodiment of the evaluation chip according to the present invention will be described.

A peripheral function in which the peripheral circuit 30 and the peripheral chip 80 are built-in is built-in, but the peripheral circuit 31 is not built-in. A case will be described with reference to FIGS. 3 and 4.

The peripheral chip 80 is mapped in the same address space as the peripheral circuit 31, and when the peripheral control signal 90 is "1", the peripheral control signal 90
Selected when 91 is “0”.

First, the first bit of the mode register is set to "1" and the second bit is set to "0" by the instruction of the CPU. Since the first bit of the mode register is "1", both the peripheral selection signal 60 and the peripheral control signal 90 become "1", and the peripheral circuit 30
Is selected. Since the second bit of the mode register is "0", the peripheral selection signal 61 and the peripheral control signal 91 are "0", and the peripheral circuit 31 and the peripheral chip 8 are instructed by the CPU.
When the address to which 0 is mapped is accessed, peripheral circuit 3
1 is not selected and the peripheral chip 80 is selected.

That is, when the instruction fetched from the program memory 2 is an access instruction to the address to which the peripheral circuit 31 and the peripheral chip 80 are mapped, the CPU 10 accesses the peripheral chip 80 via the peripheral bus 51 and the emulation bus 5.

In the example described above, the peripheral circuit 30 and the peripheral chip 80 have a built-in peripheral function, but the peripheral circuit 31 does not.
If the first bit of the mode register is set to "1" and the second bit of the mode register is set to "1", the peripheral circuits 30, 31 and the peripheral circuit 30,
It is possible to emulate a product that incorporates the peripheral chip function mapped to an address different from 31.

As described above, by outputting the peripheral selection signal and the peripheral bus from the evaluation chip 1 to the outside of the evaluation chip, the emulation of the product that includes the peripheral functions that are not included in the evaluation chip is developed, and only the peripheral chip that is not included in the evaluation chip is developed. It is possible to minimize the development cost and man-hours since it can be performed only by doing the work.

Further, since it is possible to easily emulate a peripheral function in the evaluation chip that is mapped to the same address as the peripheral function in the evaluation chip and a peripheral function different from the peripheral function, there is an advantage that the mapped address can be effectively used. is there.

〔The invention's effect〕

As described above, in the evaluation chip according to the present invention, in addition to the CPU function, the peripheral circuits are built in, and various peripheral functions are built in by selecting only the peripheral circuits necessary for emulation of the target chip by the peripheral selection signal. Since a single evaluation chip can be used to emulate the above product, it is not necessary to newly develop a corresponding peripheral chip, and it is possible to reduce the development cost and man-hours of the emulation tool for the target chip.

Further, by configuring the peripheral chip to output the peripheral selection signal and the peripheral bus to the outside, even if the peripheral function that the evaluation chip does not have is built in, only the chip that has the missing peripheral function is newly developed. Since the target chip can be emulated by itself, there is an effect that the development cost and the development man-hours of the target chip emulation chip can be reduced to the minimum. Further, since the target chip can be emulated by using the peripheral chip mapped to the same address as the peripheral circuit in which the evaluation chip is incorporated, the mapping address can be effectively used.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an variation chip of a first embodiment of the present invention, FIG. 2 is a correspondence diagram of mode flags and peripheral selection signals, and FIG. 3 is a second diagram of the present invention. A diagram of a configuration example of emulation using the variation chip of the embodiment of
FIG. 4 is a block diagram of the variation chip of the second embodiment of the present invention, and FIG. 5 is a diagram of a conventional emulation configuration example. 1 ... EVA chip, 2 ... Program memory, 3, 4 ...
Peripheral chip, 5 ... Emulation bus, 6 ... Peripheral control signal, 7 ... Program address bus, 8 ... Program data bus, 10 ... CPU, 20 ... Emulation control circuit, 21 ... Mode register, 30, 31 …… Peripheral circuit, 40,41 …… Buffer, 50 …… Internal bus, 51 …… Peripheral bus, 60,61 …… Peripheral selection signal, 70,71,72 …… External terminal, 80 …… Peripheral chip, 90,91 …… Peripheral control signals.

Claims (1)

[Claims] 1. A central processing unit, an emulation control circuit for controlling an emulation operation, and an emulation chip containing one or more peripheral circuits. A mode register for designating the configuration of the peripheral circuit at the time of the emulation operation, and this mode register. Means for supplying the peripheral control signal to the peripheral circuit, or the peripheral control signal is connected to the peripheral circuit and the outside of the variation chip. And a peripheral bus signal generating means for accessing the peripheral circuit, and an external terminal for inputting and outputting the peripheral bus signal to the outside of the variation chip. Has access to the outside of the variation chip. Et Variations chip that.