JPS63291135A - Microcomputer developing device - Google Patents

Abstract

PURPOSE:To eliminate an external bus I/F/port emulator which is needed conventionally by being equipped with a program memory I/F and an external instruction code bus in an EVA chip. CONSTITUTION:The device has a processor for evaluation which does not have a built-in program memory, a first memory to store a first program, a second memory to store a second program and a tracer debugging circuit 300. A processor for evaluation independently has a first port 130 connected with the first memory and a first bus, and a second port 140 connected by using the second memory and a second bus, and a tracer debugging circuit 300 is connected to the first bus. The processor for evaluation has a function to output the second program inputted from the second memory through the second bus to the second port 140 through the first port 130 to the first bus and writes the second program into the tracer debugging circuit 300. Thus, a hardware can be curtailed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a microcomputer development device used to develop programs for a one-chip microcomputer (hereinafter referred to as a "microcomputer") having a built-in program memory. .

[Conventional technology]

Generally, a microcontroller has a built-in program memory 1 and a central processing unit (CPU) including a data memory, as shown in Figure 9.
It includes a CPU (hereinafter referred to as ``CPU'') 2, a peripheral circuit 4, and a terminal (hereinafter referred to as 1 external I/F/port 1) 3 that serves as both an external bus interface and a general-purpose port. CPU 2 according to instructions stored in built-in program memory 1
performs arithmetic processing and controls peripheral circuits. The microcontroller executes only the instructions in the built-in program memory, and the external memory 6 and external circuit 5 allocated outside the microcontroller are
If the operation of writing data or reading data (hereinafter referred to as 1 access 1) is not executed,
External bus I/F/port 3 is used for controlling external circuit 5 as a general-purpose port. However, if the microcontroller accesses the external memory 6 or external circuit 6 to read instructions and executes instructions from the outside instead of the built-in program memory IJIK, or accesses data, it must output addresses and input data to the external memory. External bus I/F/port 3 is used as an external memory access port for output. Therefore, the external bus I/F/port 3 must be able to be used by switching between an external memory access port and a general-purpose port depending on the purpose of use. It has a circuit configuration.

In order to use the microcomputer, the user must develop a program to control the CPU 2 and store it separately in the built-in program memory and external memory as necessary. Generally, a microcomputer development device is used to develop a program. FIG. 1θ shows a configuration diagram of a conventional microcomputer development device. The conventional Evachip (evaluation processor) 100 has the same circuit functions as a microcontroller except for the built-in program memory, and also has an external path I/F port and a control circuit for a program development device on one chip. . Program memory emulator 20
0 is an external memory used in place of the built-in program memory of the microcomputer, and is provided in. As mentioned above, the Evachip 100 does not have a built-in program memory, but it has almost the same functions as a microcontroller, so it is designed by directly using the design of the microcontroller. External bus I/F with the same function as the bus I/F of
/ port is provided. The evaluation chip 100 outputs the address to the address bus 1300 via the external bus I/F/port, and further outputs the control number W to the control bus 1500 to access the program memory emulator 200, and the command read out to the data bus 1400. Input the code via the external bus I/F/port. Therefore, since the external memory IJ I/F/port function cannot be realized, the external bus I/F/port emulator 1200 must be connected to the outside of the evaluation chip 100. The external bus I/F/port emulator 1200 configured externally is configured with an IC such as TTL, a gate array, and the like. The Evachip 100 is an external bus I/
The external bus I/F/port emulator 200 is accessed via the F port.

Tracer/debug circuit 300 is connected to address bus 1300
, data bus 1400. It is connected to the control bus 1500 and stores the addresses and instruction codes of instructions executed by the Evachip, as well as addresses, data, and control signals to be accessed, and the information is used for operation analysis of the Evachip (hereinafter referred to as 1 trace function 1). Ru. In addition, malfunctions in the program can be detected by rewriting the contents of the program memory emulator 200, by detecting that a predetermined address has been accessed using stored addresses and data, and by reading the contents of registers inside the evaluation chip. It also has a function (hereinafter referred to as 1 debug function 1) to develop a normal program by removing the debug function. Therefore, in the microcomputer development equipment, the evaluation chip 100 inputs instruction codes from external memory via the program memory emulator 200 and external bus I/F 7-port emulator 1200, executes arithmetic processing, and outputs the execution results to the tracer/debugger. It is analyzed by circuit 300, modified as necessary, and used to develop a complete program.

[Problems to be Solved by the Invention] However, the above-described conventional microcomputer development apparatus using the Eva chip has the following drawbacks.

First, an external bus I connected to the outside of the Eva chip 100
The /F, /I' port emitter 1200 has a complicated structure and has the disadvantage that it is not possible to economically and compactly construct the microcomputer development apparatus. Moreover, external bus I/
F,/port emulator 1200 is Evachip 10
Devices different from 0 (TTL IC, gate array, etc.)
Because the microcontroller is made up of Therefore, when interfacing with an application circuit prepared by a user connected to a program development device, the microcontroller development device can access the application circuit normally, but when the microcontroller executes the developed program, the application circuit cannot be accessed normally. This may cause inconvenience.

Second, in order to shorten the microcontroller's processing time, it is necessary to execute instruction code input and CPU arithmetic processing, including data access, in parallel. Because the same external bus I/F port is used to access both, it is not possible to execute both in parallel, and the same operation as that of a high-speed microcontroller with a short processing time is evaluated (hereinafter referred to as "emulating"). There was a drawback that it could not be done.

[Means for solving problems]

The present invention develops and evaluates the first and second programs of a microcomputer that executes a first program stored in a built-in program memory and a second program stored in an external memory attached to the outside. In a microcomputer development device used for
The evaluation processor has a first memory that stores the first program, a second memory that stores the second program, and a tracer/debug circuit, and the evaluation processor has a first memory that stores the first program, a second memory that stores the second program, and a tracer/debug circuit. The tracer/debug circuit independently has a first port connected to the second memory using a bus, and a second port connected to the second memory using a second bus. bus, and the evaluation processor transfers the second program input from the second memory to the second port via the second bus to the second port via the first port. The second program output to the first bus is written to the tracer/debug circuit.

〔Example〕

Next, a first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a microcomputer development apparatus using an EVA chip embodying the present invention. In the Eva chip 100, only the external memory 400 is directly connected to the external bus I/F port. The program memory I/F port includes a program memory emulator 200 and a tracer/
A debug circuit 300 is connected. Further, an internal address bus and a data bus are connected to the internal bus output port, and the tracer/debug circuit 300 is coupled thereto.

Program memory emulator 200 outputs signal 136
When is 101, the instruction code is output to the fetch data bus 900.

FIG. 2 is an internal configuration diagram of the Eva chip 100.

CPUll0. Peripheral circuit 150. The external bus I/F port 140, internal address bus, and data bus 160 operate in the same manner as shown in FIG. 9, so a description thereof will be omitted. Program counter (PC) 120 +-17' Generates the address of an instruction to be read from the program memory, and the value of the address is updated every time one instruction code is read. The contents of the program counter 120 are the program memory I/F
The signal is input to the port 130 and the external bus I/F port 140, and is output from the fetch address bus and the external address bus. The external instruction code inputted from the external memory 400 is inputted to the external path I/F port 140 and then inputted to the program memory I/F port 130 via the external instruction code bus 1100. Program memory I/F port 130 sends its instruction code to CPU 10 via an internal bus and also to tracer/debug circuit 300 via 7-etch data bus 900. On the other hand, the instruction code read from the internal program memory emulator in response to the fetch control signal 136 is sent to the tracer 7127 circuit via the fetch data bus 900 and the program memory I
/F port 130 and is sent to the CPU via the instruction bus.
110. CPUll0 executes these instructions and sends the results from the internal bus output port to the tracer 7127 circuit 300 via the address/data bus 1300.
Enter.

FIG. 3 shows a detailed diagram of the program memory I/F board 130, and the operation of the EV chip lOO in response to command input will be explained using the timing diagram of FIG. In FIG. 3, the output of program counter 120 is input to external address discrimination circuit 134 and simultaneously output to fetch address bus 800 as is. External address discrimination circuit 1
34 determines that the address of the program counter 120 is in an external program memory space other than the built-in program memory space, and sets the output signal 135 to 11'. Further, when the output signal 135 is 101, an output signal 136 is outputted via the fetch signal generation circuit 131, and the program memory emulator is controlled to an output enabled state. Further, the output signal 135 is input to an external bus I/F (baud) 140, and controls input of instruction codes from an external program memory. The fetch data bus is composed of 8 bits and all have the same configuration, so the configuration is shown with 1 bit (K). When output signal 135 is 1, output buffer 1
33 becomes conductive, the external instruction code is output to the fetch data bus, and is also input to CPUll0 as an instruction code via the input buffer 132. The 7-step signal generation circuit 131 generates a fetch control signal i oo indicating the instruction read state from the control signal output from the CPU 110.
Create o.

In FIG. 4, at timings TI and T2, addresses AI and A2 of the built-in program memory space are output to the fetch address bus 800. At this time, the output signal 135
and 136 is 101. The program memory emulator 200 outputs the corresponding instruction codes OPI and OP2 to the 7-etch data bus 900. The read instruction codes OPI and OP2 are input to CPUll0 via the instruction bus and executed. T3. At timing T4, the output signal 135 and the fetch control signal 136 become 111, so the instruction code OP3. OP4 is read out to the external instruction code bus, outputted to the fetch data bus 900 via the output buffer 133, and the instruction code OP3. OP4 is input via the input buffer 132 and is input to CPUll0 via the instruction bus. Note that when the output signal 136 is gla, the program memory emulator 200 is in a state in which it does not output anything to the fetch data bus 900 (high impedance state).

Also, regarding reading the instruction code, the internal address bus
Since the data bus 160 is independent, processing by the CPU 110 can be executed independently. Fetch address bus 800.
Fetch data hash 900. Output signal 136 and fetch control signal ioo.

is input to the tracer 7127 circuit 300,
A normal program can be developed by analyzing the state of reading instruction codes from the program memory emulator 200 and external program memory using the tracer 7127 circuit 300. Further, the internal address bus and data bus 1100 are also input to the tracer 7127 circuit 300, and the execution state of the instructions of the CPU 110 can be checked.

Note that the external address discrimination circuit 134. The fetch signal generation circuit 131 is also necessary in the conventional example. Therefore, the hardware required for the present invention includes the fetch address bus 800. External instruction code bus, fetch data bus 9
00, the output buffer 133, and the input buffer 132. However, the fetch address bus 800 is the output of the program counter 120 as it is, and the external instruction code bus is also a signal of the instruction code itself read from the external program memory. Therefore, the present invention can be realized with only a small amount of hardware based on the hardware of a microcomputer.

A second embodiment of the present invention is shown and explained in FIG.

The difference from the first embodiment shown in FIG. 2 is that a MOD terminal is added to the program memo IJI/F port 130. In a microcomputer development device, an external program memory should originally be prepared by a user who creates a program and connected to the outside of the program development device. However, microcomputer development equipment may have a convenient function (hereinafter referred to as 1. External Alternative Memory Function) that allows program designers to prepare a certain amount of memory for use.This external alternative memory function A MOD terminal is provided to realize this.

FIG. 6 is a configuration diagram of the program memory emulator 200. The fetch address bus 800 and the fetch data bus 900 are connected to the built-in program memory emulator 201.
and an external alternative program 203. Also,
Output signal 136 is from built-in program memory emulator 2
02, and Nando Game) 201. When the fetch address bus 800 is input to the address discrimination circuit 204 and an address is set in a space allocated to a predetermined external alternative program memory in the external program memory space, the MOD signal is set to 11#. When the output signal 136 and the M (JD times signal) both become 1, the Nant gate 201 outputs an external alternative (the program counter 120 is set in the external memory address space and the space allocated to the external alternative program memory). An operation is performed to read the instruction code from the program memory 203 onto the 7-etch data bus.

FIG. 7 is a configuration diagram of the program memo IJI/F 130. The difference from FIG. 3 is that the output of the MOD terminal is input to the AND gate 137 via the inverter 139, and the output signal 135 of the external address discrimination circuit 134 becomes the other input of the AND gate 137.
The output of is input to the output buffer 133. Program counter 1 when MOD terminal is 10”
If the contents of 20 are in the external memory space, the AND gate lj
It becomes 136% 1. However, M
When the OD terminal becomes "L", the output of the AND gate 137 becomes "@0" and the multi-output buffer 133 is cut off.

FIG. 8 is a timing diagram of the second embodiment of the present invention. Timing l'l, T2. T3. At T4, the MOD signal is 0" and the explanation is omitted since it is the same as in FIG. Since the OD store name is ``1'', the instruction read operation has the same timing as the instruction read from external memory, but the instruction code is external alternative memory I.
J 203 to the 7-etch data bus 900,
CPU 1 via input buffer 132 and instruction bus
0 is input, and the corresponding arithmetic processing is executed. Tracer/debug circuit 300 performs a trace function for reading instruction codes from internal program memory, external program memory, and external alternate memory.

〔Effect of the invention〕

As explained above, by providing a program memory I/F and an external instruction code bus in the evaluation chip, the present invention eliminates the need for an external bus I/F/port emitter, which was previously necessary, and makes microcomputer development equipment economical. Moreover, it can be designed compactly, and since the external bus I/F/port function built into the Eva chip is used as is, it has the effect of making the electrical characteristics the same as that of a microcomputer. In addition, instruction read operation and CPU
Since the operation of the microcontroller can be made independent of the operation of the microcontroller, it is possible to provide an EV chip that can handle faster operation of the microcontroller.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a microcomputer development device using an EV chip implementing the present invention, Figure 2 is a block diagram of an EV chip implementing the present invention, and Figure 3 is a detailed diagram of the program memory I/F in Figure 2. , FIG. 4 is a timing diagram when reading instructions from the EV chip in FIG. 2, FIG. 5 is another block diagram of the EV chip implementing the present invention, FIG. 6 is a detailed diagram of the program memory emitter, and FIG. 5 is a detailed diagram of the program counter/F of the EV chip shown in FIG. 5 that implements the present invention, FIG. 8 is a timing diagram when reading instructions of the EV chip shown in FIG. 5 that implements the present invention, and FIG. 9 is a diagram of a general microcomputer. FIG. 10 is a block diagram of a microcomputer development device using a conventional Eva chip. 100...Eva chip, 200...Program memory emulator, 300...Tracer/debug circuit, 400...External memo'J
, 110...CPU, 120...Program counter, 130...Program memory I/F port, 140...External bus I/F port, 150... ...Peripheral circuit. Agent Patent Attorney Otoru Uchihara ■2 Figure 1 Figure 4

Claims (1)

[Claims] The microcomputer is used to develop and evaluate the first and second programs of a microcomputer that executes a first program stored in a built-in program memory and a second program stored in an externally attached external memory. In a microcomputer development apparatus, the evaluation processor does not have the built-in program memory, a first memory that stores the first program, a second memory that stores the second program, and a tracer/debug circuit. The evaluation processor has a first port connected to the first memory using a first bus, and a second port connected to the second memory using a second bus. the tracer/debug circuit is connected to the first bus, and the evaluation processor inputs input from the second memory to the second port via the second bus. The second program outputted to the first bus is outputted to the first bus through the first port, and the second program outputted to the first bus is outputted to the tracer/debug circuit. A microcomputer development device characterized by writing.