JP2563708B2 - Microprocessor device and emulator device using the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor device, and more particularly to a microprocessor device having a novel structure for simplifying the debugging work required when developing a microprocessor application system and an emulator device used for the same.

[0002]

2. Description of the Related Art An emulator device is one of debug support devices used in debugging application system development of a microprocessor device. This emulator device controls the operation of the microprocessor device with the microprocessor device mounted in the application system, and
It is a device that supports debugging of the application system by observing the operating state of the microprocessor device. In particular, a real-time trace function for observing the operation of the microprocessor device in a real-time operation state is an important function. In the real-time trace, since the operating state of the microprocessor device is observed in real time, the trace information is created only from the information obtained by observing the movement of the chip bus of the microprocessor device. In a microprocessor device with a simple structure, the relationship between instruction execution and instruction fetch and operand access is also simple, so the trace information necessary for debugging can be obtained simply by observing the instruction and operand accesses that occur on the chip bus. be able to.

[0003]

On the other hand, in a high performance microprocessor device, methods such as prefetching of instructions and operands and write buffering of operands are often used as means for improving performance. If these methods are adopted, the correspondence between the instruction execution order and the access order of instructions and operands on the chip bus is not unique. Therefore, it becomes difficult to know the operating state of the processor only by observing the chip bus. Therefore, it has been difficult to debug an application system using such a microprocessor device.

The above-mentioned conventional problems will be described in detail. For example, a microprocessor device for prefetching instructions / operands has a plurality of prefetch queues therein, and prefetched instructions / operands are stored in the queues. store. Then, in the case other than the branch instruction, the instructions are executed in the order stored in the queue, and the operands required for the instructions are sequentially used accordingly. If the branch instruction is taken when the branch instruction is inside the queue and the branch destination instruction is not inside the queue, the data inside the queue is purged and all instructions / operands inside the queue after the taken branch instruction are discarded. . As a result, among the instructions fetched by the microprocessor device, some instructions are not executed inside the microprocessor device and some are not used.

However, a conventional microprocessor device for prefetching instructions / operands externally outputs information indicating an instruction not executed / an operand not used, or an instruction actually executed / an operand used. Didn't have the means to output.

Also, the instruction executed as the evaluation chip /
Some of the operands used are output to the outside of the microprocessor unit, but in this case an output bus for outputting the contents of the execution PC to the outside was provided separately from the address bus, so the number of pins of the microprocessor unit Was increased by the output bus for the execution PC.

As described above, the conventional microprocessor device does not have means for outputting the information regarding the actually executed instruction / used operand to the outside of the microprocessor device. Therefore, there are the following two problems.

The first problem relates to real-time trace, which is one of the main functions of the emulator. The real-time trace function stores an input / output signal of the microprocessor device in a memory at a fixed timing, analyzes the stored memory contents, and displays the analyzed contents. That is, all the instructions / operands fetched by the microprocessor device are stored in the trace memory, analyzed and displayed.

In a microprocessor device for prefetching, if a branch is taken when the branch destination instruction is not inside the queue among the prefetched instructions, all the instructions inside the queue after the instruction that caused the branch are discarded, and the microprocessor device. Fetches a new branch destination instruction, but since the trace memory also stores the instructions inside the queue after the branch instruction that was not executed, the instruction stored in the trace memory and the microprocessor device actually The instruction executed internally will be different.

The second problem is that when there is a branch destination instruction inside the queue, there is no method from outside the microprocessor unit to know whether or not the branch is successfully taken. For example, if the branch destination instruction is inside the queue, the microprocessor device does not perform a new fetch even if the branch is taken, so it is not possible to determine from the outside of the microprocessor device whether the branch was taken. Furthermore, if there are multiple conditional branch instructions inside the queue, the same branch destination instruction when the condition is satisfied, and they are inside the queue, whether the branch was taken, and which branch condition was taken There was no way from the outside of the microprocessor unit to know if anything.

Further, when the emulator is realized by using the evaluation chip having the output bus for the execution PC, the above problems are solved, but this evaluation chip has a different configuration from the actual chip actually used by the user. Therefore, debugging cannot be done in a strict sense. In addition, a chip having an output bus for the execution PC has a larger number of output pins and a larger chip size, so that the chip cannot be actually used by the user.

Therefore, the present invention has been made to solve the problems of the above-described conventional microprocessor device and emulator device, and its purpose is to support emulators in a microprocessor device actually used by a user. A microprocessor device that can output information and an emulator device that incorporates this microprocessor device as a real chip are realized, and the results of real-time trace, which is the main function of the emulator device, are compared with the internal state of the microprocessor device. It is an object of the present invention to provide an emulator that can be analyzed accurately and easily.

[0013]

To achieve the above object, a microprocessor device according to a first aspect of the present invention generates an operand address register for storing an operand address for operand access, and the operand access. Access generation instruction address register for storing the generated access generation instruction address, an operand data register for storing input / output data to the address indicated by the operand address, an operand address output from the operand address register, and the access generation instruction An access generating instruction address output from the address register as an input signal, operating based on a selection signal given from the outside, and outputting any one of these input signals as an output signal; Means of selection The operation is characterized in that they are composed of the output means for outputting an output signal selected to the outside.

According to a fifth aspect of the present invention, a microprocessor device has an operand address register for storing an operand address for operand access, and an access generation for storing an access generation instruction address that generated the operand access. An instruction address register, an operand data register for storing input / output data to / from the address indicated by the operand address, data output from the operand data register, and an access generation instruction address output from the access generation instruction address register. A selection unit that inputs as an input signal, operates based on a selection signal given from the outside, and outputs any one of these input signals as an output signal, and an output signal selected by the operation of the selection unit to the outside. Output to It is characterized by being composed of the output means.

By the way, an emulator according to a ninth aspect is connected to the microprocessor device according to the fourth aspect, a holding means connected to an address pin as an output means in the microprocessor device, and the holding means. Address output means, trace information storage means for storing information from the address pins and data input / output pins of the microprocessor device and the address output means as trace information at the time of real-time trace, and the selection signal to generate the selection signal. And a trace control means for outputting to the selecting means in the processor device, generating a holding signal to output to the holding circuit, and generating a storage signal to output to the trace storing means. When the hold signal is enabled and the selection signal is enabled And having a function of outputting the operand address in the serial address output means.

Furthermore, a microprocessor device according to an eleventh aspect of the present invention includes an address generation unit for generating an address for memory access, an execution PC register indicating an execution PC to be executed by an arithmetic unit, and the address generation unit. A multiplexer for multiplexing the output signal from the execution PC register according to the change of the state of the selection signal given from the outside, and the output signal from the address generation unit and the execution PC register by the operation of the multiplexer. When the selection signal is in a disable state, the output signal from the address generator is output to the address bus, and the selection signal is enabled. , The output signal from the address generator and the execution P By multiplexing the output signals from the register at a predetermined timing, characterized by having a function of outputting these output signals to the address bus.

An emulator according to a fourteenth aspect temporarily outputs an output signal from the microprocessor device according to the twelfth aspect and the address generation unit output via the address bus in the microprocessor device. And a trace information storage means for storing output signals from the address generation unit and the execution PC register obtained via the address bus, that is, trace information at the time of real-time trace. The holding means is controlled by a holding signal that indicates the timing of storing the trace information, and the trace storage means is controlled by a storage signal that indicates the timing of storing the trace information, and the selection signal is in the enable state. And when the hold signal changes to the disable state The holding means holds the input signal and outputs the content thereof, and stops the output when the holding signal changes to the enable state, and when the selection signal and the storage signal are both in the disable state, the microprocessor device The trace information storage means has a function of storing an execution instruction address as an output signal output from the above through the address bus.

The emulator according to the fifteenth aspect further comprises a holding means for temporarily holding an output signal from the address generation section output via the address bus in the microprocessor device mounted during the emulator test,
The trace information storage unit stores output signals from the address generation unit and the execution PC register obtained via the address bus, that is, trace information at the time of real-time trace, and the holding unit stores the trace information. The trace signal is controlled by a holding signal that indicates the timing of storing the trace information, and the trace storage unit is controlled by a storage signal that indicates the timing of storing the trace information. When the selection signal is in the enable state and the holding signal is in the disable state. When the holding signal holds the input signal and outputs its content when the holding signal changes to the enable state, the holding means stops the output, and when the selection signal and the storage signal are both in the disable state. From the microprocessor via the address bus The trace information storing means execution instruction address as an output signal is characterized by having a function of storing.

[0019]

Since the microprocessor device of the present invention is provided with the means for outputting the address of the access generation instruction in which the operand access is generated by the external selection signal,
In debugging a system to which the microprocessor device is applied, it is possible to output the address of an access generation instruction that has generated an operand access to the outside. Therefore, it becomes possible to easily associate instructions and operands, and debug work becomes easy.

Further, in the microprocessor device having another structure, the address in the execution PC (program counter) can be output to the outside of the microprocessor device, so that the debugging work is simplified.

Further, the emulator using the microprocessor device has a holding means for temporarily holding the address of the execution instruction or the address of the execution PC,
Since these addresses can be stored in the trace information storage means at a predetermined timing, efficient debugging can be executed.

[0022]

EXAMPLES The present invention will be described in detail below with reference to examples.

In the following description of the operating states, LOW enable and HIGH disable are used.

FIG. 1 is a block diagram showing the configuration of a microprocessor device according to the first embodiment of the present invention. The microprocessor device 1 further includes an operand data register 2 for holding data required for operand access, an operand address register 3 for holding an operand address used for operand access, and a configuration of a conventional microprocessor. An access generation instruction address register 4 that holds the address of the access generation instruction that generated this operand access, and either the register 3 or the content of register 4 is selected by the external selection signal sent via the external selection signal line 6. The selection circuit 5 outputs the selected content to the address signal line 7 via the address pin in the microprocessor device 1. Note that normal signal lines are used for other signal lines (eg, data signal line, control signal line, etc.) required for operand access. In the figure, 8 indicates a data signal line for inputting / outputting data to / from the operand data register 2.

In the microprocessor device 1 having the above-mentioned structure, the contents of the operand address register 3 or the operand address are generated on the address signal line 7 by a selection signal given from the outside of the chip through the selection signal line 6, for example. It is possible to select and output any of the contents of the access generation instruction address register 4. As a result, for example, when the microprocessor device 1 is debugged, the address of the access generation instruction and the operand address are transferred to the address signal line 7 by controlling the selection signal.
Since the output timing of the above signal can be time-division-multiplexed and output, the correspondence information between the operand address and the access generation instruction executed by the microprocessor device 1 that has generated it can be output to the outside. Therefore, debugging becomes easy.

Considering another configuration based on the basic concept of the present invention, a configuration in which a dedicated signal pin for outputting an instruction address at the time of operand access is provided in the microprocessor device 1 is also conceivable. However, in this case, the number of pins of the microprocessor device 1 is greatly increased, which is not practical. On the other hand, according to the configuration of the embodiment shown in FIG. 1, by using the signal timing on the address signal line by time division multiplexing, the data on the data signal line 8 can be accessed without increasing the number of pins so much. It is possible to output the instruction address of the instruction that is the generation source.

In the microprocessor device 101 as the embodiment of the present invention shown in FIG. 1, the address signal line 7 connected to the address pin is used to output the address of the access generation instruction. However, the present invention is not limited to such a configuration. That is, in the microprocessor device 101 as another embodiment of the present invention shown in FIG. 2, the selection circuit 105 is provided for the access generation instruction address register 104 and the operand data register 102, and the access generation instruction of the access generation instruction is provided on the data signal line 108. It is also possible to time-division-multiplex the address and the operand data and output.

FIG. 3 is a debug support device (emulator device) 1 for the microprocessor device 1 shown in FIG.
It is a block diagram of No. 0, showing a second embodiment of the present invention. In the figure, an address signal line 11 for transmitting an address signal which is switched in time division and used for outputting an operand access and an access generation instruction address from the microprocessor unit 1 is a holding circuit for holding an operand address. 13 is connected. The output (address signal) of the holding circuit 13 is the address signal line 12
The operand address is supplied to the target system 30 via the. In the trace memory 14 for storing trace information at the time of real-time trace, in addition to the address signals on the address signal lines 11 and 12, the data signal line 15 and the control signal line 16 which are other signal lines constituting the chip bus are provided. It is connected. Selection signal output to microprocessor device 1 via selection signal 17, holding circuit 13
To the holding signal line 18,
The storage signal output to the trace memory 14 via the storage signal line 19 is generated by the control circuit 20.

FIG. 4 is an operation timing chart of the debug support device 10 shown in FIG. Next, the operation of the debug support device 10 shown in FIG. 3 will be described with reference to FIG. When starting the operand access, the microprocessor unit 1 outputs the operand address to the address signal line 11. At this point, the trace control circuit 20 sets the selection signal (on the selection signal line 17) output to the microprocessor device 1 to a value for outputting the operand address in the operand address register 3 (shown at low level in FIG. 4). Further, the trace control circuit 20 deactivates the hold signal (on the hold signal line 18) output to the hold circuit 13 (indicated by the low level in FIG. 4), and the address signal (address signal as an address output line which is an input to the hold circuit 13 ( Address signal line 1
The value of 1) is output as it is to the output address signal (on the address signal line 12). When the trace control circuit 20 activates the holding signal (on the holding signal line 18) (shown at a high level in FIG. 4), the holding circuit 13 stores the input value at that time in the holding circuit 13, and the holding signal While being activated (H level), the stored value is output onto the address signal line 12. Therefore, the target system 30 is supplied with the operand address from the holding circuit 13 until the end of the bus cycle. After the operand address is stored in the holding circuit 13, the control circuit 20 sets the selection signal (selection signal line 17) to a value for outputting the access generation instruction address (shown in high level in FIG. 4). The microprocessor device 1 receives this signal and outputs the execution instruction address on the address signal line 11 in place of the operand address that has been output so far. After that, at the timing when the operand data becomes valid, the trace control circuit 20
Activates the storage signal for the trace memory 14 (see FIG.
Then, the trace memory 1
Trace information is stored in 4. In this case, the trace information is the access generation instruction address output on the address signal line 11. In the device shown in FIG. 3, as the trace information, the access generation instruction address, the operand address, the operand data, and the control signal are the trace memory 1
4 via the signal lines 19A, 19B, 19C and 19D (the signal lines 19A to the trace memory 14 are stored.
19B, 19C, and 19D may be provided for each type of information, and the respective storage signals may be given at different timings).

In the first and second embodiments of the present invention shown in FIGS. 1 and 3, the operation has been described without mentioning the relationship between the bus cycle and the clock cycle. When it is composed of clock cycles, the operation is easily controlled. For example, in a microprocessor device in which one bus cycle requires two clock cycles, the operand address at the first clock,
The execution instruction address is output at the second clock. When one bus cycle requires two clock cycles or more, it can be easily realized in terms of timing without using a particularly high-speed element.

In the emulator as the second embodiment shown in FIG. 3, when the address information of the execution instruction that generated the operand access is output on the address signal line 11 and this information is time-division multiplexed and output. , Which is shown in FIG.
It is also possible to use other signal lines which have a time margin at the time of operand access as shown in the section of the description of the embodiment. For example, the same function can be realized by using the data signal line 15.

The data signal line 15 is a bidirectional signal line unlike the address signal line, but it can be applied by changing the timing of outputting the execution instruction address at the time of reading and writing. For example, when one bus cycle is executed in two clocks, the access generation instruction address can be output in the first clock in the read operation and in the second clock in the write operation.

In the second embodiment shown in FIG. 3, the case where the address value of the access generation instruction address is directly output is shown. However, if the address value can be associated with a part of the address value. Alternatively, the same effect can be obtained by outputting the relative address based on the difference from the reference address value.

As described above, the emulator device 1 of FIG.
When it is 0, it is possible to obtain the trace information such as the execution instruction address necessary for the real-time trace without extremely increasing the number of pins of the microprocessor device.
For this reason, the correspondence between operand access and instruction execution on the chip bus becomes clear, and debugging during development of a microprocessor device application system becomes easy. In addition,
The microprocessor device 1 shown in FIGS. 1 and 3 requires a function for associating an operand with an access generation instruction and a mechanism for outputting the address of the access generation instruction inside the microprocessor device, but in this case, the number of pins is increased. Is one.

Furthermore, considering the case of the debug support device (emulator device) for the microprocessor device according to the present invention shown in FIG. 3, a holding circuit for supplying an address signal to the target system and a selection signal and a holding signal. Although a control circuit for controlling the signal is newly required, the circuit configuration is simple and the increase in hardware is small. From the increase of these hardware,
The introduction of the microprocessor device 1 of the present invention has a great advantage that the software for analyzing the instruction execution from the trace information becomes simple.

In the above first and second embodiments, the execution instruction address can be obtained by time division multiplexing the address signals on the address signal lines.

The present invention time-division-multiplexes address signals,
It is also possible to obtain PC (program counter) data instead of the access generation instruction address. At this time, in the case of a high-performance microprocessor, a PC indicating an instruction being processed in each unit is provided in the instruction fetch unit, the decode unit, the operand management unit, the execution unit, etc. It is also possible to specify the PC and output its data (address).

A microprocessor device and an emulator device having the above-mentioned functions as the third and fourth embodiments of the present invention will be described below with reference to FIGS.

FIG. 5 is a schematic configuration diagram of a microprocessor device according to a third embodiment of the present invention. The minimum bus cycle used in the microprocessor device 40 of this embodiment is 2 clocks and has a bus cycle end signal (see FIG. 9) output through the bus cycle end signal line 74. In the figure, outputs from the address generation unit 44 and the execution PC register 45 are input to the multiplexer 41.
Switch to select these outputs and select the address bus 42
Output to. The multiplexer 41 is selectively controlled by an input signal for mode switching input via a mode switching signal line 43, and when this signal is disabled (H level), the address generation unit is set as shown in the timing chart of FIG. Only the information of 44 is output to the address bus signal output line 72 in one bus cycle. When this signal is enabled (Low level), the information from the address generator 44 and the information from the execution PC register 45 are switched by the multiplexer 41 during one bus cycle as shown in the timing chart of FIG. It has a function of outputting to the bus 42.

FIG. 8 is a schematic configuration diagram of an emulator device as a fourth embodiment of the present invention in which the microprocessor device 40 of the third embodiment of the present invention is a microprocessor to be debugged.

The emulator device 70 incorporates the debugged microprocessor device 40 therein, and inputs / outputs signals input / output from the microprocessor device 40 via an address bus signal output line 72 to a user board (not shown). Input to an input terminal (not shown) for the microprocessor device.

In the case of the emulator 70 using the microprocessor device 40 of the third embodiment of the present invention, the output timing to the address bus signal output line 72 to the user board is always made equal to that when the mode switching signal 43 is disabled. The microprocessor to be debugged 40
And a signal output line 72 connected to the user board, a latch circuit 77 for latching the address bus is provided. The latch circuit 77 holds the memory address information in the address generation unit 44 in the first half of the bus cycle until the bus cycle end signal is output so that the address bus timing in the debugged mode is set for the user board. adjust. Further, since the latch operation by the latch circuit 77 is required only when the mode switching signal is enabled (L level), the operation control of the latch circuit 77 is performed by the mode switching signal. FIG. 9 shows operation timings of signals in the emulator device 70 shown in FIG.

The execution PC trace memory 78 stores the execution P
It is for storing the address of C, and the output signal of the address bus is sampled in the trace memory according to the bus cycle end signal. Since the address of the execution PC is output only when the mode switching signal is enabled (L level), the execution P is executed similarly to the latch circuit 77.
The operation control of the C trace memory 78 can be performed by a mode switching signal.

The execution PC trace memory 78 is a memory for storing the address information of the execution PC output from the address bus signal output line 72 when the mode switching signal is enabled (active). By comparing the execution PC stored here and the address bus information stored in the real-time trace unit, the real-time trace result regarding the instruction actually executed inside the microprocessor can be analyzed.

[0045]

As described above in detail with reference to the embodiments, the microprocessor device according to the present invention can output the access generation instruction address by the selection control signal, so that the correspondence between the operand access and the instruction execution becomes clear. , Debugging of microprocessor device application system becomes easy. Particularly when performing an operation test of a high-performance microprocessor device, the debugging work can be simplified by using the microprocessor device of the present invention and the emulator device of the present invention in combination.

Further, according to the present invention, since the operation timing of the microprocessor device can be controlled by the selection control signal and the address of the execution PC can be output to the outside using the address bus, an output bus dedicated to the execution PC is provided. It becomes possible to easily analyze the analysis of the real-time trace result, which is the main function of the emulator, faithfully to the operation inside the microprocessor device.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a microprocessor device as a first embodiment of the present invention.

FIG. 2 is another schematic configuration diagram of the microprocessor device shown in FIG.

3 is a schematic configuration diagram of an emulator device as a second embodiment of the present invention, which uses the microprocessor device shown in FIG.

FIG. 4 is a timing chart showing an operation of the emulator device shown in FIG.

FIG. 5 is a schematic configuration diagram of a microprocessor device as a third embodiment of the present invention.

6 is a timing chart showing an operation of the microprocessor device shown in FIG.

7 is a timing chart showing an operation of the microprocessor device shown in FIG.

8 is a schematic configuration diagram of an emulator device as a fourth embodiment of the present invention, which uses the microprocessor device shown in FIG.

9 is a timing chart showing an operation of the emulator device shown in FIG.

[Explanation of symbols]

1 Microprocessor 2 Operand data register 3 Operand address 4 Execution instruction address register 5 Selection circuit 6 Selection signal line 7 Address signal line 10 Emulator device 40 Microprocessor 42 Address bus 43 Mode switching signal line 71 Address bus signal output from microprocessor 40 Line 72 Address bus signal output line 73 Mode switching signal input line 74 Bus cycle end signal line 75 Clock

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-2-158847 (JP, A) JP-A-60-262251 (JP, A) Interface No. 56 (Sho 57-1-1), CQ Publishing, P.P. 119-124

Claims (15)

(57) [Claims] 1. An operand address register for storing an operand address for an operand access, an access generation instruction address register for storing an access generation instruction address that generated the operand access, and an input for an address indicated by the operand address. An operand data register that stores output data, an operand address that is output from the operand address register, and an access generation instruction address that is output from the access generation instruction address register are input as input signals, and a selection signal that is given from the outside is input. Operating on the basis of one of these input signals as output signal
A microprocessor device comprising: a selection unit for outputting one of the two; and an output unit for outputting the output signal selected by the operation of the selection unit to the outside. 2. The microprocessor device according to claim 1, wherein the output means is an address pin. 3. The selecting means uses the operand address as the output signal when the selection signal is in an enabled state, and sets the operand address and the access generation instruction address at a predetermined timing when the selection signal is in a disabled state. 2. The microprocessor device according to claim 1, which is selected and used as the output signal. 4. The selecting means uses the operand address as the output signal when the selection signal is in the enable state, and uses the operand address and the access generation instruction address as the output signal when the selection signal is in the disable state. The microprocessor device according to claim 1, wherein: 5. An operand address register for storing an operand address for operand access, an access generation instruction address register for storing an access generation instruction address that has generated the operand access, and an input for an address indicated by the operand address. An operand data register for storing output data, data output from the operand data register and an access generation instruction address output from the access generation instruction address register are input as input signals,
A selection unit that operates based on a selection signal given from the outside and outputs any one of these input signals as an output signal, and an output for outputting the output signal selected by the operation of the selection unit to the outside. A microprocessor device comprising means and. 6. The microprocessor device according to claim 5, wherein the output means is a data input / output pin. 7. The selecting means selects the data as the output signal when the selection signal is in the enable state, and selects the data and the access generation instruction address at a predetermined timing when the selection signal is in the disable state. The microprocessor device according to claim 5, wherein the output signal is the output signal. 8. The selecting means uses the data as the output signal when the selection signal is in the enable state, and uses the data and the access generation instruction address as the output signal when the selection signal is in the disable state. 6. A microprocessor device according to claim 5, characterized in that 9. The microprocessor device according to claim 4, holding means connected to an address pin as output means in the microprocessor device, address output means connected to the holding means, and the microprocessor. Trace information storage means for storing information from the address pin, data input / output pin of the processor device and the address output device as trace information at the time of real-time tracing, and generating the selection signal and outputting it to the selection device in the microprocessor device. And a trace control unit that generates a hold signal and outputs the hold signal to the hold circuit, and generates a store signal and outputs the store signal to the trace storage unit, wherein the hold unit is provided when the hold signal is enabled. When the selection signal is enabled, the operand address is sent to the address output means. Emulator device and outputs a. 10. Holding means for inputting an operand address output via an address pin in a microprocessor device installed during an emulation test and temporarily holding the operand address, and the holding means obtained via the address pin. Trace information storage means for storing an operand address and an access generation instruction address, that is, trace information at the time of real-time trace, and a holding signal for outputting the selection signal at a predetermined timing and instructing the holding means for the timing for storing the trace information. And a trace control means for controlling to output a storage signal for instructing a timing of storing the trace information to the trace information storage means, when the selection signal is in the enable state and the holding signal When changes to the disable state The holding means holds the input signal and outputs the contents thereof, and stops the output when the holding signal changes to the enable state, and when both the selection signal and the storage signal are in the disable state, the microprocessor device An emulator device, wherein the trace information storage means stores an access generation instruction address as an output signal output from the address bus via the address bus. 11. An address generation unit for generating an address for memory access, an execution PC register indicating an execution PC to be executed by an arithmetic unit, output signals from the address generation unit and the execution PC register, A multiplexer for multiplexing in accordance with a change in the state of the selection signal given from the address, and an address for outputting the output signal from the address generation unit and the output signal from the execution PC register to the outside by the operation of the multiplexer. When the selection signal is in the disable state, the output signal from the address generator is output to the address bus, and when the selection signal is in the enable state, the output signal from the address generator is The output signal from the execution PC register is circled at a predetermined timing. By pulex, microprocessor instrumentation characterized by having a function of outputting these output signals to said address bus
Place . 12. The microprocessor device according to claim 11, wherein the address generator generates an operand address. 13. The microprocessor device according to claim 11, wherein the address generation unit generates an execution instruction address. 14. The microprocessor device according to claim 12, and holding means for temporarily holding an output signal from the address generation unit output via the address bus in the microprocessor device, The trace information storage unit stores output signals from the address generation unit and the execution PC register obtained via an address bus, that is, trace information at the time of real-time trace, and the holding unit stores the trace information. the hold signal for instructing the timing of, and the trace information price
The storing means is controlled by a storage signal instructing a timing of storing the trace information, and the holding means outputs an output signal when the selection signal is in the enable state and when the holding signal changes to the disable state. Hold and output its contents, and stop the output when the hold signal changes to the enable state, and when both the select signal and the storage signal are in the disable state, from the microprocessor device via the address bus. An emulator device , wherein the trace information storage means stores an execution instruction address as an output signal. 15. Holding means for temporarily holding an output signal from an address generation unit output via an address bus in a microprocessor device mounted during an emulator test, and the holding means obtained via the address bus. It is composed of an output signal from the address generation unit and the execution PC register, that is, trace information storage means for storing trace information at the time of real-time trace, and the holding means uses a hold signal for instructing a timing for storing the trace information. In addition, the trace information case
The storing means is controlled by a storage signal instructing a timing of storing the trace information, and the holding means outputs an output signal when the selection signal is in the enable state and when the holding signal changes to the disable state. Hold and output its contents, stop the output when the hold signal changes to the enable state, and output from the microprocessor via the address bus when both the select signal and the storage signal are in the disable state The emulator device , wherein the trace information storage means stores the execution instruction address as the output signal.