JP3166667B2 - Emulation microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an emulation microcomputer, and more particularly to an emulation microcomputer which senses a voltage level of an external input terminal and uses the result as a read value of a register.

[0002]

2. Description of the Related Art Conventionally, an emulation microcomputer is applied as an in-circuit emulator for emulating a flash memory self-writing function. Recently, microcomputers with built-in flash memory (hereinafter also referred to as flash microcomputers)
The number of devices having a function of rewriting a flash memory in which a user program is stored by controlling firmware without using a dedicated writer according to the user program is increasing. This is a so-called flash memory self-writing function. With the increase of this function, an in-circuit emulator capable of emulating this function is required.

A configuration of a conventional in-circuit emulator will be described with reference to FIG. The conventional in-circuit emulator 100 is set between the target system 6 and the host 7. The in-circuit emulator 100 is roughly composed of an emulation unit 101 and a debug unit 2. One emulation unit 101 includes a CPU evaluation chip 3 that is functionally equivalent to the target microcomputer, a peripheral evaluation chip 102 that is functionally equivalent to the peripheral part of the target microcomputer, and an emulation memory corresponding to the memory of the target microcomputer. And 5.

An emulation section 101 which is a component of the in-circuit emulator 100 has a CPU function of a target microcomputer and a CPU evaluation chip 3.
Peripheral functions of the target microcomputer
At 02, the memory of the target microcomputer is emulated by the emulation memory 5, respectively. Further, an interface (not shown) with the debug unit 2 is provided as an interface (hereinafter, also referred to as an I / F) with the target system 6. The peripheral evaluation chip 102 functions as a peripheral evaluation chip by using a target emulation microcomputer (a flash microcomputer is applied in the conventional example) in an emulation mode. The debug unit 2 has functions necessary for debugging such as a break function and a trace function, an I / F with the host 7 such as a personal computer or a workstation, and an I / F with the emulation unit 101.

FIG. 6 is a block diagram showing a more detailed configuration example of the peripheral evaluation chip 102 of FIG. The details of the peripheral evaluation chip 102 will be described below with reference to FIG.

RESET terminal 1 of peripheral evaluation chip 102
The RESET signal 30 which is LOW active is input to the outside from the VPP / MODE terminal 111.
Is supplied with an output signal 111 from the mode pull-in unit 103. The mode pull-in unit 103 is a selector having a function of outputting either the VPP signal 120 as an external input signal or the signal 31 fixed to GND as the signal 121. When the RESET signal 30 becomes LOW level, the signal 31 is selected, and the RESET signal 30 becomes H level.
When it reaches the IGH level, the VPP signal 1
Select 20.

[0007] The mode detection unit 112
02 mode is detected. At the rising edge of the RESET signal 30 from LOW to HIGH, the level of the signal 121 of the VPP / MODE terminal 111 is detected. The peripheral evaluation chip 102 enters the normal mode if the level of the signal 121 is higher than the HIGH level,
If the level is set, the emulation mode is set.

[0008] The high voltage detecting unit 113 detects a high voltage (10 V).
Has a function of detecting whether or not is applied. V
When the level of the signal 121 of the PP / MODE terminal 111 is 10
If it is V, it outputs a HIGH level; otherwise, it outputs a LOW level to the signal 125. The decoding unit 114 is an address decoder for accessing a register. The read / write signal generation unit 115 outputs the FLPMC register 1
17 controls writing and reading. The FLPMC register 117 is an 8-bit register, but has no latch for writing and holding data in the VPP bit (bit 1), and outputs the output signal of the high voltage detection unit 113 as read data.

Next, the operation of the conventional in-circuit emulator 100 when emulating flash memory self-writing will be described with reference to FIGS.

The flash memory self-writing is a function of rewriting the flash memory by making the firmware stored in the normally invalid back ROM in the flash microcomputer valid by a user's boot program and executing it. However, a high voltage is required to actually rewrite the flash memory. Therefore, before the firmware is executed, the boot program determines whether a high voltage (10 V) is applied to the VPP / MODE terminal of the flash microcomputer by checking the VPP of the FLPMC register.
It must be checked by reading the bit. The VPP bit of this FLPMC register is VP
If P = 1, a high voltage is applied to the VPP / MODE terminal.

In the in-circuit emulator 100, when the flash memory self-writing boot program in the emulation memory 5 is executed, an instruction to read the VPP bit of the FLPMC register of the peripheral evaluation chip 102 is executed. Execution of this instruction is VP
This is to check whether 10 V is applied to the P / MODE terminal 111. At this time, when the level of the VPP signal 120 is set to 10 V, 10 V is applied to the VPP / MODE terminal 111 for high voltage detection, and 10 V is detected by the high voltage detection unit 113. , HIGH level signal 125 is output. However, the VPP / MODE terminal 111 is a terminal shared with mode detection, and the peripheral evaluation chip 102
It is necessary to set a mode after resetting. Therefore, a selector such as a mode pull-in unit 103 is required outside the microcomputer in order to set an emulation mode by resetting and then detect a high voltage.

Next, when the VPP bit of the FLPMC register is read by the boot program, the address of the FLPMC register is sent to the address data bus 122. Then, the address is decoded by the decoding unit 114, and the output signal 123 becomes HIGH level. Signal 123
When the read / write signal generation unit 115 becomes active, the read signal 124 is output and the gate of the tri-state buffer 116 is opened, so that the high voltage detection unit 113
Is output to the address data bus 122 as a read value of the VPP bit of the FLPMC register, and VPP = 1 can be read.

As described above, when emulating this function, the in-circuit emulator 100
Since the emulation memory 5 is rewritten instead of the flash memory, a high voltage is not required for writing the emulation memory 5 itself.
In order to check the VPP bit of the MC register, it is necessary to input a high voltage.

Another conventional example having a similar technical field to the present invention is "Microcomputer, evaluator chip and emulator using the same" in JP-A-2-130640. In this conventional example, switching between the normal operation mode and the emulation mode is possible, and the emulation mode occupies a large weight. If emulation is not provided in a timely manner, it will seriously hinder the development schedule. The present invention is said to be effective in this regard.

[0015]

However, according to the above-mentioned prior art, when the in-circuit emulator emulates the self-writing of the flash memory, the VPP bit of the FLPMC register is set to VP.
Since the voltage level of the P / MODE terminal is sensed and read, a high voltage (10 V) must be applied to the VPP / MODE terminal to create a state of VPP = 1. Further, since the VPP / MODE terminal is a terminal for both high voltage detection and mode detection, there is a problem that an external circuit having a selector function such as a mode pull-in unit is required.

The present invention requires no external circuit, and
An object of the present invention is to provide an emulation microcomputer capable of emulating flash memory self-writing without inputting a high voltage signal to a PP / MODE terminal.

[0017]

In order to achieve the above object, an emulation microcomputer according to the present invention stores a predetermined level of data indicating a state where a high voltage necessary for rewriting a flash memory is applied. It is characterized in that it has a register that stores the VPP bit in advance, and the VPP bit of the register can be read by the boot program during the emulation mode.

Further, the above-mentioned VPP bit can be written only in the break state.
By setting the P bit to “1” or “0”, it is preferable to enable emulation of flash memory self-writing.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an emulation microcomputer according to the present invention will be described in detail with reference to the accompanying drawings. 1 to 4 show an embodiment of an emulation microcomputer according to the present invention.

<First Embodiment> FIG. 1 is a configuration diagram of an in-circuit emulator using an emulation microcomputer according to the first embodiment. FIG. 2 is a more detailed configuration diagram of the peripheral evaluation chip 4 which is a component of the in-circuit emulator of FIG.

An in-circuit emulator 8 in which the emulation microcomputer of the present embodiment is applied as the peripheral evaluation chip 4 includes an emulation unit 1 and a debug unit 2. The emulation unit 1, which is a component of the emulation unit, has an emulation memory 5
It has a PU evaluation chip 3 and a peripheral evaluation chip 4.
The difference between the configuration of the in-circuit emulator 8 of FIG. 1 and the configuration of the conventional in-circuit emulator 100 of FIG. 5 lies in the peripheral evaluation chips 4 and 102. Therefore, the present embodiment will be described mainly with reference to FIG. 2 which is a detailed view of the peripheral evaluation chip 4.

FIG. 6 shows the peripheral evaluation chip 4 of this embodiment.
And there is no external circuit like the conventional mode pull-in unit 103 shown in FIG.
The signal 31 is directly input to the VPP / MODE terminal 11. The mode detection unit 12 has a function of the conventional mode detection unit 112,
The function to output the level and the LOW level in the emulation mode is added. The function of the high voltage detector 13 is the same as the function of the high voltage detector 113 of the conventional example. Also, the function of the decoding unit 14 is the same as the function of the decoding unit 114 of the conventional example.

The break detection unit 25 is connected to the HIG when the user's program is not executed in the in-circuit emulator 8 (hereinafter referred to as a break state).
An H-level signal is output, and a LOW-level signal is output when the user program is running.

A read / write signal generator 15 for controlling reading / writing of the FLPMC register 23;
The read / write signal generator 16 that controls reading and writing of the MC register 24 is mapped to the same address. These read / write signal generators 15 and 16 respectively mask the output signal 33 from the decoder 14 with the output signal 34 of the mode detector 12 and the output signal 35 of the inverter 17 which is an inverted signal of the output signal 34.
Which of the output signals 36 to be activated is selected by the output signal 36 of D19 and the output signal 37 of AND18.

The FLPMC register 23 is a conventional FLP
The configuration is the same as that of the MC register 117. When the read / write signal generation unit 15 is active, the peripheral evaluation chip 4
Is equivalent in circuit to the peripheral evaluation chip 102 of the conventional example.

The FLPMC register 24 of this embodiment is
The configuration of the VPP bit is different from the FLPMC register 117 of the conventional example. That is, it has a latch 21 for writing and storing data, and the VPP of the FLPMC register 24
The bits can be written by the output signal 43 of the AND 26 obtained by masking the write signal output 39 of the read / write signal generator 16 with the output signal 42 of the break detector 25. Further, the gate of the tri-state buffer 22 can be opened by the read signal output 40 of the read / write signal generator 16 to read data. Further, the latch 21 does not change the value stored by the reset.

Next, the operation at the time of emulation of flash memory self-writing in the first embodiment will be described.
This will be described with reference to FIGS. As in the conventional example, the FLPMC register 2 is used in the user's boot program.
The VPP bits 3, 24 are read to check whether VPP = 1. The relationship between this check and the start of emulation is as follows.

When the address of the FLPMC register is sent to the address data bus 32, the address is decoded by the decoding unit 14, and the output signal 33 becomes HIGH. During the emulation mode, the signal 35 becomes HI.
GH level, the read / write signal generator 16
Becomes active, and the FLPMC register 24 can be accessed.

The VPP bit of the FLPMC register 24 can be written only in the break state. Therefore,
In the break state, the FLP
"1" or "0" in the VPP bit of the MC register 24
Is set in the host 7 so that VPP =
One or zero states can be created. Therefore, VP
Emulation of flash memory self-writing can be performed without applying a high voltage to the P / MODE terminal 11.

Since there is no need to sense the voltage level of the external terminal, the VPP / MODE terminal 11 only needs to function as a terminal for mode detection. Therefore, if fixed to GND, the peripheral evaluation chip 4 is set to the emulation mode by reset. Even if reset, F
The VPP bit of the LPMC register does not change the held value.

<Second Embodiment> An in-circuit emulator 5 according to a second embodiment of FIG.
0 and the configuration of the conventional in-circuit emulator of FIG.
There are two differences. Therefore, the present embodiment will be described mainly with reference to FIG. 4 which is a detailed view of the peripheral evaluation chip 52. The peripheral evaluation chip 52 of the present embodiment does not have an external circuit like the mode pull-in unit 103 of FIG. 4 in the related art, and the RESET signal 30 is transmitted to the RESET terminal 60 and the
A signal 31 is directly input to 1.

The mode detecting section 62 has a function of outputting a HIGH level in the normal mode and a LOW level in the emulation mode to the function of the mode detecting section 112 of the conventional example. The function of the high voltage detection unit 63 is the same as the function of the high voltage detection unit 113 of the conventional example. The function of the decoding unit 64 is also the same as the function of the decoding unit 114 of the conventional example.

The break detecting section 66 sets the HI in the in-circuit emulator 50 when the user's program is not executed (hereinafter referred to as a break state).
It outputs a GH level signal and outputs a LOW level signal when the user program is running. The read / write signal generation unit 65 is activated by an output signal 81 from the decoding unit 64, and controls reading and writing of the FLPMC register 69.

The FLPMC register 69 corresponds to the FL shown in FIG.
The configuration of the VPP bit is different from that of the PMC register 117. The VPP bit of the FLPMC register 69 has a latch 70 for writing and holding data and not changing the value held by reset. The latch 70 can write data by the output signal 86 of the AND 67 obtained by masking the write signal output 84 of the read / write signal generator 65 with the output signal 85 of the break detector 66.

When reading the VPP bit of the FLPMC register 69, it selects whether to read the data of the latch 70 or the output signal 87 of the high voltage detector 63. This selection is performed by setting the read signal output 83 of the read / write signal generation unit 65 to the output signal 82 from the mode detection unit 62 and the inverted signal of the output signal 8 of the inverter 68.
8 and the output signals 90 and A of the AND 71 respectively masked.
The gate of the tri-state buffer 73 or the tri-state buffer 74 is opened by the output signal 91 of the ND 72 to perform the operation.

Next, an operation example during emulation of flash memory self-writing in the second embodiment will be described with reference to FIGS. In this operation example, as in the conventional example, the FLP
The VPP bit of the MC register 69 is read and the VPP
Check if = 1. The relationship between this check and the start of emulation is as follows.

When the address of the FLPMC register is sent to the address data bus 80, the address is decoded by the decoding unit 64, the output signal 81 becomes HIGH, and the read / write signal generation unit 65 becomes active. Register 69 can be accessed. The VPP bit of the FLPMC register 69 can write data to the latch 70 only in the break state, and reads the data of the latch 70 during the emulation mode. Therefore, in the break state, the debugger 2 previously sets the VPP bit of the FLPMC register 69 to “1”.
Alternatively, if the host 7 is set to write “0”, a state of VPP = 1 or 0 can be created.
Further, emulation of flash memory self-writing can be performed without applying a high voltage to the VPP / MODE terminal 61.

Further, since it is not necessary to sense the voltage level of the external terminal, the VPP / MODE terminal 61 only has to function as a terminal for mode detection. Set to emulation mode. FLPMC by reset
The value of the VPP bit of the register 69 is not changed.

The above embodiment is an example of a preferred embodiment of the present invention. However, it is not limited to this.
Various modifications can be made without departing from the spirit of the present invention.

[0040]

As is clear from the above description, the emulation microcomputer of the present invention stores a predetermined level of data indicating a state in which a high voltage necessary for rewriting the flash memory is applied to the VP in advance.
The data is stored in the P bit, and the VPP bit can be read by the boot program during the emulation mode. Therefore, even when a high voltage signal is not input to the VPP / MODE terminal, emulation of flash memory self-writing can be performed, and high voltage is not required.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an in-circuit emulator of a first embodiment to which an emulation microcomputer of the present invention is applied.

FIG. 2 is a more detailed block diagram of the peripheral evaluation chip 4 of FIG. 1;

FIG. 3 is a configuration diagram of an in-circuit emulator according to a second embodiment.

FIG. 4 is a more detailed block diagram of the peripheral evaluation chip 52 of FIG. 3;

FIG. 5 is a configuration diagram of a conventional in-circuit emulator.

FIG. 6 is a more detailed block diagram of the peripheral evaluation chip 102 of FIG. 5;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Emulation part of 1st embodiment 2 Debugging part 3 CPU evaluation chip 4 Peripheral evaluation chip (flash microcomputer) of 1st embodiment 5 Emulation memory 6 Target system 7 Host 8 In-circuit emulator of 1st embodiment 10 First RESET terminal of the embodiment 11 VPP / MODE terminal of the first embodiment 12 Mode detection unit of the first embodiment 13 High voltage detection unit of the first embodiment 14 Decoding unit of the first embodiment 15 First Read / write signal generator of the embodiment 16 Read / write signal generator of the first embodiment 17 Inverter 18 AND circuit 19 AND circuit 20 Tristate buffer 21 Latch 22 Tristate buffer 23 FLPMC register 24 of the first embodiment 24 F of the first embodiment PMC register 25 Break detector of the first embodiment 26 AND circuit 30 RESET signal 31 GND fixed signal 32 Address data bus 33 Output signal of decode unit 34 Output signal of mode detector 12 35 Output signal of inverter 17 36 AND19 Output signal 37 AND 18 output signal 38 read signal output of read / write signal generator 15 39 read signal output of read / write signal generator 16 40 write signal output of read / write signal generator 16 41 high voltage detector 13 42 output signal of the break detection unit 25 43 output signal of the AND 26 44 output signal of the latch 21 50 in-circuit emulator 51 of the second embodiment 51 emulation unit 52 of the second embodiment 52 peripheral evaluation chip of the second embodiment (Flash 60) Reset terminal according to the second embodiment 61 VPP / MODE terminal according to the second embodiment 62 Mode detection unit 63 according to the second embodiment 63 High voltage detection unit according to the second embodiment 64 Decode unit 65 Read / write signal generation unit of the second embodiment 66 Break detection unit of the second embodiment 67 AND circuit 68 Inverter 69 FLPMC register of the second embodiment 70 Latch 71 AND circuit 72 AND circuit 73 Tristate Buffer 74 Tri-state buffer 80 Address data bus 81 Output signal of decoding section 81 82 Output signal of mode detecting section 62 83 Read signal output of read / write signal generating section 65 84 Write signal output of read / write signal generating section 65 85 Break Output signal 86 of detection section 66 and output of AND67 Force signal 87 Output signal of high voltage detector 63 88 Output signal of inverter 68 89 Output signal of latch 70 Output signal of AND71 91 Output signal of AND72 100 Conventional in-circuit emulator 101 Conventional emulation section 102 Conventional example Peripheral evaluation chip (flash microcomputer) 103 Mode pull-in section 110 Conventional reset terminal 111 Conventional VPP / MODE terminal 112 Conventional mode detection section 113 Conventional high voltage detection section 114 Conventional decoding section 115 Conventional read / Write signal generator 116 Tristate buffer 117 FLPMC register 120 of conventional example 120 VPP signal 121 Output signal of mode pull-in unit 103 122 Address data bus 123 Output signal of decode unit 114 124 Read The output signal of the read signal output 125 high voltage detection unit 113 of the write signal generator 115

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-28665 (JP, A) JP-A-4-77883 (JP, A) JP-A-63-76023 (JP, A) 182198 (JP, A) JP-A-5-46430 (JP, A) JP-A-2-77848 (JP, A) JP-A 8-328889 (JP, A) JP-A 8-147186 (JP, A) JP-A-2000-222199 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 11/22-11/34

Claims (2)

(57) [Claims] 1. Necessary for rewriting flash memory
Of a predetermined level indicating a state where an extremely high voltage is applied.
Register that stores the data in the VPP bit in advance.
And in the emulation mode, by the boot program
The VPP bit of the register can be read
Micro-computer for engineering simulation, characterized in that that. 2. The flash memory according to claim 1, wherein said VPP bit can be written only in a break state, and emulation of flash memory self-writing is enabled by setting said VPP bit to "1" or "0" in said break state. The microcomputer for emulation according to claim 1 .