JPH07109589B2 - Instruction processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention relates to an information processing apparatus in which an arithmetic processing unit for executing various data processing by controlling a decoding circuit for decoding an instruction code is integrated on a single semiconductor substrate. Command processing method.

[Conventional technology]

Recently, information processing devices such as personal computers and office computers are widely used not only in companies but also in general households. These information processing devices have a wide range of use, and the software accompanying them has been increasing, and the number is now huge.

Along with the increase in software, information processing equipment is also being improved in performance and speed along with user demand.

However, since new models are being commercialized one after another, it is the current situation that the information processing devices commercialized as the latest models are soon obsolete.

A lot of software is prepared for the conventional model (hereinafter referred to as the lower model), but the instruction code of the lower model is
It is completely different from the instruction code of the latest model (hereinafter referred to as upper model). The compatibility between the latest high-end model software and the conventional low-end model software has become a problem.

FIG. 8 is a block diagram of a conventional information processing device. CPU801
Is a microcomputer that executes the instruction set of the higher model. The memory 802 stores programs to be executed and processing data, and is connected to the CPU 801 and the input / output device 803 by a bus.

Even if the software for the lower model is executed by the device having the above-mentioned configuration, the CPU 801 cannot interpret the instruction code of the higher model and perform the correct processing.

It is also impossible to ignore this huge number of conventional software for lower-class models because it cannot be used for higher-class models. So, as the method of using the software for the lower model on the higher model so far, firstly, the source program of the software for the lower model is rewritten for the higher model and used on the higher model, and second, for the upper model. There was a way to create completely new software with instructions.

However, the first method has a problem in that it takes a lot of time to rewrite software for all lower models currently used for higher models. In addition, the second method is the same as before so as to newly create as much software as conventional software, or
There is a problem that it takes more man-hours and costs. In other words, the above two methods cannot be used now that the number of softwares for low-end models has become huge. Therefore, conventionally, an information device 900 having a configuration as shown in FIG. 9 has been considered.

Next, the configuration and operation of the information processing apparatus 900 will be described with reference to FIG.

FIG. 9 shows a microcomputer 90 that executes the instruction set of a higher model.
1 is a block diagram of an information processing apparatus 900 equipped with both 1 and a microcomputer 902 that executes a lower model instruction set. FIG. In FIG. 9, a microcomputer 901 that executes the instruction set of the higher model and a microcomputer 902 that executes the instruction set of the lower model
Are connected to the emulation controller 903.
When executing software for higher-level models, the address bus 905 and data bus 906 under the control of the emulation control unit 903 execute a microcomputer 901 that executes the instruction set of the higher-level model.
And executes the program for the higher-level model in the memory 904. When executing the software for the lower model, the address bus 905 and the data bus 906 are connected to the microcomputer 902 that executes the instruction set of the lower model under the control of the emulation controller 903, and the program for the lower model in the memory 904 is executed. To execute. In this way, it is possible to execute software for both lower and upper models.

[Problems to be solved by the invention]

The above-described conventional information processing apparatus is equipped with two microcomputers, one for executing the instruction code of the higher-order model and the other for executing the instruction code of the lower-order model, which has the drawback of increasing the system scale of the information processing apparatus. . Along with that, there is a drawback that the price becomes expensive. In addition, the fact that two microcomputers are installed means that when a microcomputer for executing instruction code of a lower model is used, another microcomputer for executing instruction code of a higher model is not used, When using the instruction code execution microcomputer, the other subordinate model instruction code execution microcomputer is not used, so only one of the microcomputers is used at any one time, so the hardware is wasted. It has the drawback of becoming

[Means for solving problems]

An information processing apparatus according to the present invention integrates an arithmetic processing unit that executes various data processes on a single semiconductor substrate by controlling a decoding circuit that decodes a first instruction code group stored in a program storage unit. In the semiconductor integrated circuit, a queue storing means for storing a plurality of first instruction code groups and a plurality of second instruction code groups and a queue for storing the first instruction code groups and second instruction code groups in the program storage means An instruction read means for sending to the storage means, an execution means for executing the first instruction code group, and an instruction code conversion storage means for generating the first instruction code group from the second instruction code group,
Storing processing of the first instruction code group and the second instruction code group in the program storage means by the instruction reading means to the queue storage means and the second instruction code to the first instruction code by the instruction code conversion storage means The conversion processing and the execution processing of the first instruction code by the execution means are executed in parallel.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an information processing apparatus according to the present invention. The information processing apparatus 100 has two modes. One is a mode for executing an instruction for a higher model (hereinafter referred to as a native mode) and the other is a mode for processing as an instruction for a lower model (hereinafter referred to as an emulation mode). ). The microcomputer 101 of the information processing apparatus 100 shown in FIG. 1 has both a function of executing an instruction set of a lower model (hereinafter referred to as an emulation function) and a function of executing an original instruction set. Microcomputer
101 includes an execution unit 102, an input / output device 103, an instruction code selector 104, a code conversion memory 105, a QUEUE 106, and a fetch unit 107. The QUEUE 106 can store a plurality of instructions, and when read out, the instructions are sent to the internal database 111 one instruction at a time in the written order. From the QUEUE 106, a QRDY signal 109 and a QFULL signal 110, which are status signals of the QUEUE 106, are transmitted. QRDY signal 109
Has been sent to the execution unit 102 and the fetch unit 107, and indicates whether or not there is an instruction code to be processed in the QUEUE 106. If there is an instruction code to process, it becomes active level "1". The QFULL signal 110 has been sent to the fetch unit 107 and indicates whether or not there is still room in the QUEUE 106 to write the instruction code. If the QUEUE 106 is full and the instruction code cannot be written, the active level becomes "1". If the QUEUE 106 is not used, the information processing apparatus operates as shown in FIG. 4, and the execution unit 102 cannot read the next instruction code from the memory 108 until the execution of the instruction code is completed. , At any given time, only one of fetch and execute can be performed. If there is QUEUE 106, even if execution unit 102 is executing the instruction code, it is fetched from memory 108 by the instruction of fetch unit 107 and stored in QUEUE 106. QUEUE if QRDY signal 109 is active level "1"
Since the instruction codes are sequentially sent from 106, when the previous instruction code is fetched by the execution unit 102, the next instruction has already been sent from the QUEUE to the internal data bus 111. Therefore, as shown in FIG. 5, fetch and execution are performed in parallel, and the processing time is shortened as compared with the case in which there is no QUEUE in FIG.

The fetch unit 107 receives the QRDY signal 109 and the QFULL 110 from the QUEUE 106 and controls the writing of the instruction from the memory 108 to the QUEUE 106. QFULL signal 110 is inactive level "0", QRDY signal 109 is active level "1"
If so, QUEUE106 still has room to write instructions,
QFULL signal 110 is inactive level “0”, QRDY signal
If 109 is also the inactive level “0”, the QUEUE 106 does not contain the instruction to process, so the fetch unit 10
Address information is transmitted from 7 to the internal address 113 and received by the memory 108 via the external address bus 114. Then, the instruction code is sent from the memory 108, written in the QUEUE 106 via the external data bus 112, and stored. When QUEUE 106 becomes full, QFULL signal 110 becomes active level 1 and fetch unit 107
Stop sending address information. When QFULL signal 110 becomes inactive level “0”, QUEUE from memory 108 again
The instruction code is written to 106.

The code conversion memory 105 stores a code conversion table that converts an instruction code of a lower model into an instruction code of a higher model.

The instruction code selector 104 selects either the instruction code on the internal data bus 111 or the converted instruction code in the code conversion memory 105, and sends it to the execution unit 102.

The memory 108 stores a program executed by the microcomputer 101 in a native mode, a program executed in an emulation mode, and processing data.

In the execution unit 102, a program counter (P
115), program status word (below)
A PSW) 116 and a register group 117 are included.

The PSW 116 is provided with a mode setting flip-flop 118 that sets the native mode and the emulation mode. Besides, a Z flag, a carry flag and the like are also included, but they are not shown in the figure. When the mode setting flip-flop 118 is "1", the single-chip microcomputer 101 is in the native mode, and the fetched instruction code is interpreted and executed as the instruction code for the higher model. When the mode setting flip-flop 118 is "0", the single chip microcomputer 101 enters the emulation mode and processes the fetched instruction code as an instruction code for a lower model.

The instruction processing executed by the execution unit 102 will be described below with reference to the flowchart of FIG. MOV is a transfer instruction that transfers data between registers and registers, between registers and memory, or directly transfers data to registers.
ADD, which directly transfers data to the memory, is an add instruction, register plus register, register plus memory,
The memory plus register, the register plus data, and the memory plus data are processed, and the calculation result is stored in the register or the memory. SUB is a subtraction instruction, processes register minus register, register minus memory, memory minus register, register minus data, memory minus data, and stores the calculation result in the register or memory. INA, n is an input / output instruction that transfers the data stored in the address n of the input / output device 103 designated by the second operand to the accumulator A. OUTA, n
Is an input / output instruction, and transfers the contents of the accumulator A to the address n of the input / output device 103 specified by the second operand. INT is an interrupt instruction.
And PSW116 are saved in the stack area and branched to a predetermined interrupt vector. Then, the mode setting flip-flop 118 in the PSW 116 is forcibly set to enter the native mode. The RET1 instruction is a return instruction to the main program, and when this instruction is executed, the information of PC and PSW before the interrupt instruction saved in the stack area is restored, and it returns to the main program again.

Next, the operation of the information processing device 100 will be described. This information processing apparatus 100 uses the QUEUE 106, so the execution unit 102
Is executing the instruction code, the fetch unit 10
Fetching from the memory 108 is performed according to the instruction of 7, and QUEUE106
Stored in. If the QRDY signal 109 is the active level "1", the instruction code is sent from the QUEUE 106 one after another. Therefore, when the previous instruction code is fetched by the execution unit 102, the next instruction is already sent from the QUEUE 106 to the internal data bus 11.
Has been sent to 1. Up to this point, the operation is common to both the native mode and the emulation mode. The subsequent operation will be described separately in the native mode and the emulation mode.

First, the case of the native mode will be described. The instruction code on the internal data bus 111 is the instruction code of the higher model. Since the execution unit 102 is operating in the native mode, the instruction code selector 104 uses the internal data bus 1
11 Select the instruction code above and output it to the execution unit 102. The execution unit 102 decodes this instruction code and processes each instruction described in FIG. At this time,
The next instruction code has already been output on the internal data bus 111 and is waiting for the processing of the previous instruction code to finish. Thus, as shown in FIG. 5, the instruction code is fetched and the instruction code is executed in parallel, so that the processing time is shortened as compared with the case without the QUEUE in FIG.

Next, the case of the emulation mode will be described. The instruction code on the internal data bus 111 is an instruction code of a lower model. The instruction code of the lower model is the code conversion memory.
It is sent to 105 and converted into the instruction code of the higher model by the code conversion table in the code conversion memory 105. That is, the code conversion memory 105, when the instruction code of the MOV instruction for the lower model is input, converts it to the instruction code of the MOV instruction for the upper model that performs the same processing as the MOV instruction for the lower model, and similarly, the ADD instruction for the lower model is converted. When the instruction code is input, it is converted to the instruction code of the ADD instruction for the upper model that performs the same processing as the ADD instruction for the lower model. Because the execution unit 102 is operating in emulation mode, the instruction code selector 10
Reference numeral 4 selects the instruction code of the code conversion memory 105, and outputs the instruction code converted to the higher model instruction to the execution unit 102. The execution unit 102 decodes this instruction code and executes transfer if MOV, addition if ADD, and subtraction if SUB. The operation of the execution unit 102 after converting the instruction code is the same as that described with reference to FIG. At this time, the following instruction code has already been converted. As described above, as shown in FIG. 7, the instruction code is fetched, the instruction code is converted, and the instruction code is executed in parallel, so that the processing time is shortened as compared with the case without the QUEUE in FIG. It

〔The invention's effect〕

As described above, the present invention has the function of executing the instruction set of the lower model and the function of executing the instruction set of the higher model, and therefore has the advantage of being able to execute both the software for the lower model and the software for the higher model. is there.

Further, since the information processing apparatus according to the present invention uses the instruction code conversion memory, only the microcomputer having the function of executing the instruction set of the higher model without installing two microcomputers can process the instructions of the lower model. Because it can be done, it is possible to use 2 of the microcomputer for the lower model and the microcomputer for the higher model until now.
Can be made smaller than the information processing device that used
There is also an advantage that the cost can be reduced.

Further, since the information processing apparatus according to the present invention uses QUEUE, the instruction code is fetched and the instruction code is executed in parallel instead of reading the instruction code from the memory each time one instruction is processed. Therefore, there is an advantage that the program processing speed is fast.

[Brief description of drawings]

FIG. 1 is a block diagram of an information processing apparatus according to the present invention, FIG. 2 is a flowchart in a native mode, FIG. 3 is a flowchart in an emulation mode, and FIG. 4 is QUEU.
Time chart when E is not used, FIG. 5 is a time chart when QUEUE is used, FIG. 6 is a time chart when QUEUE is not used in the information processing apparatus according to the present invention, and FIG. 7 is information according to the present invention. QU in processing equipment
FIG. 8 is a block diagram of a higher-order model to which the conventional emulation function is not added, and FIG. 9 is a block diagram of a higher-order model with a conventional lower-model emulation function. 102 ... Execution unit, 103 ... Input / output device, 104 ... Instruction code selector, 105 ... Code conversion memory, 106 ...
QUEUE, 107 …… Fetch unit, 108 …… Memory, 109
…… QRDY signal, 110 …… QFULL signal, 111 …… Internal data bus, 112 …… External data bus, 113 …… Internal address bus, 114 …… External address bus, 115 …… PC, 116 …… PS
W, 117 ... Register, 118 ... Mode setting flip-flop, 801 ... CPU, 802 ... Memory, 803 ... I / O device, 901 ... High-end model microcomputer, 902 ... Low-end model microcomputer, 903 ... … Emulation controller, 904 …… Memory, 905 …… Address bus, 906 …… Data bus.

Continuation of the front page (56) References JP 59-8058 (JP, A) JP 59-99552 (JP, A) JP 51-32146 (JP, A) JP 54-30752 (JP , A) Nikkei Electronics, April 23, 1984, Nikkei McGraw-Hill, P. 100-105

Claims (1)

[Claims] 1. An arithmetic processing unit for executing various data processing is integrated on a single semiconductor substrate under the control of a decoding circuit for decoding a first instruction code group for a higher model stored in a program storage means. In the semiconductor integrated circuit described above, storage means for storing a plurality of first instruction code groups for the higher-order model and second instruction code groups for the lower-order model, and the first instruction code group in the program storage means. Instruction reading means for sending the second instruction code group to the storage means, execution means for executing the first instruction code group, and generation of the first instruction code group from the second instruction code group. If the instruction code conversion means for executing the instruction code conversion means and the instruction code group sent from the storage means are the first instruction code group for the higher-order model, the first instruction code group for the higher-order model is selected and stored. hand When the output instruction code group is the second instruction code group from the generated by the instruction code conversion means said second instruction code first
Selecting means for selecting and sending the instruction code group to the executing means, and when the instruction code group in the program storing means is the second instruction code group, the program storing means by the instruction reading means. Processing of storing the second instruction code group in the storage means, conversion processing of the second instruction code to the first instruction code by the instruction code conversion means, and the first processing by the execution means. If the instruction code group in the program storage means is the first instruction code group, the first instruction code in the program storage means by the instruction reading means is executed in parallel. Instruction processing for storing the instruction code group of 1) in the storage means and the execution processing of the first instruction code by the execution means in parallel. Formula.