JP2754786B2 - Information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus provided with a microcomputer, and more particularly to an information processing apparatus that performs data processing of security information such as billing information.

[Conventional technology]

Information processing systems using microcomputers have rapidly developed and spread, and are being used in various fields. However, in an information processing system using a general-purpose microcomputer supplied to the market, for example, the following problems regarding information security occur.

(Problem Example 1) The instruction code group of a general-purpose microcomputer supplied to the general market is usually made public, and the program memory of an information processing system using such a microcomputer is stored in a third party (for example, using the system). Person) can decipher and understand the entire system. And if a third party modifies the program,
It is possible to destroy or change by intentionally inputting data or commands.

In addition, since the program can be decoded, even if the data generated from the information processing system includes a check word (check digit), it knows the check word generation algorithm and directly changes the check word of the data. It is also possible.

Therefore, when the generated data is, for example, billing information or signal information, the profit on the side that should use the information may be impaired.

(Problem Example 2) If a third party can obtain or reproduce all components constituting an information processing system including a general-purpose microcomputer, the third party stores the information processing system, particularly in a program memory. Then, it is possible to copy the software including the software used in the system. If the duplication is performed without permission, the interests of the right holder of the information processing system may be impaired.

As a means for solving the above-mentioned problems relating to information security, it is effective to use a method in which the information stored in the program memory is decrypted or copied by a third party so that the information cannot be used. As one of the realization methods, an instruction code (hereinafter, referred to as an instruction code that can be determined and executed by an internal instruction decode circuit by a microcomputer).
Shown as normal code. ), Another code (hereinafter, referred to as a conversion code) corresponding to the conversion code is newly set, and a program described by the conversion code is stored in the program memory.

FIG. 8 is a diagram showing the configuration of this type of conventional information processing apparatus, and its operation will be described below.

The microcomputer 1 is a general-purpose microprocessor that decodes a predetermined instruction code and executes various data processing, and a program memory 2 and a data memory 3 are connected via an address bus 4 and a data bus 5, respectively. . In particular, the output of the program memory 2 is
Is connected to the data bus 5 via the.

The program memory 2 stores a program described by a conversion code executed by the microcomputer 1.
The data memory 3 stores various data used in the program processing of the microcomputer 1. The encoder 6 is a hardware logic that encodes the conversion code into a normal code of the microcomputer 1, and uses, for example, a PLA (programmable logic array).

The microcomputer 1 supplies address information to the program memory 2 via the address bus 4 based on an internal PC (program counter) value (not shown) and reads a conversion code. The conversion code is input to the encoder 6 and outputs the corresponding code to the data bus 5. The microcomputer 1 fetches this code as a normal code, and executes a predetermined data processing.

The above-described series of operations are repeated to sequentially perform the program processing. However, the conversion code stored in the program memory 2 is a code that is not disclosed to a third party, and the third party cannot know the relationship with the normal code. . Therefore, falsification and use of various data generated by the program is impossible except by accident. Even if the contents of the program memory 2 are duplicated, the present information processing system cannot be duplicated unless the encoder 6 is obtained.

[Problems to be solved by the invention]

In such a situation, in the above-described conventional information processing system, the output data of the program memory 2 is always converted via the encoder 6, so that all the programs have to be described in conversion codes. However, since the conversion code at this time is usually defined for each requester of the system, existing program development tools such as general-purpose assemblers and compilers cannot be used. Therefore, while programs have been increasing in scale with the sophistication and complexity of systems, the development of programs using converted codes has become extremely inefficient.

Recently, along with the sophistication of the information processing society,
On the other hand, unauthorized use of information is becoming increasingly malicious,
Also in the conventional information processing system described above, since the output of the encoder 6 is connected to the microcomputer 1 via the external data bus 5, information output by inputting various patterns to the encoder 6 is externally observed. And reproduce the encoder itself to duplicate the entire system, or monitor the output of the encoder 6 and actually execute the program while monitoring the output of the encoder 6 to analyze the total program processing. It did not satisfy the request.

SUMMARY OF THE INVENTION The present invention has been made in order to improve such problems in program development and security in the conventional information processing system, and effectively utilizes hardware resources of existing microcomputers. It is an object of the present invention to provide an information processing apparatus that is highly flexible and cannot be used illegally by a third party.

[Means for solving the problem]

The information processing apparatus of the present invention is described by an arithmetic processing unit that executes various data processing in response to an input instruction code, and a first instruction code group that is a code that can be directly executed by the arithmetic processing unit. A first program, a program memory for storing a second program described by a second code group that is a code that cannot be executed by the arithmetic processing unit as it is, and decodes the first instruction code group. A decoding circuit that generates first control information based on a decoding result; and an address control unit that receives the second instruction code group and the first control information and generates address information based on the input information. Instruction code conversion storage means for selecting and generating the first instruction code group corresponding one-to-one from the second instruction code group based on the address information; A first data bus that uses the first instruction code group read from the RAM memory as transfer data, and a second data bus that uses the first instruction code group output from the instruction code conversion storage unit as transfer data And a selector for selecting one of the first data bus and the second data bus and connecting to the decoding circuit, wherein the first program Or the instruction code group read from the program memory to execute while dynamically switching any one of the second programs is the first instruction code or the second instruction code group. By generating and supplying the second control information for specifying the selector to the selector, the mode switching means for specifying the selection condition of the selector is provided. And characterized in that it.

The mode switching means, for example, decodes a mode switching instruction code stored in a program memory by a decoding circuit, or outputs second control information that specifies selection conditions of a selector based on an interrupt request signal from an external terminal. To generate.

Also, the microcomputer stores code conversion information, which is stored in the instruction code conversion storage means and indicates the correspondence between the first instruction code group and the second instruction code group, and outputs the operation result to an external terminal. Has a test means for deriving it.

As described above, the information processing apparatus of the present invention uses a microcomputer having a function of converting an input conversion code into an instruction code that can be internally executed by a code conversion table stored in a built-in memory. Thus, the conversion code is directly input to the microcomputer, and the mode for executing the instruction based on the normal code and the mode for executing the instruction based on the conversion code are switched.

〔Example〕

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an internal configuration of an information processing apparatus according to an embodiment of the present invention.
Reference numeral 100 controls the entire system, and a program memory 200 and a data memory 300 are mutually connected via an address bus 400 and a data bus 500, respectively. The program memory 200 stores a program executed by the microcomputer 100 and described by a normal code and a program described by a conversion code. In the program, a normal mode command instruction 201 for transitioning to a mode for executing a normal code instruction (hereinafter, referred to as a normal mode) is provided.
And a conversion code mode designation instruction 202 for transitioning to a mode for executing an instruction based on the conversion code (hereinafter, referred to as a conversion code mode). Data memory 3
00 stores various data used in the program processing of the microcomputer 100.

FIG. 2 is a block diagram of the microcomputer 100. The arithmetic processing 101, the conversion memory 102, the address control circuit 103,
The conversion memory 102 includes an internal address bus 104, an address bus terminal 105, an internal data bus 106, a data bus terminal 107, a selector 110, and an RS flip-flop (hereinafter, referred to as F / F) 113. Is realized by a mask ROM.

The arithmetic processing unit 101 includes an instruction decode circuit 108, a timing control circuit (not shown), an arithmetic and logic operation circuit, a general-purpose register, and a program counter. Arithmetic processing unit 101
Performs predetermined data processing according to the instruction code output from the selector 110. First, the instruction decoding circuit 108 decodes the input instruction code. Subsequently, the timing control circuit controls the output timing of various control signals (not shown) according to the decoding result,
The arithmetic logic circuit, general-purpose registers, and program counter are controlled as necessary. When the instruction decoding circuit 108 determines the first byte instruction code of the 2-byte length instruction in its own decoding processing, the instruction decoding circuit 108 switches the address in the conversion memory 102 to refer to the next second byte instruction code. The designation signal 109 is output to the address control circuit 103. Also, F / F set signal 1 that specifies the normal mode
11 and F / F reset signal 112 that specifies the conversion code mode
Is output to F / F113. The internal address bus 104 connects the address bus terminal 105 to the arithmetic processing unit 101, and transfers the address information processed by the arithmetic processing unit 101 to the address bus terminal 105.
To the address bus 400. Internal data bus 106
Connects the data bus terminal 107, the arithmetic processing unit 101, the address control circuit 103, and the selector 110, and is used for mutual data transfer. The conversion memory 102 stores an instruction code conversion table, and the instruction code read from the data bus terminal 107 onto the internal data bus 106 and the page designation signal 109 are used to generate a read address.
The output of the conversion memory 102 is connected to the selector 110. Since the conversion memory 102 is integrated in the LSI and has a small electric capacity and a small signal delay, it can operate with low power consumption and high speed, and is very suitable for high-speed conversion of instruction codes. The address control circuit 103 generates a read address of the conversion memory 102 based on the page designation signal 109 and the instruction code from the internal data bus 106. F / F
113 is a normal mode designation instruction 201 in an instruction decode circuit 108.
Is set to “1” by the F / F set signal 111 generated when the conversion code mode designation instruction 202 is determined, and is reset to “0” by the F / F reset signal 112 generated when the conversion code mode designation instruction 202 is determined. Also, it is set to “1” by the system reset signal 114. The selector 110 receives the input of the internal data bus 106 and the output of the conversion memory 102, and connects the output of the internal data bus 106 to the instruction decode circuit 108 when the F / F 113 is "1".
When the F / F 113 is "0", the output of the conversion memory 102 is connected to the instruction decode circuit 108.

FIG. 3 is a diagram showing an address and an internal configuration of the conversion memory 102. The address is composed of 9 bits, and a bit 8 (page specification field 3-1) includes a page specification signal.
109 is connected. The internal data bus 106 is connected to bits 7 to 0 (instruction code field 3-2). In the memory, a table area of 256 bytes is secured for two pages, page 0 and page 1, and normal codes corresponding to the conversion codes are sequentially assigned, each using an 8-bit conversion code as an address.

FIG. 4 is a diagram showing the operation principle of instruction code conversion. FIG. 4 (a) shows the operation principle of the instruction code conversion when the instruction code length is 1 byte, and FIG. 4 (b)
Shows the operation principle of instruction code conversion when the instruction code length is 2 bytes.

The block diagram of FIG. 2 and the conversion memory of FIG.
The operation of converting an instruction code according to the present invention will be described with reference to the block diagram of FIG. 102 and the operation principle diagram of the instruction code conversion of FIG.

Immediately after a system reset or by the instruction decode processing in the instruction decode
And when the F / F set signal 111 becomes active, the F / F
F113 is set to "1", and thereafter, the instruction decode circuit 108
The normal code on the internal data bus 106 is selected by the selector 110 for the instruction code input to the, and the instruction is executed in the normal mode. On the other hand, when the conversion code mode designation instruction 202 is determined by the instruction decoding process in the instruction decoding circuit 108 and the F / F reset signal 112 becomes active, the F / F 113
Is reset to "0", and the instruction code based on the output of the conversion memory 102 is selected by the selector 110 as the instruction code subsequently input to the instruction decode circuit 108, and the instruction is executed in the conversion code mode.

 Next, the operation in the conversion code mode will be described below.

The address control circuit 103 generates a 9-bit read address of the conversion memory 102 shown in FIG. 3 from the page designation signal 109 and the conversion code on the internal data bus 106.
Here, the correspondence between the conversion code and the normal code degree will be described. Generally, the instruction code length is 1 byte, 2 bytes, 3
Although various configurations are made up of individual microcomputers such as bytes, here, the case of 1 byte and 2 bytes will be taken up and extended. The case where the instruction code length is 1 byte will be described with reference to the principle diagram of FIG. 4 (a) and the block diagram of FIG. In this case, the page designation signal 109 is always inactive, the page 0 is selected in a state where the page designation field 3-1 is "0", the conversion code is supplied to the conversion memory 102 as address information, and the corresponding normal code is output. Is read. Further, the case where the instruction code length is 2 bytes will be described with reference to the principle diagram of FIG. 4B and the block diagram of FIG. In the first byte of the conversion code, the page designation signal
Reference numeral 109 denotes an inactive state. When the page designation field 3-1 is "0", page 0 is selected, and the normal code of the first byte is read (step 1). When the instruction decoding circuit 108 determines that the converted instruction code is the first byte of the two-byte instruction, the instruction decoding circuit 108
109 is activated, and the page designation field 3-1 becomes "1". The page 1 is selected by the address control circuit 103, and the second byte normal code is read from the conversion memory 102 by the second byte conversion code (step 2).

As described above, the conversion code of 1-byte length or 2-byte length is converted into a normal code of 1-byte length or 2-byte length, and the instruction is executed.

In this embodiment, the conversion code is converted into the normal code of the arithmetic processing unit 101 by the conversion memory 102 which is a mask ROM, and the output of the conversion memory 102 is only connected to the selector 110. Cannot be read out through the data bus 500 to the outside. Therefore, there is no possibility that a conversion rule for converting the conversion code written in the conversion memory 102 into a normal code will be known to a third party.

In the present embodiment, as an example of the conversion of the instruction code,
The case where the instruction code length is 1 byte and 2 bytes has been described. However, regarding the conversion of other byte instructions, the address configuration shown in FIG. Thus, it is possible to convert the instruction code based on the same principle.

Next, a second embodiment of the present invention will be described with reference to the drawings. The second embodiment is similar to the selector 11 of the first embodiment.
A signal designating a selection condition of 0 is generated based on a signal input from an external terminal.

FIG. 5 is a block diagram of an information processing apparatus according to a second embodiment of the present invention. Except for having a function of inputting a signal from an external terminal 700 to a microcomputer 600, the configuration and operation are the same. Is the same as the information processing apparatus in FIG. 1 of the first embodiment.

An external terminal 700 has a data processing request signal from a host computer to which the information processing apparatus is connected online.
800 will be supplied.

FIG. 6 is a block diagram of a microcomputer 600 in the information processing apparatus according to the second embodiment of the present invention.
The configuration and operation of the arithmetic processing unit 101, the conversion memory 102, the address control circuit 103, the internal address bus 104, the address bus terminal 105, the internal data bus 106 and the data bus terminal 107 are shown in FIG. Microcomputer 100
And the detailed description is omitted.

The instruction decode circuit 108 outputs the same page designation signal 109 as the page designation signal 109 of the instruction decode circuit 108 in the first embodiment to the address control circuit 103. The interrupt control circuit 604 receives the interrupt request signal 602 from the mode switching terminal 603 connected to the external terminal 700,
When the active state is received, the process branches to a predetermined interrupt vector, and the mode switching signal 605 is activated. In addition, the mode switching signal 605 is made inactive when returning from a series of interrupt processing. The mode switching signal 605 is supplied to the selector 601. The selector 601 receives the internal data bus 106 and the output of the conversion memory 102 as inputs, and connects the output of the internal data bus 106 to the instruction decode circuit 108 when the mode switching signal 605 is inactive. The output of the time conversion memory 102 is connected to the instruction decode circuit 108. The program memory 200 stores a main processing program based on normal code and a series of program processing based on a conversion code from a conversion destination address of a conversion code of an interrupt vector. When there is a data processing request 800 from the host computer, the mode shifts to the conversion code mode under the control of the interrupt control circuit 604 to execute the instruction.

As described above, in the present embodiment, the mode can be switched by the terminal signal, and at the same time, similarly to the first embodiment, the conversion rule for converting the conversion code written in the conversion memory 102 into the normal code is defined as the first rule. There is no possibility to be known to the three.

Further, in the above-described information processing apparatus of the present invention, the contents of the conversion memory 102 can be externally tested by a third method.
An example will be described. In the third embodiment, in the test mode of the LSI, a result obtained by subjecting the contents of the instruction code conversion table stored in the conversion memory 102 to predetermined arithmetic processing can be read out to the outside through the data bus terminal 107. Things.

FIG. 7 is a block diagram of a microcomputer 900 in the information processing apparatus according to the third embodiment of the present invention. The arithmetic processing unit 101, the conversion memory 102, the internal address bus 104, the address bus terminal 105, the internal data bus 106, Instruction decode circuit 108
The configuration and operation of the selector 110 are the same as those of the microcomputer 100 of the first embodiment and the microcomputer 600 of the second embodiment, and a detailed description thereof will be omitted.

The test circuit 901 receives the output of the conversion memory 102 as an input,
An internal gate circuit generates data in which the logical values of all bits of the input data are inverted. Output is internal data bus
Connected to 106.

The address control circuit 902 receives the internal address bus 104 in addition to the internal data bus 106 in the address control circuit 103 of the first embodiment, and outputs the address information from the internal address bus 104 to the conversion memory 102 in the test mode. I do.

With the above configuration, in the test mode, the conversion memory 10
2 is mapped in the memory space of the microcomputer 900 and can be read by a data access instruction such as a data transfer instruction.

Hereinafter, the operation of the ROM code test of the conversion memory 102 in the test mode will be described.

The arithmetic processing unit 101 fetches a read instruction for the lowest address to which the conversion memory 102 is mapped,
After decoding, the address information of the conversion memory 102 is output to the address control circuit 902 via the internal address bus 104. The address information is output from the address control circuit 902 to the conversion memory 102, and ROM code data corresponding to the address information is read. The data read here is
This is information of the instruction code conversion table itself. When the read data is input to the test circuit 901, all bits are inverted and output to the internal data bus 106, and the arithmetic processing unit 101
The data is read into an internal general-purpose register (not shown).

Next, when the arithmetic processing unit 101 fetches and decodes a write instruction to the external memory space, the contents of the general-purpose register are transferred to the data bus terminal 1 via the internal address bus 104.
Output to 07.

Subsequently, while sequentially incrementing the address of the conversion memory 102 by +1 to the highest address to which the conversion memory 102 is mapped, the above-described processing of the data read operation and the external write operation of the conversion memory 102 is repeated, and
The test is performed by sweeping out inverted data for the M code.

Here, since the configuration of the inverting gate circuit in the test circuit 901 is not disclosed to a third party, it is impossible to decode the contents of the instruction code conversion table of the conversion memory 102 from the information swept out from the data bus terminal. It is.

In this embodiment, for simplicity, an example has been described in which the logic of all bits of data is inverted.
In, by changing the bit position of data, or using a decoder, ROM, etc., more complicated and advanced data conversion at the time of ROM code sweeping out in the test mode is possible.

〔The invention's effect〕

As described above, normally, when developing a program, a tool such as a high-level language compiler or assembler is used to efficiently manufacture and debug, but a general-purpose tool cannot generate a conversion code. Therefore, only the minimum processing that should be prevented from being decoded by a third party needs to be described in the conversion code. However, according to the information processing apparatus of the present invention, a mode in which an instruction is executed based on the conversion code and a tool can be used. Since a function for dynamically switching between a mode in which instructions are executed based on a normal code and a mode in which the program is executed is provided, most of the program can be developed using a tool and the program is highly flexible.

In addition, since a conversion code that is not disclosed to a third party is input, converted into a normal code that can be executed by a conversion memory integrated in the microcomputer, and the instruction is executed, the contents of the conversion memory, which is the core of the conversion rule, are directly Cannot read outside. Also, during LSI testing, they are converted to special codes and output. Therefore, the third party cannot know by any means the correspondence between the input converted code and the actually executed normal code, and decrypts the program written with the converted code to illegally use the processed data. It is not possible. For the same reason, it is practically impossible for a third party to duplicate a microcomputer that receives the same conversion code and executes the instruction. Therefore, the information processing apparatus of the present invention can provide a function optimal for information security.

Further, the microcomputer used in the information processing apparatus of the present invention can easily set an arbitrary conversion code only by rewriting the contents of the conversion memory. Therefore, even when setting different conversion codes for each of the OEM's individual requirements, compared with the case of newly designing and manufacturing a microcomputer having a new individual instruction code, much less man-hour and cost are required for a short period of time. For example, an information processing apparatus having excellent versatility can be provided by utilizing existing hardware resources, and the practical effect of the present invention is extremely high.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of an information processing apparatus according to the present invention, and FIG. 2 is a microcomputer 10 of the first embodiment.
FIG. 3 is a block diagram of the conversion memory 102 of the first embodiment.
FIG. 4 is a principle diagram of instruction code conversion of the first embodiment, FIG. 5 is a block diagram of a second embodiment of the information processing apparatus of the present invention, and FIG. FIG. 7 is a block diagram of a microcomputer 600 of the second embodiment, FIG. 7 is a block diagram of a microcomputer 900 of the third embodiment, and FIG. 8 is a block diagram of a conventional information processing apparatus. 105: Address bus terminal, 107: Data bus terminal, 10
9… Page designation signal, 111… F / F set signal, 112 ……
F / F reset signal, 114 …… System reset signal, 201
…… Normal mode designation command, 202… Conversion code mode designation command, 602 …… Interrupt request signal, 603 …… Mode switching terminal, 605 …… Mode switching signal, 800 …… Data processing request signal, 901 …… Test circuit , 902... Address control circuit.

Claims (4)

(57) [Claims] An arithmetic processing unit for executing various data processing in response to an input instruction code, and a first instruction code group described by a first instruction code group, which is a code executable by the arithmetic processing unit as it is. And a program memory that stores a second program described by a second code group that is a code that cannot be executed by the arithmetic processing unit as it is, and decodes the first instruction code group, and decodes the first instruction code group. A decoding circuit that generates first control information based on the second command code group and the first control information, and an address control unit that generates address information based on the input information; Instruction code conversion storage means for selecting and generating the first instruction code group corresponding one-to-one from the second instruction code group based on the address information, and the program memory A first data bus that uses the first instruction code group read from the first transfer code as a transfer data, and a second data bus that uses the first instruction code group that is the output of the instruction code conversion storage means as the transfer data. An information processing device comprising a microcomputer having a selector for selecting one of the first data bus and the second data bus and connecting to the decoding circuit; Alternatively, the instruction code group read from the program memory to execute while dynamically switching any one of the second programs is the first instruction code or the second instruction code group. Mode switching means for specifying selection conditions for the selector by generating second control information for specifying the selector and supplying the control information to the selector. An information processing apparatus characterized by the following. 2. The method according to claim 1, wherein the mode switching means generates the second control information based on a result of decoding the mode switching instruction code stored in the program memory by the decoding circuit. The information processing apparatus according to claim 1, wherein 3. The information processing apparatus according to claim 1, wherein said mode switching means generates said second control signal based on an interrupt request signal from an external terminal. . 4. A code conversion information stored in said instruction code conversion storage means, said code conversion information indicating a correspondence relationship between said first instruction code group and said second instruction code group. And a test means for leading out to an external terminal.
Item 4. The information processing device according to Item 3.