JPS61240333A - Input and output interruption processing system - Google Patents

Abstract

PURPOSE:To reduce the overhead due to the simulation of a virtual computer program by applying a direct interruption to the virtual computer in case the virtual computer at the receiver side of an interruption request and this interruption is permitted. CONSTITUTION:The discriminating information of an interruption receiver VM is designated to a central processing unit 23 from a channel processor 24 via a signal line 10 in an input/output interruption request process to a virtual computer VM system. The discriminating information on the VM which is under execution is held in a register 11 by an input/output start instruction. A comparator 12 compares the information on the register 11 with the information sent from the line 10. When the coincidence is obtained from this comparison, the comparator 12 supplies the coincidence signal to an AND gate 14. While the interruption request signal 17 given from the processor 24 is supplied to an interruption reception circuit 13 together with the interruption reception signal held in an interruption mask register 16. When the coincidence is obtained between both signals, the circuit 13 sends an interruption permitting signal to the gate 14. Thus the gate 14 is opened and the interruption signal is applied directly to a VM area 26 of a main storage device 21 via an interruption control part 15.

Description

[Detailed Description of the Invention] [Summary] This is an input/output interrupt processing method for a virtual machine. If the virtual machine that is the interrupt request destination is running and is in a state that allows interrupts, an interrupt is generated directly to that virtual machine without going through the processing of the virtual machine control program. Provide means to do so.

[Industrial application field]

The present invention relates to an input/output interrupt processing method for an input/output processing request issued by a virtual machine in a computer system that executes a virtual machine.

In a computer system, a computer usage method in which a computer system different from the computer system (hereinafter referred to as the actual computer system) is operated virtually under the control of a virtual computer control program is a virtual computer method. known as.

In a virtual computer system, when controlling the resources of a real computer system, in order to avoid interference between multiple virtual computer systems and to convert different device addresses between the real computer and the virtual computer, it is necessary to There is a part where the execution proceeds through the virtual machine control program,
Speeding up the processing of such parts is important for the processing efficiency of the virtual machine.

[Prior art and problems to be solved by the invention] FIG. 2 is a block diagram showing an example of the configuration of a computer system.

In the figure, 1 is a main storage device, 2 is a storage control device, 3 is a central processing unit, and 4 is a channel processing device. It also relays control information between the central processing unit 3 and the channel processing unit 40.

The channel processing device 4 generally controls a plurality of channel devices connected thereunder in common, and various input/output devices are connected to each channel device.

In one type of virtual computer system, a virtual computer control program (hereinafter referred to as VM monitor) that is started in the central processing unit 3 by an interrupt set to occur at regular intervals, for example, controls the virtual computer under control. By selecting one of the computers (hereinafter referred to as VM) and passing control, execution of the VM is started.

When transferring control to a VM, the VM monitor sets identification information of the VM in a predetermined IIIJ control register of the central processing unit 3. The identification information is used by the VM monitor to identify each VM that exists in the system at the same time.
This is information (for example, a number) that is uniquely assigned to a user.

When an input/output activation instruction is read during execution of a VM, as is well known, as the execution of the input/output activation instruction, the input/output device address on the VM is transferred to the actual computer using a control table determined by the identification information of the VM. Also, the channel address word in the VM area is transferred to the channel address word area of the real computer, and from then on, the channel processing device 4 will be notified.

When the channel processing device 4 recognizes the input/output activation command,
Read the channel address word as usual and begin the I/O activation process.

An interrupt request from the channel processing device 4 to the central processing unit 3 due to the completion of an input/output operation, etc. is controlled by the interrupt control mechanism of the central processing unit 3 as an interrupt of the actual computer, so it can be handled by a known mechanism. , the input/output device address and other status information transferred from the channel processing device 4 are set in the Gyanel status word (hereinafter referred to as C8W) in a predetermined area of the main storage device 1, and the input/output device address for input/output interrupts is set. By setting the program status word (hereinafter referred to as psw) in the central processing unit 3, control is concentrated on the input/output interrupt processing routine of the VM monitor.

The corresponding routine of the VM monitor identifies the VM to which the input/output device is assigned, for example, based on the input/output device address of the interrupt request source, and if the VM is running and the VM
If the interrupt mask is in the interrupt enabled state, the V
Transfer the C8W of the actual computer to the CSW in the storage area of M, convert the input/output/device address to the input/output device address on the VM if necessary, and transfer the PSW for VM's input/output interrupt.
By setting this in the central processing unit 3, an input/output interrupt is simulated on the VM.

If the VM identified above is not running,
For example, the contents of C8W are connected to the interrupt queue, and the interrupt processing of the VM monitor is completed.

Interrupts in the interrupt queue can be accessed by the VM monitor, e.g.
If there is an interrupt to an executable VM that is scanned and loaded into the main memory when switching the VM or executing a privileged instruction to update the interrupt mask in the VM, the above procedure will be applied. The control simulates an interrupt to the VM.

According to the conventional control method described above, it is necessary to simulate the interrupt using the VM monitor every time an input/output interrupt request occurs, which is a major cause of the overhead caused by the VM monitor. Means] FIG. 1 is a block diagram showing the configuration of the present invention, and 1.2
1 is a main storage device, 22 is a storage control device, 23 is a central processing unit, and 24 is a channel processing device.

10, in the input/output interrupt request, the channel processing device 2
4 is a signal line specifying VM identification information, 11 is a register that holds identification information of the VM being executed, and a comparator 12
compares the contents of the re-identification information and outputs a matching signal.

Reference numeral 13 denotes an interrupt acceptance circuit, which outputs a decision as to whether acceptance is possible or not based on, for example, an interrupt request line 17 that displays an interrupt request for each channel device, and the contents of an interrupt mask register 16.

14 activates the interrupt control section 15 based on the AND output of the outputs of the comparator 12 and the interrupt acceptance circuit 13.

The interrupt reception unit 15 executes predetermined interrupt processing.

[Effect]

Similarly to the above, by executing the input/output activation command, the central processing unit 23 instructs the channel processing device 24 to activate the input/output operation. At this time, the V that executed the instruction
The identification information of M is sent from the register 11 to the channel processing device 2.
4 and is retained.

In response to an input/output interrupt request, the channel processing device 24 turns on the signal corresponding to the requesting channel device on the interrupt request line 17 as usual, and also sends the interrupt destination VM to the signal line 10.
Sends identification information.

The identification information of the interrupt mask register 16 and register 11 is
When the interrupt request conditions are met, the interrupt control unit 15 is activated and causes the VM being executed to generate an interrupt.

As described above, since an input/output interrupt to a running VM occurs directly without going through the VM monitor, overhead due to interrupt simulation is eliminated. In this way, there are many opportunities for input/output interrupt requests to occur in the running VM, so
The above control can improve the performance of the VM system.

〔Example〕

Identification information is set in the register 11 in FIG. 1 by the VM monitor when the VM starts executing.

Further, as is well known, the interrupt mask register 16 is used to allocate, for example, one of the control registers and control acceptance of interrupts from the channel device using bits corresponding to the channel device. Set by the VM's control program.

According to the present invention, the interrupt mask of the VM, not the actual computer, is actually held in the interrupt mask register 16 to control interrupt acceptance.

Upon generation of an interrupt request, a signal indicating the interrupt request channel device is raised on the interrupt request line 17.

The interrupt reception circuit 13 compares the signal on the interrupt request line 17 with the contents of the interrupt mask register 16, and outputs a signal to the AND gate 14 if the request channel device is in an interrupt enabled state. .

The comparator 12 uses the identification information of the register 11 and the signal line 10.
When the identification information input in the AND gate 14 is on, the AND gate 14 outputs a heon signal.
is started.

As with normal interrupts, the interrupt control unit 15 sets the CSW on the main storage device 21 based on the information transferred from the channel processing device 24, and transfers the PSW for input/output interrupts from the main storage device 21. An interrupt is executed by loading each register of the central processing unit 25.

However, in this case, the target C8W and PS
W is not those of the real computer (i.e. VM monitor),
The interrupt control unit 15 uses the address translation mechanism 25 to convert the access address so that it becomes the csw and psw of the currently executing VM, and the address is in the vM area 26 of the currently executing VM in the main storage device 21. Access C8W%psw.

Therefore, the VM's PSW is loaded and the VM's I/O interrupt handling routine is initiated, ie, a direct interrupt to the VM is made.

The address conversion mechanism 25 may be a known conversion mechanism in a virtual storage system, and the conversion is executed, for example, by adding the main memory address at the beginning of the VM area.

As a result of the above, the interrupt destination VM of the input/output interrupt request is running,
If the request source channel device is in a state that allows interrupts, the interrupt is executed directly to that VM, but the input/output interrupt is
If it is not executed as described above, for example, the interrupt information is connected to an interrupt queue similar to the conventional case described above, and the VM monitor simulates the interrupt at a later time.

For this purpose, if there is an input/output interrupt request and the above-mentioned interrupt conditions are not satisfied, the interrupt wait processing unit 27 is activated, and as in the past, the input/output interrupt request at a predetermined address in the VM monitor area is Connect this interrupt request to queue 28.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, input/output interrupts to a VM in a computer system are handled by a VM.
Since it is possible to execute directly without using a monitor,
There is a significant industrial effect in that the overhead due to interrupt simulation of the VM monitor is reduced and the performance of the 7M system is improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of the configuration of a computer system. In the figure, 1.21 is the main storage device, 2.22 is the storage control device,
3.23 is a central processing unit, 4.24 is a channel processing unit, 10 is a signal line, 11 is a register, 12 is a comparator, 13 is an interrupt reception circuit, 15 is an interrupt control unit, 16 is an interrupt mask register , 17 is an interrupt request line, 25 is an address conversion mechanism, and 27 is an interrupt wait processing unit.

Claims (1)

[Scope of Claims] In input/output interrupt request processing of a virtual computer system, an identification information specifying means (10) for specifying identification information of an interrupt destination virtual computer; displaying identification information of a virtual computer being executed; Identification information display means (11), said identification information designation means (10), and said identification information display means (
11), means (12) for comparing identification information with
12) means (13, 14, 15, 16) for generating an interrupt for the virtual computer by identifying that a match has been detected and that the virtual computer is in a state that permits the interrupt;
).