JPH01283643A - Input/output control system for virtual computer system - Google Patents

Abstract

PURPOSE:To execute the processing at high speed by dividing and allocating a subclass being a unit for controlling separately an input/output interruption request to a host program for controlling a virtual computer system and a guest program for running on the virtual computer. CONSTITUTION:An input/output interruption request to a host or a guest which is generated when the guest is running is subjected to a mask control by an input/output interruption holding bit 4, a real subclass mask 3 and a control subclass mask 2. Subsequently, the input/output interruption request to the host and the input/output interruption request to the host are processed in accordance with an input/output interruption generating condition of the host and in accordance with an input/output interruption generating condition of the guest, respectively. In such a way, an input/output interruption which is generated in the course of running of a guest program can be informed to an appropriate one of a host program or the guest program. Also, an instruction for cutting down an interruption request can also be executed directly by receiving only an interruption of the guest in the course of running of the guest program, therefore, the processing of a virtual computer system can be executed at high speed.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an input/output control method in a virtual computer system, and in particular, to processing of input/output interrupt processing of a guest program and processing of an instruction to accept a pending input/output interrupt. This paper relates to an input/output control method in a virtual computer system that enables high-speed operation.

[Conventional technology]

A virtual computer system uses a real computer in time-sharing, and sets virtual hardware information in each time-divided time slot, so that one real computer can be used for each time slot as if it were separate. It operates like a computer. As a prior art related to such a virtual computer system, for example, Japanese Patent Publication No. 60-493
A technique described in Publication No. 52 and the like is known.

A virtual computer system based on this type of conventional technology requires interrupts to be notified to a guest program (hereinafter referred to as a guest) running on a virtual machine, and a host program (hereinafter referred to as a host program) that manages a real computer and realizes a virtual computer system. ,
It has an interrupt that should be notified to the host (called the host), and can interrupt the guest at high speed. Generally, it is desirable to interrupt each program directly, and the same applies to input/output interrupts.

As a prior art related to the direct execution method for input/output interrupts, the technology described in, for example, Japanese Patent Laid-Open No. 61-240333 is known.

This type of conventional technology opens a control register to a guest, and when guest identification information sent with an input/output interrupt request from an input/output processing unit matches the running guest, an interrupt is generated. It is permitted.

[Problem to be solved by the invention]

The above-mentioned conventional technology makes it possible to directly interrupt the corresponding program when an input/output interrupt request to the guest occurs while the guest is running. However, when an input/output interrupt request to the host occurs, On the actual computer, the control registers that control the permission of input/output interrupts for each subclass, which individually determine whether or not input/output interrupts can be accepted, are open to the running guest, making it possible to control input/output interrupt acceptance to the host. is difficult. Therefore, the above-mentioned conventional technology has the problem that when an input/output interrupt request to the host is suspended while the guest is running, the response to the input/output interrupt is delayed until control is returned to the host. are doing.

An object of the present invention is to solve the problems of the prior art described above, to make it possible to directly notify an appropriate host or guest of an input/output interrupt with a relatively small amount of hardware, and to enable input/output interrupt requests to be directly notified to the appropriate host or guest. When the input/output interrupt is present, it is determined whether the input/output interrupt can be accepted under the control of the control register without being affected by the input/output interrupt control bit, and if it is determined that the interrupt is possible, the input/output interrupt is A virtual computer system that can accept input/output interrupts under the control of the guest's control register to speed up processing when a TPT instruction that accepts one of the requests is directly executed on the guest. The purpose of this invention is to provide an input/output control method for

[Means to solve the problem]

According to the present invention, the object is to divide and allocate each subclass, which is a unit for individually controlling input/output interrupt requests, to the host and guest, so that the host and guest programs can generate input/output interrupts for each subclass. There are input/output interrupt control bits that can control conditions all at once, control registers that allow a program to control input/output interrupt generation conditions for each subclass, and a control register that allows a program to disable input/output interrupts for each subclass. A subclass mask, a control subclass mask that can release the disabled state for each subclass when the I/O interrupt control bit is disabled, and an I/O interrupt pending register that stores the subclass with the I/O interrupt request. As a result of controlling input/output interrupt requests using the input/output interrupt control bit, real subclass mask, and control subclass mask, if there is a subclass that can generate input/output interrupts, the input/output interrupt microprogram is activated. As a result of controlling input/output interrupt requests using a real subclass mask and a control subclass mask by eliminating the influence of the means for notifying the relevant subclass and the input/output interrupt control bit, the microprogram has a method for accepting input/output interrupts. This is achieved by providing a means for notifying whether or not the service is acceptable and, if it is acceptable, its subclass.

[Effect]

An input/output interrupt request to the host or guest that occurs while the guest is running is masked by the input/output interrupt pending bit, real subclass mask, and control subclass mask. As a result, input/output interrupt requests to the host are processed according to the host's input/output interrupt generation conditions, and input/output interrupt requests to the guest are processed according to the guest's input/output interrupt generation conditions. For any request, if there is a subclass that satisfies the I/O interrupt generation conditions, the microprogram is started, and the microprogram is activated depending on whether the subclass of the generated I/O interrupt belongs to the host or guest. , the corresponding program is notified of the input/output interrupt. Also, T
Execution of the PI instruction is not affected by the input/output interrupt control bits, but is controlled by the real subclass mask and control subclass mask, and is processed according to the guest-only input/output interrupt conditions, and the subclass that satisfies the conditions is If it exists,
It is determined that input/output interrupts can be accepted, and this is done by accepting input/output interrupts for the corresponding subclass.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a logic circuit implementing the present invention, FIG. 2 is a flowchart explaining host subclass mask setting processing, FIG. 3 is a flowchart explaining guest subclass mask setting processing, and FIG. FIG. 5 is a flowchart explaining interrupt processing when running as a guest, FIG. 5 is a flowchart explaining TPT command processing when running as a host, and FIG. 6 is a flowchart explaining TPT command processing when running as a guest. In Figure 1, 1 is the input/output interrupt control bit, 2 is the control subclass mask, 3 is the real subclass mask, 4 is the interrupt pending register, 5, 9.14
is an OR gate, 6 is an OR output, 7 and 13 are AND gates, 8 is an AND signal, 10 is an interrupt generation request signal, 11 is a priority circuit, 12 is an interrupt register, and 15 is an interrupt pending signal. . Note that in the following description, input/output interrupts are simply referred to as interrupts.

As shown in FIG. 1, a logic circuit implementing the present invention includes a control subclass mask (hereinafter referred to as C3CM) 2, a real subclass mask (hereinafter referred to as R3CM) 3, and an interrupt pending register (hereinafter referred to as INTP). ) 4 and a gate 5 that performs logic according to the contents of these masks and registers,
7, 9, 13°, 14, a priority circuit 11, and an interrupt register (hereinafter referred to as 1NTR) 12.

In FIG. 1, interrupt requests of each subclass generated by each of the input/output device, input/output control device, and input/output processing device are stored in INTP4. The interrupt request in rNTPd, the mask information in R3CM3, and the logical sum output 6 from the OR gate 5 of the mask information and interrupt control bit (hereinafter referred to as pswr) 1 in C3CM2 correspond to subclasses, respectively. The AND gate 7 performs a logical product,
It is output as a logical product output 8. This logical product output 8 is
After passing through the priority circuit 11, it is stored in the 1NTR 12.

Further, this logical product output 8 is obtained by calculating the logical sum of all subclasses by an OR gate 9, and generates an interrupt generation request signal lO.
is output from the OR gate 9 as follows.

On the other hand, the inverted signal of the mask information in C3CM2 and the R3C
The mask information in Ma and the interrupt request in TNTPJ are:
After the AND gate 13 performs a logical product for each subclass, the OR gate 14 performs a logical sum of all the subclasses, and outputs the result as an interrupt pending signal 15.

C3CM2 and R3CM3 are configured by registers that can be read and written by a microprogram, and INTR12 is a register that can be read.

The interrupt generation request signal 10 indicates to the system that an interrupt needs to be generated, and serves as a trigger for starting an interrupt processing microprogram. The interrupt pending signal 15 indicates whether or not there is an interrupt request to be accepted when a TPI instruction, which is an instruction for reaping an interrupt request, is activated. T NTR12 allows both interrupts and TPI instructions to be generated for each subclass of the interrupt target, and if multiple subclasses are pending interrupts,
The priority circuit 11 stores the subclass with the smallest number.

PSWI displays the host's interruption permission information when the host is running, and the guest's interruption permission information when the guest is running, and "l" means permission.

Furthermore, subclasses, which are units for individually controlling input/output interrupt requests, are divided and assigned to each host and guest, and the information is set in control registers (not shown) of each host and guest. ing.

Next, the operation of processing interrupts and TPI commands on the host and guest using the hardware logic circuit shown in FIG. 1 configured as described above will be described.

First, the host subclass mask setting process before running the host and when transitioning from the guest state to the host state is performed in the second step.
This will be explained using figures.

In this case, the subclass setting process is to clear C3CM2 (step 201), R5CM
3 stores the contents of a control register (hereinafter referred to as NCR) that controls permission of interrupts for each subclass specified by the host program (step 202).
. If HCR is rewritten by the host program, R3CM3 is updated accordingly. This ensures that all subclass interrupts in host state are controlled solely by the contents of HCR and PSWII.

On the other hand, since the state of a guest that is not running when the guest program is started is saved by the host, it is necessary to restore that value to the hardware again. The guest subclass mask setting process in this case will be explained with reference to FIG.

(1) First, it is checked whether the PSWI of the host is "1" (step 301).

(2) If host PSWII is 11”, CSCM2
The contents of the TT CR are stored in (step 303).

(3) Also, if the PSWII of the host is 0'', the C3C
Clear M2 (step 302).

These processes (1) to (3) prevent the presence or absence of an interrupt request of the subclass assigned to the host and the possibility of interrupt from interfering with the guest's interrupt control, and, as will be described later,
This is necessary to determine whether an interrupt that occurs while the guest is running belongs to the host or the guest.

(4) Next, the logical sum of the contents of HCR and the contents of a control register (hereinafter referred to as GCR) specified by the guest program is stored in R3CM3 (step 304).

In the process of setting the guest subclass mask mentioned above,
One subclass may be shared by the host and guest, but in that case, the host needs to ensure control over the division of interrupts, etc.

Further, OCR may exist before conversion and after conversion, but to simplify the explanation, these will not be distinguished. When the OCR is rewritten by the guest, only step 304 is executed each time since neither the host's PSWI nor HCR changes during guest execution.

Next, the operation of interrupt processing during guest running will be explained with reference to FIG.

In this case, the subclass mask 2.3 setting process is performed according to the flow shown in FIG. 3 described above. A host subclass interrupt request that occurs when the guest is running in such a state is generated when the PSWI of the host is 0'' or 1) (if the content of the corresponding subclass in CR is 0'', The interrupt generation request signal 10, which is the output of the OR gate 9 shown in FIG.
When the PSWI of the host is "1" and the corresponding subclass of HCR is "1", if a subclass interrupt request of the host occurs, the interrupt generation request signal 10 becomes "1",
Notify interrupt occurrence.

(1) As described above, the interrupt microprogram is activated, and the subclass of the generated interrupt is output from the TNTR 12 (step 401).

(2) A logical AND operation is performed between the contents of the corresponding subclass of C3CM2 and the contents of the subclass successively obtained in step 401 (step 402).

(3) In the case of an interrupt to the host, this step 40
The calculation result of 1 is 1'', it is determined that the interrupt is of a subclass assigned to the host, and the state of the actual computer is transitioned to the host (step 403).

(4) After reaching this state, the host executes interrupt acceptance processing for the host (step 404).

The above process is performed when an interrupt occurs to the host when running as a guest. However, when an interrupt request to a subclass of the guest occurs when running as a guest, PSWII becomes "1".
If the content of the corresponding subclass of OCR is "1" in ", the interrupt generation request signal 10 shown in FIG. 1 becomes "1", and the interrupt microprogram is notified of the occurrence of the interrupt.

Thereafter, steps 401 and 402 described above are performed in the same manner as described above. The result of the AND operation in step 402 is "0" in this case, and it is determined that the interrupt is for the subclass assigned to the guest, and the interrupt is directly executed by the running guest in step 404 without transitioning to the host. Reception processing is executed.

Note that the interrupt processing while the host is running can be performed in the same manner as in the prior art, so the explanation thereof will be omitted.

Next, the process when executing the TPT command on the host will be explained with reference to FIG. In this case, subclass mask 2,
3 is set according to the process explained with reference to FIG.

(1) Whether or not the interrupt pending signal shown in Figure 1 is "1", that is, there is a subclass of the host with the interrupt request, and the content of the corresponding subclass of the HCR is "1" regardless of the PSWTI. Check whether it is. If the interrupt pending signal 15 is "0", the subclass of the host requesting the interrupt does not exist, so the process ends (
Step 501).

(2) In step 501, if the interrupt pending signal 15 is "1", after setting the contents of C3CM2 to all "1", the TN
The TR12 is read (steps 502 and 503).

(3) Thereafter, the contents of C3CM2 are returned to the cleared state immediately before execution of step 502, and interrupt acceptance processing is executed (steps 504, 505).

In the process of executing the TPI instruction on the host described above, at the time of step 501 in which the interrupt pending signal 15 is tested, C3CM2 is all "0", and the test condition is only R30M3 that stores HCR. The masked result will be reflected. In addition, setting the contents of C3CM2 to all "1" in step 502 before executing step 503 eliminates the influence of PSWII,
This is to reflect only the contents of R30M3 in the readout of rNTR12.

Next, the process of directly executing a TPI instruction on the guest will be explained with reference to FIG. In this case, subclass masks 2 and 3 are set according to the process explained with reference to FIG.

(1) First, check whether the interrupt pending signal shown in Figure 1 is "1", that is, there is a guest subclass with an interrupt request, and regardless of the PSWI, the contents of the corresponding subclass of the GCR are Check whether it is "1".

If the interrupt pending signal 15 is "0", the subclass of the guest requesting the interrupt does not exist, so the process ends (step 5oi) = (2) In step 601, the interrupt pending signal If 15 is 1”, the contents of R30M3 and C3CM2 are temporarily saved (
Step 602).

(3) After performing an AND operation on the inversion result of C3CM2 and the contents of R30M3 and storing the result of the operation in R30M3, the contents of C3CM2 are set to all "1" (steps 603 and 604).

(4) Read TNTR12. By this reading, only the subclass of the guest subclass that has an interrupt request can be read (step 605).

(5) After that, the recovery process of the contents of R3CM3 and C3CM2 is executed, and the interrupt acceptance process is executed (step 6
06,607).

In the process of executing TPI instructions on the guest mentioned above,
When determining the interrupt pending signal 15 in step 601,
At that point, C3CM2 already stores the contents of HCR, and R5CM3 stores the logical sum of the contents of Tf CR and OCR.As can be understood from the logic in Figure 1, the contents of the host subclass The interrupt request is made in step 601.
does not affect the judgment conditions. Furthermore, the processing in steps 603 and 604 is a process for eliminating the influence of PSWII when reading T NTR12, and making it possible to read only the subclass assigned to the guest among the subclasses that have an interrupt request. be.

According to the embodiment of the present invention described above, it is possible to notify an appropriate host guest of an interrupt that occurs while the guest is running, and furthermore, when executing a TPT command, only for subclasses that have
Testing and acceptance of interrupt generation requests may enable operation.

[Effects of the Invention] As described above, according to the present invention, an input/output interrupt that occurs while a guest program is running can be notified to an appropriate host program or guest program, and TPr Since instructions can be executed directly by accepting only guest interrupts while the guest program is running, it is possible to speed up the processing of the virtual computer system and improve performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a logic circuit implementing the present invention, FIG. 2 is a flowchart explaining the host subclass mask setting process, and FIG. 3 is a flowchart explaining the guest subclass mask setting process. FIG. 4 is a flowchart for explaining interrupt processing when running as a guest, FIG. 5 is a flowchart for explaining TPI command processing when running as a host, and FIG. 6 is a flowchart for explaining TPI command processing when running as a guest. 1--Interrupt control bit, 2--Control subclass mask, 3--Real subclass mask, 4--
・---1 interrupt pending register, 5, 9, 14
--------OR gate, 6-----OR output,
7.13 --- AND gate, 8 --- AND signal, 10 --- Interrupt generation request signal, 11 ---
-Priority circuit, 12--1 interrupt register, 15-
---Interrupt pending signal. Figure 1 Porridge 2 Figure 3 'f' sp ``j-y = Straw person 7 Swa shell 2t'fl Figure 4 Guest running guard〒H Teratomi 11fu V Father rsW Figure 5 Tile, TPI- $+1ff- Fig. 6 Gemata H, TPL now panther

Claims (1)

[Claims] 1. In a virtual computer system that can run multiple operating systems simultaneously, a subclass, which is a unit that individually controls input/output interrupt requests, is divided into a host program that controls the virtual computer system, and a virtual machine that controls input/output interrupt requests. An input/output control method in a virtual computer system characterized by dividing and assigning to a guest program running on a computer. 2. Process input/output interrupt requests from subclasses assigned to the host program that occur while the guest program is running, according to the host program's input/output interrupt generation conditions, and process input/output interrupt requests from subclasses assigned to the guest program. 2. The input/output control method in a virtual computer system according to claim 1, wherein the input/output interrupt request is processed according to input/output interrupt generation conditions of a guest program. 3. When an input/output interrupt request exists, only for the input/output interrupt request of the subclass assigned to the guest program, determine whether the input/output interrupt can be accepted under the control of the guest program's control register, and 2. The input/output control method in a virtual computer system according to claim 1, wherein an instruction for accepting one of the input/output interrupt requests is directly executed on a guest program. 4. In a virtual computer system that can run multiple operating systems simultaneously, the host program that controls the virtual computer system and the guest program that runs on the virtual machine are each a unit that individually controls input/output interrupt requests. An input/output interrupt control bit that can collectively control the input/output interrupt generation conditions of subclasses, a control register for each program that allows host and guest programs to control input/output interrupt generation conditions for each subclass, and subclasses. An actual subclass mask that can disable input/output interrupts for each subclass, a control subclass mask that can release the inhibited state for each subclass when the input/output interrupt control bit is disabled, and An input/output control method in a virtual computer system, comprising: an input/output interrupt pending register that stores a subclass with an output interrupt request.