JPS6043754A - Emulator - Google Patents

Abstract

PURPOSE:To attain emulation of a target system via a common bus by providing a support CPU which controls an emulator and a bus switching part, and connecting an emulation memory, tracer and a monitor via one common bus. CONSTITUTION:A support CPU9 is set under a main CPU1 which controls a system as a whole and controls an emulator totally. A bus switching part 10 switches buses 11-13 when a using request of the common bus 11 is fed from the CPU9 or an emulation CPU2. The CPU2 usually has higher priority than the CPU9 for use of the bus 11. In case an access conflict arises between the CPU9 and the CPU2 to an emulation memory 14, a tracer 15 and a monitor 16 connected to the bus 11, the conflict state is solved by the mediating function of the part 10.

Description

[Detailed description of the invention] The present invention relates to an emulator.

In particular, the emulation memory, the tray r and o, which includes a path switching section and is controlled by the path switching section: -E=
The emulator is an emulator that performs path switching between the common/mass and the support OPU path, allowing the emulation CPU or support OPU to access the emulation memory, tracer, or monitor, respectively, through one common path. It is related to.

In recent years, microprocessor-applied equipment has developed rapidly,
It has come to be used in all fields. The emulator Vi helps microprocessor-applied devices achieve their desired goals in a short period of time.It runs microprocessor-applied devices in real time, and helps find and debug programs and hardware bags under development. It's easy.

A conventional emulator has a configuration as shown in FIG. In other words, the main 0PUI is accessed via the emulation memory 3, controller 4, and monitor 5f that constitute the emulator: the main CPU path 6,
On the other hand, emulation 0PU2'4. which acts as a CPU to be installed in the target system 7. Emulation CPU path 8t-via emulation memory 3
．． ) Make sure to access the laser 4 and monitor 5.

For this reason, emulation memo 173. The main CPU bus 6 and the emulation CPU path 8 are connected to the tracer 4 and the monitor 5, respectively, which has the disadvantage of physically increasing the number of wires. As the number increases, the number of path wiring increases accordingly, and the defects expand.Also, the emulation memory 3, tracer 4 and monitor 5 respectively
The emulation memory 3 must have a mapping circuit and an access target determination circuit. was complicated.

Furthermore, there is a problem in that access contention occurs between the main 0 PUI and the emulation CPU 2. In order to cope with this, a complicated path switching circuit must be provided in each device.

The emulation memory 3 is a storage device for storing the program of the target system 7, that is, the user program under development.
Emulation CPU 2 starts from the moment when the specified conditions are met.
Take the execution track record. In other words, 4AF allows you to trace each cycle, such as a machine cycle or a pass cycle, without specifying the path state! It is. It also stores the function to stop the monitor 5d user program and the monitor program that emulation 0PU2 executes when it stops, as well as the main 0PUI and emulation 0PUI.
This device is equipped with a memory that stores information τ exchanged with the PU2.

The present invention VI, aims to solve the above-mentioned drawbacks, and provides a CPU for managing the emulator, a path switching unit, and connects the emulation memory, tracer, and monitor with a common path of 11 directions.
It aims to provide a kill emulator that emulates the target system through the nuclear common basketball.

The present invention will be explained below with reference to all 42 and subsequent diagrams.

Here, the 21st is the 411Q emulator according to the present invention.
Figure 5 and Figure 3 are an explanatory diagram of the principle of the emulator according to the present invention & Figure 4? An embodiment of the address bus and data bus switching circuit tjf configuration, Fig. 5 an embodiment of the μ path length tνb, Figures 6 to 51↓81 Nominal emulation CPU common bus usage. The time chart at the time of occurrence, No. 91XI, No. 1o is emulation C.
12 shows a time chart when a conflict for a request to use the common bus occurs between PU and OJ'jJ.

In the configuration diagram of the emulator according to the present invention shown in FIG.
1, 2.7 correspond to those in FIG. Sabo)C
The PU 9 manages the entire emulator of the present invention and is provided under the main CPU 10 that manages the entire system.

The path switching unit IO is also two-board 0PU9. When a request for a common path 4 is received from the emulation 0PU2, the common path 11 is switched to the support CPU path 12 or the μ emulation CPU path 1:). Normal emulation 0 PIJ2υ76 is the default) CPU 911 (has preferential use of the common path 11 for IT.Common) 11 VC'd emulation memory 14. tray? 15. A monitor 16 is connected, and these emulation memories 14.
Tracer 15. Or support 0PU for monitor 16
9. ! : When an access conflict occurs with the emulation 0PU2, the conflict is resolved by the arbitration function of the node switching unit 10 by the method shown in FIG. μhArJ3.

In addition, emulation memory 14 & tray two 15
, each device on the monitor 16 is designed to allow quick access.

Figure 3 (I)+j: When emulation 0PU2 accesses the target system 7 and the tracer 15 races the emulation 0PU2, the occupancy status of the common path 11 of emulation OP U 2 is detected. It shows. The emulation 0PU2 occupies the common path 11 at the beginning of this lift 6·μΦ 1 machine cycle and after rF4.

When the emulation CPU 2 occupies the common lotus 11, μE is shown, and when the emulation CPU 2 does not occupy the common lotus 11, S is shown (Figure 3 [■) below]. Same thing).

Figure 3 (I)? The figure shows the occupancy status of the common path 11 when the Maemi-style office lady U 2 is accessing all of the emulation memory 14. In this case, emulation memo I for emulation CPU 2)
14 is completed quickly, and the common path 11 is released as soon as access is completed.

FIG. 3 Qll) shows the occupation status of the common node ζ space j1 when the emulation 0PU2 accesses the target system 7 and the tracer 15 is not racing the emulation 0PU2.

In this case, while determining whether the emulation CPU 2 is accessing the target system 7 or the entire emulation memory 14, the emulation CPU 21iUI occupies the common path 11 and the emulation 0PT32 If it is determined that the target system 7 is being accessed, the common bus 11 is then released.

An example of the configuration of the path switching section 10 in which such switching of the common path 11 is performed is shown in FIG. 'J 'l)
This will be explained with a diagram.

Figure 4 (J emulation C1) Using a 16-bit microprocessor in U, one address bus and data bus 5υ conversion times j+;1'y CD-implementation drive.
'jk rJ, 'c is shown.

In the same figure, 17B & mapping circuit, 18 to 23 are tri-state output buffer circuits.

24, 25 ii) Latch circuit for live state output.

26 to 29t negative logic differential 1S circuit%: (0, 3
1) One ζ represents the input circuit. These buffer circuits 18 to 23 and U latch circuits 24 and 25
5 passes through each circuit (in the direction of the arrow shown) address and data.

Mapping circuit 17B & balance, emulation -/con CPU path 13', via c -c emulation OIJ
At 1 ns O~23 from U2;) Back, Emulator E 70 P U 71' Res (g Bottom E AD
t: 4 ija t, 6) 14 to 23 are manually operated, :A the Matsubinno L-! 1 and each 17B, change the J address f 'A 'f address shiko' address 4 and 7
On the other hand, the signal is output to the buffer circuit 18. Address O~2 of CPU 2 or L); U'J) Ura;
14ADt) to 130 fatigue addresses, . . . are input to the buffer circuit 20 -j'. Emie 1/- Noyon Ij P
When LI 2 passes the same Jl pass 11 and the furnace is turned off, and when the limit part 10 knows one prefecture, the pass cutting part 10 is installed (LC is 'AS 0'. Nine lessons - circuit 32
From the buffer circuit is to 20 emulator access on (hereinafter referred to as 1), abbreviated as AON) No. 1B is output.iii+il''! r L J no Tosa Active Totoru. The same applies to other signals), and thus the E A I) input to the buffer circuits 18 and 20 is 14 to 23° EA
It passes through the buffer circuits 18 and 20 of DO~131ri and becomes addresses (hereinafter abbreviated as AD) O~20. Furthermore, among the EADOs to 23, EADs 14 to 23 that are manually input to the mapping circuit 17B are input to the buffer circuit 19, and these EADs 14 to 23 are used for address conversion.
&: Non-mapped addresses (NMPA under L3, abbreviated as D) 0 to 9 pass through the Nonotsufa circuit 19 without interruption.
and is supplied to the tracer 15. Support CPU9
When the common path 11 / (L: to be used) is sensed by the switching unit 10, support access is turned on (hereinafter referred to as 5A) from the sterilization circuit 32 to the buffer circuit 21 as shown in FIG.
(abbreviated as ON) signal is output. As a result, the support OPU address c (abbreviated as SA, D) 0-20 input to the buffer circuit 21 passes through the buffer circuit 21 and becomes ADO-20. Even if a conflict occurs between the emulation CPU 2 and the sabot CPU 9 for a request for the common/split path, either the dEAON signal or the 'risAON signal is output from the control circuit 32 shown in Figure 5, and the emulation CPU 2 and Sabo) C! P.U.
The address bus is switched by the path switching unit 10 without causing an address conflict with the address bus 9.

Data bus switching is performed as follows.

In other words, when transferring data from the emulation CPU bus 13 to the common path 11, the emulation CPU bus 13
When the path switching unit 10 senses that the common path 11 will be reused by the computer 2, the path switching unit 10 issues a common path use request (hereinafter referred to as B B U S
The EAON signal and the data strobe (hereinafter abbreviated as L) and data strobe (hereinafter abbreviated as L) signals are generated in the path switching unit 10, and the control circuit 32 shown in FIG. A read/write (hereinafter abbreviated as It/W) No. 1J, in this case a TiW signal, is output. From the negative logic NAND circuit 26 to the buffer circuit 22.
\Enable signal is sent tl, emulation OP
U-Pax13c/) engineering 'Mulation CPU data (
The data 0 to 15 (hereinafter abbreviated as EDAT&) are placed on the data bus of the common path 11 via the notifier circuit 22 as data 0 to 15 (hereinafter abbreviated as 1+AT'A).

i fc M K , both Mx From the lotus 11 to the emulation CPU path 13, DATAO~15 (f- is loaded.

When path reversal 1i1i 10 senses that emulation 0PU2 uses common path 11, BBt
The rstLq signal is generated in the path switching unit lO, and the fifth
The control circuit 32 shown in the figure outputs a signal/W (in this case, a signal and an emulation CPU data clock (hereinafter abbreviated as E DOL K)).

hi BUS RQ signal and emulation apu
Read signal of AS13 (hereinafter w lL 1g and lti
), the negative logic NAND circuit 27 and latch circuit 24 are enabled, and DA'J, 'AO~15 are sent to the emulation CPU/process 13, but I
Bow DOL K signal Niyoshi dba XII's DA'I'A
O to 15 are latched by the latch circuit 24, so E
The contents of I) ATAO to 15 when the DOLK signal is latched are held. Then, DATA θ~15 latched by the latch circuit 24 is lost to the emulation 0PU2 at an operation timing to be described later.

The data bus switching for the support 0PU9 is almost the same as that for the emulation 0PU2 (7). That is, support) CPU9[+111 buffer circuit 23 & latch circuit 25. Negative logic NAND circuit 28
．． 29 and Inno Ku Ichiyo Circuit 31μ.

Emulation OP U 211+! Buffer L of I
'J path 22° latch circuit 241 negative logic NAND circuit 16
．． 27 and the inverter circuit 30 and correspondingly, the 5AON signal output from the control circuit 32 in FIG. Tsuku C and below S
(abbreviated as DOL K) 1μ, Zaboto OP U
Read signal of path 12 (hereinafter abbreviated as S It times signal)
KEEA ON No. 4.7, Jsu53 (, + 3 几Q
signal.

E DOL J signal %El (corresponds to each signal. EAON signal and S A ON signal μ system (2)
There are no simultaneous outputs from circuit 32, so EDATAO~15 on emulation CPU path 13 goes to DATAO~15 on common path 11, and vice versa.
AO~15 is the emulation CPU, and Fi is on bus 13.
Data bus switching from DATAO to 15 and support CP
Support CPU data of U path 12 (hereinafter abbreviated as 5DNTA = i) 0 to 15μ d Lotus 11 I) A T
AO~15 and vice versa DATAO~15 are switched to the support CPU path 12, and the +3 exchange of each data bus with the switchback of the data path to 5 DATAO~15 is performed without conflict.

FIG. 5 shows the configuration of an embodiment of the path switching section. 17
A is the access target identification circuit and emulation 0
The access of PU2 is determined whether or not to use A
1c outputs "H" when the target system 7 is accessed.

Reference numeral 32 denotes a side-turning circuit which outputs each of the control signals described above to the address and O/data bus switching circuit 33 for filJωJ as described in FIG. Nak.

Since the control circuit uses a 32μ high-speed interface, it is composed of a gate circuit and the like.

This is a 33μ address and data bus switching circuit having the circuit configuration described in FIG.

Figure @6 shows a time chart when there is no common path use request from support 0PU9, emulation 0PU2 accesses 7 frames of the target system, and tracer 15 is tracing.

When the EBUS Q output is also generated in the path switching RB 10, the control 1 circuit 32 outputs the EAON signal, and the buffer circuit 18.20 becomes enabled.
+fj emulation 0PU2 occupies Am path 11. And after the 18AON signal is output.

Even if a predetermined period of time has elapsed, that is, even if the 14th intercostal interval has elapsed, the access object determination circuit 17A will still be unable to access M A P IJ.
Since the N, 11 signal is not output, the control circuit 32 determines that the access is from the emulation 0PLI 21ri target system 7 side, and releases the emulation 0PU 21- from occupying the common path 11. This opening of the common path 11 corresponds to the period f shown in FIG. Accordingly, as stated,
If emulation 0PU2 and support OP U
If there is an access conflict with 9, it will be canceled)
The CPU 9 can utilize this free time to use the common path 11.

In the case of FIG. 6, the tracer 15 traces the execution summary of the emulator 0PU2, so when all the path information (address, data, control) is determined, the control circuit 32 outputs the EAON signal again. I(,/
A W multiplied signal and a DS signal are output. As a result, the cipher circuit 22 is enabled, and the emulation OPU
The data EDA'r A O~15 obtained by accessing the target system 7[1111 by the target system 7[1111] is loaded onto the DATAO~15 of the common path 11 via the buffer circuit 22. At the same time, buffer circuits 18 and 20 are enabled).

Address information is also output (■ in the figure). That is, the emulation 0PU2 occupies the common path 11 again. At this time, the acknowledge (hereinafter abbreviated as OK) signal is j
IilJ a11 is output from circuit 32, and this signal triggers the signal? Insert 15id pass 4 information.

The six signals shown in (a) in the figure are signals within the path cut FA unit 10, and the five-tree signals shown in (b) are signals from the common path 11.

Figure 7 shows the case where the common path 1 of the support cPU9 is not available, and the emulation OPU 2 or the common path 11 is not available.
The figure shows a time chart when Qi is used (with Qi as the read cycle).

g S U +3 It in path switching section 1.0. (When No. 8 is born, h fblJ im circuit 32 to 1y A
The ON ls signal is output, the buffer circuit 18.20 is enabled, and the emulation c
p U 2 occupies the common path 11 . And E A
tJ After N signal output.

After a predetermined time of 1 dJ has elapsed, the MAPON signal is output from the access target control circuit 17A. As a result, the control circuit 32 determines whether the emulation ap02 uses the common bus lli, and subsequently the emulation 0PU2'
ri continues to occupy the Jim space 11 (FIG. 1). For example, emulation 0PU2 is emulation memory 1
When performing read access to 4, EADO~2
EAD 14 to 2317 of 3) ADO whose address has been converted to a real address by the virtual address mapping circuit 17B
A read access is made to the emulation memory 14 at addresses .about.20. The emulation memory 14 is a high-speed memory, and the ADO
The contents stored on ~20 are f) ATAO~1
5 and is placed on the common path 11. Then, the A OK signal from the emulation memory 14 is sent to the NOPASS switching unit lO.
E is sent to the latch circuit 24 which serves as an enabler.
The DATAO-15 are latched by the DOLK signal (FIG. 71).5 After this latch, the common path 11 of the emulation 0PU2 is released as shown in (2) in the same figure. And emulation 0PU2 1
DATAO~15) 5 emulation 0PU2 latched by the latch circuit 2 at a predetermined operation timing of the machine cycle
As a lieto. The emulation OP 02 is accessing the emulation memory 14 on the rF at the normal operation timing/) 11〈However, the read access to the emulation memory 14VC 'f, < is completed as soon as possible.'' ? As explained above, the second half of one machine cycle is the same) ill /Z 11
&if is not being used at this time. When an access conflict occurs between the emulation 0PU2 and the support CPU 9, the support CPU 9 can use the common path 11 by using this free time 1'i4] 411.

In the figure, (a) shows the seven signals in the NOx switching unit 10, and (b) shows the six signals in the L common/path 11.

FIG. 8 shows a time chart when the emulation c+puz reuses the common bus 11 as a write cycle in S case where there is no request for use of the common bus 11 by the CPU 9.

When the E13 U S It Q signal is generated in the path switching unit 10, the control circuit 32 outputs a signal tL'f, and the receiver outputs EAON.
The signal is output and the Nonotsufa circuit 18.20 is enabled and fL, h b emulation C as shown in Figure 8I.
PU2 occupies 11 common paths. Then, after a lapse of time after the EAON signal is output, the access target establishment circuit 17
A to M A J) Outputs ON signal. As a result, emulation OP U 2 uses Kyomoe Hasu 11! l (I disconnection is made by the control circuit 32, and continues to occupy the emulation CPU 2't'JL common path ll' (FIG. 8 1) 5 For example, the emulation 0P
U2 performs write access to the emulation memory 14 (lJ, 4, IflAI) B among 0 to 23
Mapping circuit 17 for virtual addresses of ADs 14 to 23
[ADO~20 whose address was converted into a real address in step 1 is the buffer circuit is, zo? 1. onto the common path 11 via c. Ru.

) 5 The E DATA O~15 output from the emulation CPU 2 to be written is enabled by the DS signal V output from the control circuit 32, so that the buffer circuit 22 is enabled. and is loaded onto the common path 11 as DATAO~15.

Then, DATAQ~15 is written onto the memory 14 (7)''v A'DO~20 of the emulation memory 14, which operates at high speed.

As a result, the AOK signal is sent from the emulation memory 14 to the path switching unit 11, and from then on, as shown in H in the figure, the emulation OP U 2 ? , t Release the occupation of the common path 11.

Generally, the data to be written to the CPU is output immediately after the address is output, so that the write process to the emulation memory 14 can be completed quickly. Therefore, compared to the normal operation timing of emulation 0PU2 &
14: As in the case of the lead explained in Section I and Figure 7,
The second half of the machine cycle is an idle time when the common bus 11 is not used.

When an access conflict occurs between the emulation 0PU2, support 0PU9, and D, the free time can be used to use either the CPU 9 or the common path 11.

In the same figure, the seven signals in (a) are signals within the NONOS switching unit 10, and the six signals in (b) are all from the IT1.
This is ZZS 11th pass number.

Next, the concept of the operation when a conflict occurs between the emulation QPU 2 and the support CPU 9 for a request to use a common path will be explained using the time charts shown in FIGS. 9 and 10.

In FIG. 9, the path switching unit 10
When the Q times signal is generated, the EAON signal is output from the control circuit 32, and as explained above, the emulation 0'P
U 2 occupies the common path 11 (FIG. 9I).

During the period shown in Fig. 9 I, 5 BUSR is generated at the path switching bar IX10.
Even if the Q signal is generated, the control circuit 32 does not output all 5AON signals, so emulation 0PU2 is connected to common path 1.
Continue to occupy 1. Then, “1tiiJ mu circuit 32
The ACK signal is sent to tL, and the gAON signal disappears, that is, it is inverted from rL to rHJ, and the emulation 0PU2 becomes the common lotus 11. (D Occupancy f: Release. Immediately control circuit 321/'1 SAON signal f,
output and support) CPU 9 occupies common path 11.

Then, when the E B U S RQ signal is generated in the path switching unit 10, if the support 0 PU 9 has not completed the pass cycle of the common path 11 by then, the E B U S RQ signal is
[), emulation CPU 2 is common path 11f:
The control circuit 32 has the right to use it as a friend.
It outputs the dEAON signal and eliminates the 5AON signal. That is, the SAON signal is inverted from "L" to "I(").

This also erases the ACK signal. While the common path 11 of emulation 0PU2 is occupied (9th
In Figure ■), the machine cycle of the CPU 9 is not yet completed, so S B [J S 11. The Q signal is still output from the control circuit 32.

When the emulation 0PU2D common path 11 is released, the control circuit 32 outputs the 8AON signal again, and the ? baud) CPU2 occupies the common path 11 (-, l
! 9), execute the machine cycle. When the support 0PU2 machine cycle is completed, the control circuit 32
~A An OK signal is sent, which causes the control circuit 321 to
-t, 5 The AON signal is extinguished. In this way, when a request for one history of the common/path 11 conflicts with the emulation CPU 9, the emulation 0PU2 described in FIG.
Path switching is performed in which the support 0PU 9 occupies the common path 11 by using the free time 4u that is not occupied by 1e.

FIG. 10 is a detailed time chart when a common path usage request conflicts between the emulation CPU 2 and the support CPU 9 in the same manner as in FIG. 9.

1O Figure 1 Supports 1-OP U 9 Common Path 11
This is the case when the machine cycle is not completed while the nh emulation 0 PU2 occupies the common space 11, and the machine cycle is completed while the nh emulation 0 PU2 occupies the common / III supports 0PU9 again occupying the common path 11 and following each other when its machine cycle is completed.

The above explanation is based on an example of a 116-bit microprocessor, and the emulation 0PU2C
The number of 1 bits is not fixed, and a microprocessor with any number of bits may be used. The number of lines of the address bus and data bus changes accordingly.

As explained above, by using two lines and four lights.

(1) A path switching section is provided to switch all lines.
Since only one common path is required and the number of path line wirings is small, the number of bits of the emulation CPU is large.
At yr 4%, the effect is indeed remarkable.

(2) And the emulator μ boat CP of the present invention
Uf: Since it is equipped, it can be separated from the main CPU and used as a standalone product.

(3)'Also, the path switching is done at the path switching section.

The emulation memory, tracer, and monitor devices each have an emulation function (Ol) U,! : Main 01
) It eliminates the need for a complicated cut-out circuit that deals with access contention with U, and at the same time reduces the need for paranoia circuits.

(4) Furthermore, by providing the mapping circuit and access target determination circuit, which were conventionally provided in the emulation memory, in the path switching section, (a) the map output can be output faster.

fb) Emulation OP U,! :Main CP
Because it is no longer accessed by both U and U.

The 4G configuration of emulation memory becomes 1 module.

(C) Support CP provided under the main CPUQ
As U moves from the emulator's base to l/'1-?, it becomes smaller.

(d) Emulation memory 'd: '4' A can be +77JIl 3-.

There are other effects.

[Brief explanation of the drawing]

Figure 1 is a diagram of a conventional emulator; Figure 2 is a diagram of the basic structure of an emulator according to the present invention; Figure 3 is a basic outline of an emulator according to the present invention; Figure 4 is a diagram showing the address bus and Example configuration of data bus switching circuit, FIG. 5 shows an example configuration of a path switching section. FIGS. 6 to 8 are time charts when a request to use a common path for μ emulation OPU occurs. Figure 9 and @lO diagram show emulation cPU and support CPU1! :! /) The time chart for the time when requests for common bus features were made is very busy. In the figure, 1μ main CPU, 2 is emulation OP
U, '3? j Emulation memory, 4) Ma tray? b 5 'ti seven units, 6 is main OPU bus, 7 target system, 81rJ, emulation OPU/path, 9 is support CI'U, lOi ma path switching unit, 11μ common path, 12 is support OPU path,
13i1 emulation CPU path, 14μ emulation memory & 151 Utrayt, 16μ monitor, 17Ai-t: access target identification circuit, 17B is pine pink circuit, 18 to 2311 breadthr circuit, 24.
25 is a latch circuit lL8. 26 is a negative logic NAND circuit, 30. :(Il, inverter circuit, 3.2 is open-
Circuit, 33μ address and data bus disconnection (negative circuit is applied. Patent applicant: Anritsu Electric Co., Ltd. 11

Claims (1)

[Claims] n) An emulation CPU 2 that acts as a heki OPU installed in the p-kerato system 7: a support 0PU 9 that manages the emulator in order to emulate the target system; and a program for the target system. an emulation memory 14 for storing a monitor program; a tracer 15 for tracing the execution history of the emulation CPU for each specified leak from the point when a specified condition is met; The monitor 16 stores information exchanged between the emulation memory, the tray f and the monitor common path 11 is connected to the emulation CPU path 13 or support CPU? , f'-) When switching to one of the OPU paths 12 and a conflict between the emulation CPU and the support CPU in requesting to use the common path occurs, priority is given to switching the common path to the emulation CPU path. When the emulation CPU is not using a common path, the support CPU /
An emulator comprising a path switching unit 10 for controlling switching of common path occupancy in ru. (2) The path switching unit 10 mapping circuit 17f
An emulator according to claim 1, characterized in that the emulator is provided with an address conversion circuit 3, and the emulation memory r is accessed after address conversion is performed by the mapping circuit. +3) The access target determination circuit 17A that determines whether the emulation CPU access uses the common bus purple; and the emulation CPU or UV port) OPU uses the common path. In some cases, the address and data switching circuit 33 has an access time conversion function that reduces the usage time of the common / each bus while each CPU processes with its own access time.
The emulator according to claim 1 or claim 2, further comprising: a control circuit 32 for controlling an address and data/access switching circuit.