JPS63208132A - In-circuit emulator - Google Patents

Abstract

PURPOSE:To inhibit an internal interruption in the course of a step operation by masking an interruption control flag in a status register of a saved target CPU, by a system CPU. CONSTITUTION:At the time of executing a step operation, first of all, an interruption control flag in status register information of a target CPU 11 saved already in a bidirectional memory 6 is further saved in a system memory 3 by a system CPU 1. Subsequently, under the control of the target CPU 11, an instruction code to be executed is stored in the bidirectional memory 6 from a target memory 12. Moreover, by the system CPU 1, this instruction code is saved to the system memory 3 from the memory 6. Thereafter, the interruption control flag stored in the bidirectional memory 6 is masked by the system CPU 1, and a step operation to which an interruption is inhibited is executed by a monitor program 7.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an in-circuit emulator that can analyze the operation of a microprocessor. This invention relates to an interrupt control function when operating in a single step using a simulator.

[Prior Art] When a central processing unit (CPU) of a microprocessor generates an internal interrupt, it cannot be masked from the outside using hardware techniques. Therefore, when an in-circuit emulator is connected to this CPU to perform single-step operation, if an interrupt occurs during a step, a program that does not originally want to perform step operation (i.e., interrupt processing: for example, a timer interrupt, etc.) (interrupts that occur at short intervals, etc.) cause the step operation to shift to interrupts that occur at short intervals.

Therefore, in order to mask this internal interrupt, it was necessary to take measures such as changing the program to be debugged (programming it so that internal interrupts do not occur temporarily).

The present invention has been made in view of these points, and is an in-circuit emulator having an interrupt control function that enables internal interrupts to be disabled during step operation without changing the debugged program at all.・The purpose is to provide an emulator.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a system memory that can be accessed by the system CPU, and a system memory that is accessible by the system CPU.
The present invention is characterized in that it includes a bidirectional memory that can be accessed by the PU and the target CPU, and when the system CPU executes a step operation, it operates according to the following procedure.

■Save the status register information of the target CPU in the bidirectional memory in advance.

(2) The system CPU further saves the interrupt control flag in the save status register from the bidirectional memory to the system memory.

(2) The system CPU causes the monitor program to obtain an instruction code for actually executing a step operation.

(2) The monitor program obtains an instruction code from the target memory under the control of the target CPU and stores it in the bidirectional memory.

(2) The system CPU refers to the instruction code stored in the bidirectional memory and saves it to the system memory.

0 Next, the system CPU masks the interrupt control flag of the status register stored in the bidirectional memory,
Instructs the monitor program to perform normal step operations.

■The interrupt control flag is in the canceled state before it is masked, and the interrupt control flag is changed to the unmasked state only when an instruction that does not affect the interrupt control flag is executed.

[Operations] In the present invention, the interrupt control flag in the status register immediately before the execution of a step operation is saved, and the relevant instruction for executing the step operation is prefetched and saved. Subsequently, the system CPU masks the saved interrupt control flag, starts the monitor program, and executes the step operation.

The masked interrupt control flag is in a released state before being masked, and the interrupt control flag is changed to a non-masked state only when an instruction that does not affect the interrupt control flag is executed.

In this way, internal interrupts can be inhibited during step operations without changing the debugged program of the target system at all.

[Example] The present invention will be described in detail below by way of example with reference to the drawings. FIG. 1 is a block diagram of the main parts of an in-circuit emulator according to the present invention. In the figure, A indicates the emulator main body side, and B indicates the target system.

On the emulator main body side A, 1 is the system CPU;
2 is a system bus, 3 is a system memory, 4 is a bus controller, 5 is a control circuit, 6 is a bidirectional memory, 7 is a memory in which a monitor program is stored, and 8 is a bus multiplexer.

In target system B, 9.10 is the bus, 11
is a target CPU, 12 is a target memory, and 13 is a target ■/○ (Ilo is a human output device).

The control circuit 5 uses the system CPUI or the target CP
The bus controller 4 and the bus multiplexer 8 are controlled in accordance with control information given from the UII via the bus 2 or 9, respectively.

The bus controller 4 transfers control of the memory to the system CP.
Switch to either the UI or target CPU 1 and perform control to enable memory access.

Bus multiplexer 8 connects system bus 2 to bus 9.
This is for switching between bus 1o and bus 1o.

The operation in such a configuration will be explained next with reference to the operation flow shown in FIG. Note that when the system CPUI or target CPUI 1 accesses memory,
! Although it is necessary to provide information to the control circuit 5 to appropriately control the bus controller 4 and bus multiplexer 8, such control operations are well known and will not be explained in detail here.

The target CPU 1 of the target system B saves its status register information to the bidirectional memory 6 under the control of the monitor program 7 in advance.

When the system CPU recognizes that a step operation is to be executed, it first determines whether or not interrupts are disabled during the step operation.If interrupts are not disabled, the step operation is executed as is.If 1 interrupt is disabled, the next operation is executed. conduct.

The interrupt control flag in the status register, which has already been saved in the bidirectional memory 6, is further saved in the system memory 3.

Next, the monitor program in the memory 7 is instructed to obtain an instruction code for actually executing a step operation. This allows the monitor program to
An instruction code is obtained from the target memory 12 under the control of I1 and stored in the bidirectional memory 6. Thereafter, the system CPUI refers to this instruction code from the bidirectional memory 6 and saves it to the system memory 3.

After these series of processes are finished, the system CPU
I masks the interrupt control flag of the status register stored in the bidirectional memory 6 and instructs the monitor program to perform normal step execution. This performs step execution with interrupts disabled.

Next, the restoration of the masked interrupt control flag will be described.

Since the interrupt $II control flag itself may be affected by the instruction that executed the step operation, the interrupt control flag is restored as follows.

■A state in which the interrupt control flag is already masked before it is masked.

■When an instruction to unmask or set the interrupt control flag is executed step by step.

In these two cases, there is no need to restore the interrupt control flag, and the series of step execution operations ends as is.

■Before the interrupt $11 control flag is masked, the release status is W! A (not masked) and an instruction that does not affect the interrupt control flag at all is executed.

Only in this case will the interrupt control flag be changed to a non-masked state. This provides the same result as if the mask had been restored.

In the manner described above, interrupt prohibition during step execution is achieved.

[Effects of the Invention] As explained in detail above, when a microprocessor that generates internal interrupts is caused to perform a step operation using an in-circuit emulator, in the conventional case, the program to be debugged must be changed in advance to generate internal interrupts. However, according to the present invention, step operations can be performed while inhibiting internal interrupts without changing the debugged program at all.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of main parts showing an embodiment of an in-circuit emulator according to the present invention, and FIG. 2 is an operational flow for explaining the operation. 1... System CPU, 2... System bus, 3...
...System memory, 4...Bus controller, 5.
...Control circuit, 6...Bidirectional memory, 7...Memory, 8...Bus multiplexer, 11...Target CPU, 12...Target memory, 13...Target I 10° 1st figure

Claims (1)

[Claims] An in-circuit emulator is provided with a system memory that can be accessed by a system CPU, and a bidirectional memory that can be accessed by the system CPU and a target CPU, and when the system CPU executes a step operation, the following steps are performed. An in-circuit emulator characterized in that the in-circuit emulator is operated by disabling interrupts when executing a step operation. (1) Save the status register information of the target CPU in the bidirectional memory in advance. (2) The system CPU further saves the interrupt control flag in the save status register from the bidirectional memory to the system memory. (3) The system CPU causes the monitor program to obtain an instruction code for actually executing a step operation. (4) The monitor program obtains an instruction code from the target memory under the control of the target CPU and stores it in the bidirectional memory. (5) The system CPU refers to the instruction code stored in the bidirectional memory and saves it to the system memory. (6) Next, the system CPU masks the interrupt control flag of the status register stored in the bidirectional memory and instructs the monitor program to perform normal step operation. (7) Before the interrupt control flag is masked, it is in the canceled state, and the interrupt control flag is changed to the unmasked state only when an instruction that does not affect the interrupt control flag is executed.