JPS63236142A - Software monitoring device - Google Patents

Abstract

PURPOSE:To facilitate the debug by confirming the level and the number of the task that is presently carried out and restarting a CPU with a hardware break point kept as it is when said task level and number have changes. CONSTITUTION:A hardware breaking means 1 holds a program memory address corresponding to the task program step to be carried out by a single step preceding timing as a hardware break point. When said program memory address is coincident with another program memory address produced by translating the step which is presently executed, a CPU 2 is temporarily stopped. Then the task level and the task number of the current time point are confirmed together with the preceding task level and number. If these levels and numbers have changes, a process control part 6 restarts the CPU 2 with the hardware breaking point kept as it is. While the CPU 2 is stopped when said task levels and numbers have no change. As a result, a single step action is possible with no influence even when a task program having a high preference level has an interruption. Thus the debug is facilitated.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention provides a method for performing a single step on a specified task program within a machine system in which a multi-task program set at multiple levels is executed. The present invention relates to a software monitoring device that performs operations.

<Prior art> Recently, priority levels have been set for multiple task programs (communication programs, display programs, printing programs, etc.), and while one task program is being executed, another task with a higher priority level and a shorter processing time is - A multi-level, multi-task environment system with program interrupts is emerging.

On the other hand, logic development systems, logic development analyzers, etc. have been cited as software monitoring devices that monitor the progress of 6G programs in computer systems. Even if you try to use a task in a computer system with a multi-level environment, the lack of break conditions and trigger conditions prevents the task program being debugged from performing single-step operations as intended. could not.

That is, if a task program with a higher priority level than this task program interrupts at the step before the step of the task program to be stopped,
When a certain step in a task program with a high priority level is translated into machine language, the program memory address corresponding to this machine language instruction is the program memory address corresponding to the step of the task program to be stopped.
It may happen that the memory address coincides with the previous software [? Jail stops program progress at this point. For this reason, debugging is difficult because the program stops at a location that is not the desired stopping position or in a task program with a high priority level.

<Problem to be solved by the invention> The problem to be solved by the invention is that in a computer system under a multi-task, multi-level environment,
Even if a task program with a higher priority level than the specified task program interrupts, single step operation can be performed without any effect.
The purpose is to configure a software monitoring device that is easy to debug.

<Means for Solving the Problems> The present invention, which has solved the above problems, performs a single-step operation for a specified task program within a computer system in which a multi-task program set at a multi-level is executed. Software monitoring! In the device, a hardware break means for stopping the central processing unit by using a program memory address generated by translating a step to be executed one timing ahead one ift as a hardware break point, and a step currently being executed. address comparison means for providing a match signal to output a break signal from the hardware break means when a program memory address generated from the hardware break point is compared with the hardware break point;・Previous task level and task number and current task at the time of break
task recognition means for checking the level and task number;
a processing control unit that restarts the central processing unit while leaving the hardware break point unchanged if there is a change in the task level and task number at the time of the hardware break, and stops the central processing unit if there is no change; This is a software monitoring device equipped with:

<Operation> The software monitoring device of the present invention maintains the program memory address corresponding to the task/program step to be executed at the next timing as a hardware break point, and translates the step currently being executed. If the CPU matches the program memory address generated by the CPU, the central processing unit is temporarily stopped. Then, check the task level and task tS at this point and the previous task level and task number, and if there is a change, restart the central processing unit with the hardware breakpoint as it is, and if there is no change. Stop the central processing unit +L
let

Kumi/71! Example> FIG. 1 is a functional block diagram realizing a software monitoring device of the present invention.

In this figure, 1 is a hardware break program memory address that occurs when the step of a task program to be executed at the next timing obtained from the program counter of central processing unit CPU2 is translated into machine language.・Hardware break means that is held as a point and gives a hardware break signal (CPU stop signal) to the target central processing unit ff1cPLJ2, 3 is when the steps of the currently executing task program are translated into machinery This is an address comparison means that compares the program memory address given from bus B to the aforementioned hardware break point and outputs a match signal, and this configuration is equivalent to the functionality of a normal software monitoring device. be.

and 4, a task level recognition means in which the task level of the designated task program is set, and which detects a match between the task level of the currently executing task program and the set task level; is a task number recognition means in which the task number of a designated task program is set, and detects a match between the task number of the currently executing task program and the set task number. Here, the task level represents the processing priority of a plurality of task programs, and the task number identifies each program constituting the programs within the same task level.

Furthermore, 6 is a processing control section consisting of a ROM and storing the operating procedure of the apparatus of the present invention as a software algorithm.

Now, let's talk about the operation of the device of the present invention as described above! l! 1
According to the algorithm of tii control section 6, Fig. 1 and Fig. 2
This will be explained using the operating algorithm shown in the figure.

When the device starts operating, the task level of the designated task program is set in the task level recognition means 4, and the task number is set in the task number recognition means 5.

Then, the program memory address generated when the program step to be executed at the next timing obtained from the program counter of the CPU 2 is translated to the mechanic n is sent to the hardware break means 1.
Hold as a break point.

On the other hand, the program memory address corresponding to the currently executed program step is given from path B, and the address comparing means 3 compares this memory address with the hardware break point.

If they match, a match signal is given to the hardware break means 1, and the hardware break means 1 stops the CPU 2 at this point.

At this point, in order to determine whether the CPU 2 has broken normally or whether the CPU 2 has broken due to a task-level hardware interrupt or a task-level software interrupt, the task level recognition means 4 uses the set task Compare the level value with the task level value of the currently executing program step.

Furthermore, the task M month recognition means 5 compares the set task number value with the task number value of the program step currently being executed.

If there is a change in either the task level or task number 11, leave the hardware break point as is and run CPU2 until the point where the task level and task number 11 match. Repeat number comparison operation.

If there is no change in the task level or task No. 11,
It is assumed that CP LJ 2 has stopped normally.

FIG. 3 shows an example of the operation of the apparatus of the present invention as a time chart.

In this figure, the task program for the purpose of performing a single step operation is 5WI3 (to).

When the task program SW3 starts, the upper task level hardware interrupts HW[1, 2, 3 and software interrupts 5W11°2 ((a), (b),
(c), (d), (e)) occur. The order of interrupting these interrupt steps is a, b, c, d, e, f, g.
shall be.

Usually, ■−+ 6−+■−)i) −+ C−+ d
-16-+ f -+ Steps proceed in the order of g→■→■.

According to the invention, the above steps a, b, c, d, e, f are carried out while the task program 5WI3 is in progress.

Even if the CPU operation is stopped by a hardware break means due to interrupt No. 9, the task level and task number are checked and the CPU is run until the task level and task No. 1 match.

This operation causes interrupt step a.

Single step operation (■→■→■→0) of the task program SW3 is possible by ignoring b, c, d, e, f, and g.

In this way, the device of the present invention gives priority to the execution of a predetermined task/program, and even if there is an interruption of υJ with a higher bell,
Single step operation can be performed without being affected by this.

<Effects of the Invention> The software monitoring device of the present invention retains the program memory address corresponding to the task/program step to be executed at the next timing as a hardware break point, and If the address matches the program memory address generated by translating, the central processing unit is temporarily stopped, the current task level and task number are checked, and the previous task level and task number are checked. For example, the following effect can be obtained by restarting the central processing unit while leaving the hardware break point unchanged, and stopping the central processing unit if there is no change.

In other words, in a computer system in a multi-task, multi-level environment, single-step operations can be performed without being affected even if a task program with a higher priority level than the specified task program interrupts. , it is possible to configure a software monitoring device that is easy to debug.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram realizing a device embodying the present invention, and FIG. 2 is an algorithm representing the operation of the device of the present invention.
FIG. 3 is a time chart showing the operation of the apparatus of the present invention. DESCRIPTION OF SYMBOLS 1... Hardware break means, 2... Central processing unit CPLJ, 3... Address comparison means, 4...
Task level recognition means, 5... Task number recognition means, 6... Processing control unit RO
M. Broom 1 diagram

Claims (1)

[Claims] Translates the step that will be executed one step ahead in a software monitoring device that performs a single step operation for a specified task program in a computer system that executes a multi-task program set at multiple levels. The program memory address generated by the hardware. A hardware break means for stopping the central processing unit as a break point, and a program memory address resulting from the currently executed step and said hardware break point.
address comparison means for providing a match signal so that the hardware break means outputs a break signal if they match, and a previous task level and task number at the point of hardware break; a task recognition means for checking a task level and a task number; and a task recognition means for restarting the central processing unit while leaving the hardware break point unchanged if there is a change in the task level and task number at the time of a hardware break. A software monitoring device comprising: a processing control unit that stops the central processing unit if there is no change.