JPS59128640A - On-line tracing method in microprogram type computer - Google Patents

Abstract

PURPOSE:To execute efficiently the verification of task operation registered in a computer in continuous running by decomposing to set one step of an execution instruction into plural microinstructions, then discriminating whether a tracing condition is formed or not to process the microinstructions. CONSTITUTION:When a current execution address is applied by a status register in a CPU, processing D and T are executed simultaneously. In the processing D, an instruction is fetched and decomposed into plural microinstructions to set up and execute them. The processing T checks whether the trace mode of a register coincides with running or not, whether an objective trace No. coincides with a current task No. or not and whether an objective trace instruction code coincides with a current execution instruction code of not. If all the conditions coincide with each other, the formation of the trace conditions is decided and combined information consisting of the present task number, execution address and time is stored in a WCS. If any one of them is inconsistent, said information is not stored in the WCS, where the WCS is a writable control storage.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a tracing method for efficiently verifying task operations registered in a continuously operating computer.

When an abnormality is recognized in the operation of a task registered in a control computer that is connected to a plant and operates without stopping for 24 hours, it is often very difficult to investigate the cause. A single task operation alone will not cause an abnormality, but when two or more tasks operate multiple or in parallel, there is an extremely rare possibility that an abnormality may occur due to mutual causal relationships.

Therefore, the occurrence of an abnormality is random and may occur once a day, once a week, or once a month. Moreover, once such an abnormality occurs, it often has a serious negative impact on the plant, so in order to prevent this from happening, when the computer system is delivered, complicated procedures are carried out during the online operation of the computer system to verify that it operates correctly. There is a need for a method to accurately grasp the movements of tasks that are moving in unison. 0 (A) CALL the trace subroutine within the program.
With this method, the program can only trace the trace subroutine at one place, so in order to verify the task in detail, the trace subroutine must be called at many places, which increases the number of memories compared to the original program. Moreover, each time you call the trace subroutine, an extra burden is placed on the computer for the processing, which reduces the overall speed, and conversely, even though there is insufficient time for the original processing, tracing Sometimes the condition is delayed and is misdiagnosed as normal on the surface. Furthermore, to delete the originally built-in trace function or add a new trace function, the program must be modified to delete or insert the trace subroutine CALL.

Since it requires reregistration, it has the drawback of affecting the operation of the computer during continuous operation.

(B) Set the target trace address by setting one of the 9 cropping branches or unconditional jump instruction codes as trace key information, and set the current execution address or current instruction code as the trace key information for each step of the CPU level execution command. In this method, if there is a match, the CPU is interrupted.In this case, only one trace key information can be specified, and the disadvantage is that too much or too little trace information may be collected. The method could not effectively verify task behavior.

In order to eliminate the above-mentioned drawbacks, the present invention makes use of the time it takes to break down and execute one step of a CPU-level execution instruction into a plurality of microinstructions in a microprogram computer, and in parallel, the trace mode, task number, instruction code, etc. It is determined whether the trace condition consisting of an address is "true" or "not true", and if it is "true", the combination information of task number 2 address and time is sent to W.
It is accumulated and saved in the CS to start the execution of the command, but when the result is not established, nothing is done and the execution of the command is started, which will be explained in detail below.

In Figure 1, 1 is the computer's CPU (central processing unit)
, 2 is MEM (main memory), 3 is WCS (Writer
ble Control Storage), and the clock is omitted. As is well known, in a microprogram type computer, the contents of the instruction counter of the CPUI indicate the address on MEM2 to be executed next, and the CPU level instructions stored at this address are broken down into a group of WCS3 microinstructions, The structure is such that CPU-level instructions are executed by executing this group of instructions.

Figure 2 shows the data array of the CPU register when using the trace mode, target trace\task number, and target trace instruction code as trace key information, and Figure 3 shows the data array of the CPU register to be traced using the trace key information.
The microinstruction expansion procedure for one step of the PU level execution command is shown. Figure 6-2 shows a case where all registers are used, and in trace mode, for example, the status register of the CPU is used. C.P.
When the current execution address of U is given by a known method, the processing of T is performed in parallel, as shown by the dotted line. Here, D; the instruction is fetched, decoded, decomposed into a plurality of microinstructions, and then executed.

T: Does the trace mode stored in the register (for example, 1-bit information of the cPU status register) match "1 operation"? Does the register's purpose trace task number match the register's current task number? Check whether the purpose trace instruction code of the register matches the currently executed instruction code of the register. If all 7 match, the trace key information is determined to be "established" and the current task number, current execution address, and time (clock information) are determined. The combination information (time 9 minutes) is stored in the WCS in an endless cyclical manner, but if even one item does not match, the combination information is not stored in the WCS. This storage method will be described later.

CP after taking the start at the end of the two processes D and T.
One step of the execution instruction of U is completed, the next execution address of the CPU is determined, and the process is repeated in the same manner. In this case, the information as to whether the trace mode is "run" or "stop", the target trace task number, and the target trace command code must be stored in each register in advance as a separate CPU-level execution command.

As another example, FIG. 4 shows the data arrangement of the WCS and CPU registers when a trace mode, a target trace task number, and a plurality of target trace addresses are used as trace key information, and FIG. 5 shows the trace key information. This section shows the microinstruction expansion procedure using . This is different from the trace key information used in Figure 3 in that multiple target trace addresses are used instead of one target trace instruction code, so any one of these traces 1H4k and the current execution address It is necessary to check the match by loading the target trace address from the WC 8 multiple times, but the other processing is completely the same between FIG. 3 and FIG. 5. Of course, the trace key information must be stored in a register or WCS in advance. In Figure 4, the red stamp is W.
CS, all others use registers, and trace mode uses the CPU status register, for example. By assigning, multiple task numbers can be used as trace information without having to specify them individually.

Furthermore, even if the task is non-resident in main memory (a task that is always stored in auxiliary memory and loaded into main memory during operation), if various tasks are running in the same main memory area in a time-sharing manner, the task number cannot be changed. By selecting it as one of the trace key information, only the operation of the target task can be extracted and traced.

The trace key information may be stored before the initial startup of the computer, or the free time of the computer during continuous operation may be stored at W.
Use CS. When the computer is initially started, data is stored from the beginning of the area at 9-, but after that, trace results are accumulated and the storage progresses to the end of the area. It is done cyclically. The shaded area in the figure stores the trace results currently being executed, and the other areas store the past trace results. This area can be read from the CPU, and the results can be output to a typewriter or the like at any time.

In FIG. 7, task A calls subroutine B as a target trace task, and it is well known that subroutine B is also regarded as task A. When the tracing method of the present invention is applied to this task A, as shown in Figure 8-1, rAJ is specified as the target trace task number in the trace key information, and [condition is branch instruction code] is specified as the target trace instruction code. Sometimes (a), ( in Figure 7)
When task A is executed following the course of b), the trace results are as shown in Figure 8-2. Also the 9th
-1 As shown in figure 1, "A" is the target trace task number in the trace key information, and "Igo3J = rlQ4J t rl" is the target trace 10- address.
When CsJ-rl (!6J is specified, the trace results when task A is executed following the courses (a) and (b) in Figure 7 are shown in Figures 9-2 and 9-3, respectively. In the example shown in Figure 9-1, the trace key information area is fixed at 8 words, and the number of target trace addresses is 6 at maximum.
Therefore, if the required number of addresses is less than this, for example, -1 may be stored as a value indicating unused. Furthermore, in order to further increase the number of target trace addresses, the trace key information area may be determined to be large when designing the WC8. If time information is stored together with the trace results, task verification can be performed with reference to the temporal changes in the operating status. To end the trace and return to normal execution, you can write the trace mode "stop" information in another task.

According to the present invention, it is possible to verify the operation of a task under test and perform failure analysis on a computer that is in continuous operation in an operating state close to its original processing state. It goes without saying that 11-task verification can be performed using this method even when the computer is not in continuous operation. It is also effective at the system creation stage as a debugging means and for storing test result information.

[Brief explanation of drawings]

Figure 1 is a schematic diagram of the configuration of a microprogram type computer. 2 and 4 are arrangement diagrams of the trace key information in the WC8 and registers, and FIGS. 3 and 5 are developed diagrams of the microinstruction procedure corresponding to the trace key information according to FIGS. 2 and 4, respectively. Figure 6 is a trace result storage status diagram, Figure 7 is a flow diagram of an example task for explaining tracing, Figure 8-1,
Figure 9-1 is an array diagram of an example of trace key information for tracing the task in Figure 7; Figure 8-2 is an array diagram of trace results using the trace key information in Figure 8-1; −
2 and 9-3 are array diagrams of trace results using the trace key information of FIG. 9-1. 1...CPU (Central Processing Unit) 2...MEM (Main Memory) T j Diagram T 2 Diagram 4 Diagram Procedure Correction Written Movement 1. Incident display Tokugan Sho\t, 5--, 37702
, Title of the invention 4.17) (1-')・dσ PANO MU SAKE 4 KITE INEI -/k V-TEEI 3. Relationship with the person making the amendment Applicant 4, Agent Address: 1111-1-5, Tanabe Shin, Kawasaki-ku, Kawasaki City, Weight of the amendment order: Showa Ha δ Years and Months z6 [216, Number of inventions to be increased by the amendment Contents of the amendment 1, Figure 6 of the drawings, Kame\\ka (2) Figures 9-2 and 9-3 are attached to Figure 6! IN %'i3 surprise 9th
Correct as shown in Figure-2 and Figure 9-3. I℃Patent Attorney Yamaguchi Suma, 3j-6 Figure O'? -2 flash + (? - 3 figure procedural amendment axis) May 26, 1980 1, Display of the case Tokkun Sho \ Subaru - 37764 arc ρ impingement V shi・5-masu 4, generation Address: Shin Tanabe II'11-1-8, Kawasaki-ku, Kawasaki City
Contents of the amendment As shown in the attached document, the content of the amendment (■) uses the rwcs on page 9, line 20 of the specification. "and"
``The information content consists of the current task number and the current execution address 9 o'clock.'' is inserted between ``At initial startup of the computer''. 2. Please refer to the drawing No. δ-2 with the correct appearance ■ Attorney Patent Attorney Yamaguchi Kaoru 237-

Claims (1)

[Claims] 1) A clock and a W C in the CPU (Central Processing Unit)
S (Writable Control Stora
In the online tracing method of a microprogram computer with
Fetch the step, set it to break it down into multiple microinstructions, and execute it; in parallel, use another microinstruction to determine whether the trace condition is ``true'' or ``untrue.''
is determined, and when it is "established", the combination information of the current task number, current execution address, and current time at the CPU level is sent to the WC8.
A microprogram type computer is characterized in that it stores data in an endless cyclical manner, but does not store data when the result is "unsatisfactory"; after taking steps to complete the two processes, it proceeds to the next execution instruction step at the CPU level. online tracing method. 2) Using 5 of the CPU registers, [operation],
A trace mode consisting of two values of "stop", a current task number, a current instruction code, a target trace task number, and a target trace command code are stored in advance, and the CPU level execution command 1 For each step, if it is determined by the microinstruction that the trace mode is "Run" and the combination information of the current task number and current instruction code matches the combination information of the target trace task number and target trace command code, the trace condition " 1. An online tracing method for a microprogram computer according to claim 1, characterized in that: 3) Using four of the CPU's registers, "operate",
A trace mode consisting of two values of "stop", a current task number, a current execution address, a target trace task number, and a plurality of target trace addresses are stored in the WC8 in advance. For each step of the execution instruction at the CPU level, the microinstruction determines that the trace mode is "running", the current task number matches the target trace task number, and the current execution address matches one of the target trace addresses. For example, an online tracing method for a microprogram computer according to item 1 of the patent scope, characterized in that the tracing condition is "satisfied."