JPS6356569B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an emulator.
In particular, it is equipped with a bus switching unit, and under the control of the bus switching unit, bus switching is performed between the common bus for emulation memory, tracer, and monitor and the emulation CPU bus or support CPU bus. The present invention relates to an emulator in which an emulation memory, a tracer, or a monitor can be accessed through a common bus.

In recent years, microprocessor-applied equipment has rapidly developed and has come to be used in all fields. Emulators help microprocessor application devices achieve their intended goals in a short period of time. Emulators operate microprocessor application devices in real time, making it easy to find bugs and debug tasks in programs and hardware being developed. I'm used to it.

A conventional emulator has a configuration as shown in FIG. That is, the main CPU 1 accesses the emulation memory 3, tracer 4, and monitor 5 that constitute the emulator via the main CPU bus 6, while the emulation CPU 2, which acts as a CPU to be installed in the target system 7, also accesses the emulation memory 3, tracer 4, and monitor 5 that constitute the emulator. The emulation memory 3, tracer 4, and monitor 5 were accessed via the CPU bus 8.
For this reason, two buses, a main CPU bus 6 and an emulation CPU bus 8, are connected to the emulation memory 3, tracer 4, and monitor 5, respectively, resulting in a disadvantage that the number of physical wires increases. As the number of bits of the CPU used increases, the number of bus wiring increases accordingly, and this drawback becomes more serious. In addition, the emulation memory 3, tracer 4, and monitor 5 are each equipped with a bus switching circuit, and the emulation memory 3 must have a mapping circuit and an access target determination circuit. When adding the mapping circuit and the access target determination circuit, their management was complicated.

Moreover, main CPU1 and emulation CPU
There may be an access conflict with 2.
In order to accommodate this, each device had to have a complicated bus switching circuit.

The emulation memory 3 is a storage device that stores the program of the target system 7, that is, the user program under development, and the tracer 4 records the execution history of the emulation CPU 2 from the time when specified conditions are met, i.e. This is a device that traces the state of the bus at specified cycles, such as machine cycles and bus cycles. In addition, the monitor 5 has the function of stopping the user program and stores the monitor program that is executed by the emulation CPU 2 when the user program is stopped.
This device is equipped with a memory that stores information exchanged with the CPU 2.

The present invention aims to solve the above-mentioned drawbacks and provides support for managing emulators.
In addition to providing a CPU, a bus switching section is also provided, and emulation memory, tracer, and monitor are installed in one
The object of the present invention is to provide an emulator that can be connected to a target system via a common bus and can emulate a target system via the common bus. The present invention will be described below with reference to FIG. 2 and subsequent drawings.

Here, FIG. 2 is a block diagram of the emulator according to the present invention, FIG. 3 is a diagram explaining the basic principle of the emulator according to the present invention, FIG. 4 is the configuration of an embodiment of the address bus and data bus switching circuit, and FIG. The figure shows the configuration of one embodiment of the bus switching section, Figures 6 to 8 are time charts when a request to use the common bus of the emulation CPU occurs, and Figures 9 and 10 show the connection between the emulation CPU and the support CPU. This shows a time chart when a conflict of requests to use the common bus occurs.

In the configuration diagram of the emulator according to the present invention shown in FIG. 2, numerals 1, 2, and 7 correspond to those in FIG. Support CPU 9 is the main CPU that manages the entire emulator of the present invention and manages the entire system.
It is located under CPU1. Bus switching section 10
Supports CPU9 or emulation CPU
When a request to use the common bus is received from 2, bus switching between the common bus 11 and the support CPU bus 12 or the emulation CPU bus 13 is performed.
Normally emulation CPU2 side is supported CPU
It has priority right to use the common bus 11 over the 9 side. An emulation memory 14, a tracer 15, and a monitor 16 are connected to the common bus 11.
When an access conflict occurs between the CPU 9 and the emulation CPU 2, the conflict is resolved by the arbitration function of the bus switching section 10 using the method shown in FIG.

The emulation memory 14, tracer 15, and monitor 16 are configured to allow high-speed access.

Figure 3 shows emulation CPU 2 accessing target system 7 and tracer 15.
When traces the execution history of the emulation CPU 2, it shows the occupancy status of the common bus 11 of the emulation CPU 2. In this case, the emulation CPU 2 occupies the common bus 11 at the beginning and end of one machine cycle.
When the emulation CPU 2 occupies the common bus 11, E is shown, and when the emulation CPU 2 is not using the common bus 11, it is shown S (hereinafter, the same applies to FIG. 3).

FIG. 3 shows the occupancy status of the common bus 11 when the emulation CPU 2 is accessing the emulation memory 14. In this case, the access of the emulation CPU 2 to the emulation memory 14 is completed early, and the common bus 11 is released as soon as the access is completed.

FIG. 3 shows the occupancy status of the common bus 11 when the emulation CPU 2 accesses the target system 7 and the tracer 15 is not tracing the movement of the emulation CPU 2. In this case, while the emulation CPU 2 is determining whether it is accessing the target system 7 or the emulation memory 14, the emulation CPU 2 side occupies the common bus 11 and the emulation CPU 2 side occupies the common bus 11.
When it is determined that the CPU 2 is accessing the target system 7, the common bus 11 is released.

An embodiment of the configuration of the bus switching section 10 in which such switching of the common bus 11 is performed will be described with reference to FIGS. 4 and 5.

FIG. 4 shows the configuration of an embodiment of the address bus and data bus switching circuit when a 16-bit microprocessor is used as the emulation CPU.

In the same figure, 17B is a mapping circuit, 18
23 to 23 are buffer circuits with tri-state output, 24 and 25 are latch circuits with tri-state output, 26 to 29 are negative logic NAND circuits, 30,
31 represents an inverter circuit. These buffer circuits 18 to 23 and latch circuit 2
4 and 25 pass address and data in the direction of the arrow shown in each circuit.

The mapping circuit 17B includes an emulation
Emulation CPU 2 via CPU bus 13
Among the addresses 0 to 23, emulation CPU addresses (hereinafter abbreviated as EAD) 14 to
23 is input, the mapping circuit 17B converts the virtual address into a real address, and outputs the converted address to the buffer circuit 18. Among addresses 0 to 23 from emulation CPU2,
The virtual addresses of EAD0 to 13 are buffer circuit 2
Enter 0. When the bus switching unit 10 detects that the emulation CPU 2 uses the common bus 11, the control circuit 32 shown in FIG.
20 to emulator access on (hereinafter referred to as EAON)
A signal (abbreviated as ) is output (it becomes active when the logic is "L". The same goes for other signals), and as a result, the EAD14 to EAD input to the buffer circuits 18 and 20
23, EAD0-13 pass through the respective buffer circuits 18, 20 and become addresses (hereinafter abbreviated as AD) 0-20. Also, among EAD0-23, EAD14-- which is input to the mapping circuit 17B.
23 is input to the buffer circuit 19, and this
EADs 14 to 23 pass through the buffer circuit 19 without undergoing address conversion to become non-map addresses (hereinafter abbreviated as NMPAD) 0 to 9, and are supplied to the tracer 15. When the bus switching unit 10 detects that the support CPU 9 uses the common bus 11, the support access is turned on (hereinafter referred to as "on") from the control circuit 32 shown in FIG.
(abbreviated as SAON) signal is output. As a result, the support input to the buffer circuit 21
CPU address (hereinafter abbreviated as SAD) 0 to 20
passes through the buffer circuit 21 and outputs AD0 to AD20.
becomes. Emulation CPU2 and support
Even if there is a conflict with the CPU 9 for a request to use the common bus, the control circuit 32 shown in FIG.
Either EAON signal or SAON signal is output, emulation CPU2 and support CPU9
The address bus is switched by the bus switching unit 10 without causing an address conflict between the address bus and the address bus.

Data bus switching is performed as follows.
That is, when transferring data from the emulation CPU bus 13 to the common bus 11, when the bus switching unit 10 detects that the emulation CPU 2 uses the common bus 11, a common bus use request (hereinafter abbreviated as EBUSRQ) signal is sent to switch the bus. Part 1
0, and the control circuit 3 shown in FIG.
2, the above-described EAON signal, data strobe (hereinafter abbreviated as DS) signal, and read/write (hereinafter abbreviated as R/W) signal, in this case the W signal, are output. As a result, an enable signal is sent from the negative logic NAND circuit 26 to the buffer circuit 22, and the emulation CPU data (hereinafter abbreviated as EDATA) 0 to 15 of the emulation CPU bus 13 is transferred to the data bus of the common bus 11 via the buffer circuit 22. Data (hereinafter abbreviated as DATA) is carried as 0 to 15.

Conversely, from common bus 11, emulation
When the bus switching unit 10 detects that the emulation CPU 2 uses the common bus 11 when transferring DATA0 to 15 to the CPU bus 13,
The EBUSRQ signal is generated in the bus switching unit 10,
R/W signal from the control circuit 32 shown in FIG.
In this case, the R signal and the emulation CPU data clock (hereinafter abbreviated as EDCLK) signal are output.

EBUSRQ signal and emulation CPU bus 1
The latch circuit 24 is output from the negative logic NAND circuit 27 by the read signal No. 3 (hereinafter abbreviated as ER signal).
is enabled and DATA0-15 are placed on emulation CPU bus 13, but EDCLK
Since DATA0 to 15 of the common bus 11 are latched to the corresponding latch circuit 24 by the signal, EDCLK
The contents of DATA0-15 when the signal is latched are held. Then, DATA 0 to 15 latched by the latch circuit 24 are taken into the emulation CPU 2 at operation timings to be described later.

Data bus switching for the support CPU 9 is also substantially the same as for the emulation CPU 2. i.e. support CPU9
side buffer circuit 23, latch circuit 25, negative logic NAND circuits 28, 29, and inverter circuit 31
are the buffer circuit 22, latch circuit 24, negative logic NAND circuit 26, and
27 and the inverter circuit 30, respectively,
The SAON signal output from the control circuit 32 in FIG.
Support CPU bus request (hereinafter abbreviated as SBUSRQ) signal, support CPU data clock (hereinafter abbreviate as SDCLK) signal, support CPU
Bus 12 read signal (hereinafter abbreviated as SR signal)
is the EAON signal, EBUSRQ signal, EDCLK signal,
Each corresponds to the ER signal. EAON signal and
SAON signals are not output simultaneously from the control circuit 32, and therefore EDATA0 to 15 of the emulation CPU bus 13 are output from the common bus 11.
DATA0 to 15 and vice versa DATA0 to 1
5 is EDATA to emulation CPU bus 13
Data bus switching from 0 to 15 and support CPU
Bus 12 support CPU data (SDATA
) 0 to 15 are DATA of common bus 11
The switching of the data buses from DATA 0 to 15 to SDATA 0 to 15 and vice versa to the supported CPU bus 12 is performed without conflict.

FIG. 5 shows the configuration of an embodiment of the bus switching section. 17A is an access target determination circuit, and the emulation CPU 2 accesses the common bus 11.
After a predetermined period of time has elapsed, it is determined whether or not to use the common bus 11.
(abbreviated as MAPON) signal is set to "L", and when accessing the target system 7, outputs "H".

Reference numeral 32 denotes a control circuit which outputs and controls each of the control signals described above to the address and data bus switching circuit 33 as described in FIG. In addition,
Since the control circuit 32 requires high-speed operation, it is composed of a gate circuit or the like.

Reference numeral 33 denotes an address and data bus switching circuit having the circuit configuration described in FIG. 4.

FIG. 6 shows a time chart when the emulation CPU 2 is accessing the target system 7 side and the tracer 15 is tracing, when there is no request to use the common bus from the support CPU 9.

When the EBUSRQ signal is generated in the bus switching unit 10,
The EAON signal is output from the control circuit 32, the buffer circuits 18 and 20 are enabled, and the emulation CPU 2 occupies the common bus 11 during the period shown in FIG. Since the access target determination circuit 17A does not output the MAPON signal even after a predetermined period of time has passed after outputting the EAON signal, that is, even after the period shown in the figure, the emulation CPU 2
The control circuit 32 determines that the access is from the target system 7 side, and the emulation
The CPU 2 releases the common bus 11. This opening of the common bus 11 continues for the period shown in the figure, and the common bus 11 is idle. As will be described later, if there is an access conflict between the emulation CPU 2 and the support CPU 9, the support CPU 9 can use the common bus 11 by utilizing this free time.

In the case of FIG. 6, the tracer 15 traces the execution history of the emulator CPU 2, so when all the bus information (address, data, control) is determined, the control circuit 32 outputs the EAON signal again, and the R/W signal and DS signal are output. This enables the buffer circuit 22, and the data obtained by the emulation CPU 2 accessing the target system 7 side.
EDATA0-15 are transferred to DATA0-15 of the common bus 11 via the buffer circuit 22. At the same time, buffer circuits 18 and 20 are enabled and address information is also output (see the same figure). In other words, emulation CPU 2 is connected to common bus 1 again.
Occupies 1. At this time, acknowledge (hereinafter referred to as ACK)
A signal (abbreviated as ) is output from the control circuit 32,
This signal causes the tracer 15 to take in bus information.

Note that the six signals A in the same figure are the bus switching unit 10.
The five signals in B are the signals in the common bus 11.
This is the signal.

FIG. 7 shows a time chart when the emulation CPU 2 uses the common bus 11 as a read cycle when there is no request from the support CPU 9 to use the common bus.

When the ESUBRQ signal is generated in the bus switching unit 10,
The EAON signal is output from the control circuit 32, the buffer circuits 18 and 20 are enabled, and the emulation CPU 2 connects to the common bus 1 as shown in FIG.
Occupies 1. Then, after a predetermined period of time has elapsed after the EAON signal is output, the access target determination circuit 17A
MAPON signal is output. As a result, the control circuit 32 determines that the emulation CPU 2 uses the common bus 11, and the emulation CPU 2 continues to occupy the common bus 11 (see the figure). For example, when the emulation CPU 2 performs read access to the emulation memory 14, EAD14 of EAD0 to EAD23
Read access to the emulation memory 14 is performed using addresses AD0 to AD20, which are obtained by converting the virtual addresses AD0 to AD23 into real addresses by the mapping circuit 17B. The emulation memory 14 uses a high-speed memory, and the contents stored on AD0 to AD20 are immediately transferred to DATA.
They are placed on the common bus 11 as numbers 0 to 15. Then, the ACK signal is sent from the emulation memory 14 to the bus switching unit 10, and the enabled latch circuit 24 receives the EDCLK signal.
DATA0-15 are latched (Figure 7). After this latch, the common bus 11 of the emulation CPU 2 is released as shown in the figure.
Then, at a predetermined operation timing of one machine cycle of the emulation CPU 2, the latch circuit 2
The emulation CPU 2 reads DATA0-15 latched to 4 as EDATA0-15. The emulation CPU 2 apparently uses the emulation memory 14 during normal operation timing.
However, the read access to the emulation memory 14 is completed extremely quickly, and as explained above, the read access to the emulation memory 14 is completed extremely quickly.
The second half of the machine cycle is an idle time when the common bus 11 is not used. Emulation
When an access conflict occurs between the CPU 2 and the support CPU 9, the support CPU 9 can use the common bus 11 by utilizing this free time.

In the figure, the seven signals (a) are signals within the bus switching unit 10, and the six signals (b) are signals from the common bus 11.

FIG. 8 shows a time chart when the emulation CPU 2 uses the common bus 11 as a write cycle when there is no request from the support CPU 9 to use the common bus.

When the EBUSRQ signal is generated in the bus switching unit 10,
In response to this, the control circuit 32 outputs the EAON signal, enabling the buffer circuits 18 and 20, and the emulation CPU 2 as shown in FIG.
occupies the common bus 11. Then, after a predetermined period of time has elapsed after the EAON signal is output, the access target determination circuit 17A outputs the MAPON signal. As a result, the control circuit 32 determines that the emulation CPU 2 uses the common bus 11, and the emulation CPU 2 continues to occupy the common bus 11 (FIG. 8). For example, when the emulation CPU 2 performs write access to the emulation memory 14, the mapping circuit 17B converts the virtual addresses of EADs 14 to 23 of EADs 0 to 23 into real addresses.
AD0 to AD20 are placed on the common bus 11 via the buffer circuits 18 and 20.

On the other hand, EDATA0 to 15 to be written outputted from the emulation CPU 2 are sent to the control circuit 32.
When the buffer circuit 22 is enabled by the DS signal output by
It can be put on 1. Immediately, the address of the emulation memory 14 operating at high speed is
DATA0-15 are written on AD0-20. As a result, from emulation memory 14
The ACK signal is sent to the bus switching unit 11, and from then on, as shown in the figure, the emulation CPU
2 releases the common bus 11.

Generally, the CPU outputs the data to be written immediately after outputting the address, so that the write process to the emulation memory 14 can be completed quickly. Therefore, compared to the normal operation timing of the emulation CPU 2, the second half of one machine cycle becomes an idle time when the common bus 11 is not used, as in the case of the read described above with reference to FIG. Emulation CPU2 and support CPU9
When an access conflict occurs between the support CPU 9 and the common bus 11, the support CPU 9 uses this free time to
can be used.

In the figure, the seven signals (a) are signals within the bus switching unit 10, and the six signals (b) are signals from the common bus 11.

Next, the concept of the operation when a conflict occurs between the emulation CPU 2 and the support CPU 9 for a request to use the common bus will be explained using the time charts shown in FIGS. 9 and 10.

In FIG. 9, the bus switching unit 10 outputs EBUSRQ.
When the signal is generated, the control circuit 32 outputs the EAON signal, and as explained above, the emulation
The CPU 2 occupies the common bus 11 (FIG. 9).
During the period shown in FIG. 9, the bus switching unit 10
Even if the SBUSRQ signal is generated, the control circuit 32
Since the SAON signal is not output, the emulation CPU 2 continues to occupy the common bus 11. Then, an ACK signal is sent to the control circuit 32, whereby the EAON signal disappears, that is, it is inverted from "L" to "H", and the emulation CPU 2 releases the common bus 11. Control circuit 32 immediately
outputs the SAON signal, and the support CPU 9 occupies the common bus 11. And in the bus switching section 10
When the EBUSRQ signal is generated, the emulation CPU 2 has the right to preferentially use the common bus 11 if the support CPU 9 has not completed the bus cycle of the common bus 11 by then (Figure 9). Therefore, the control circuit 32
Outputs the EAON signal and eliminates the SAON signal. In other words, from "L" to "H"
SAON signal is inverted. This also causes the ACK signal to disappear. While the common bus 11 of the emulation CPU 2 continues to be occupied (FIG. 9), the SBUSRQ signal is still output from the control circuit 32 because the machine cycle of the support CPU 9 is not completed. Emulation CPU
When the common bus 11 of 2 is released, the SAON signal is output from the control circuit 32 again, and the support
CPU2 occupies the common bus 11 (Figure 9),
Run that machine cycle. Support CPU
When the second machine cycle is completed, the control circuit 32
An ACK signal is sent to the control circuit 32.
will eliminate the SAON signal. When the emulation CPU 2 and the support CPU 9 conflict in requests to use the common bus 11 in this way, the emulation CPU 2 utilizes the free time when the common bus 11 is not occupied as explained in FIG.
Bus switching is performed in which the support CPU 9 occupies the common bus 11.

Figure 10 shows emulation as in Figure 9.
This is a detailed time chart when there is a conflict between CPU 2 and support CPU 9 for requests to use the common bus.
This is a case where the machine cycle is not completed while the emulation CPU 2 occupies the common bus 11, and the figure shows the period when the emulation CPU 2 occupies the common bus 11 and completes the machine cycle. Each represents a case where the common bus 11 is occupied and the machine cycle is completed.

Note that the above explanation uses a 16-bit microprocessor as an example;
The number of bits of the CPU 2 is not limited to this, and a microprocessor having an arbitrary number of bits may be used. The number of lines of the address bus and data bus changes accordingly.

As explained above, according to the present invention, (1) By providing a bus switching section and performing bus switching, only one common bus is required, and the number of bus line wirings can be reduced, so that emulation CPU
The effect becomes more pronounced as the number of bits increases.

(2) And the emulator of the present invention supports
Since it is equipped with a CPU, it can be separated from the main CPU and used as a standalone product.

(3) Also, since bus switching is performed in the bus switching section,
Emulation memory, tracer, and monitor devices include emulation CPU and main
This eliminates the need for a complex switching circuit that deals with contention for access with the CPU, and at the same time reduces the number of buffer circuits.

(4) Furthermore, by providing the mapping circuit and access target determination circuit, which were conventionally provided in the emulation memory, in the bus switching section, (a) the map output can be output faster.

(b) Since it is no longer accessed by both the emulation CPU and the main CPU, the configuration of the emulation memory becomes simpler.

(c) Support provided below the main CPU
It becomes easier for the CPU to manage the entire emulator.

(d) Emulation memory can be easily increased.

There are other effects.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a conventional emulator, Fig. 2 is a block diagram of an emulator according to the present invention, Fig. 3 is a diagram explaining the basic principle of the emulator according to the present invention, and Fig. 4 is an address bus and data bus switching circuit. Figure 5 shows the configuration of one embodiment of the bus switching section, and Figures 6 to 8 show the emulation.
Time charts when a CPU common bus usage request occurs, Figures 9 and 10 are for emulation.
It shows a time chart when a conflict for a request to use the common bus occurs between the CPU and the support CPU. In the figure, 1 is the main CPU, 2 is the emulation CPU, 3 is the emulation memory, 4 is the tracer, 5 is the monitor, 6 is the main CPU bus, 7
is the target system, 8 is the emulation
CPU bus, 9 is a support CPU, 10 is a bus switching unit, 11 is a common bus, 12 is a support CPU bus,
13 is an emulation CPU bus, 14 is an emulation memory, 15 is a tracer, 16 is a monitor, 17A is an access target determination circuit, 17B is a mapping circuit, 18 to 23 are buffer circuits, 24 and 25 are latch circuits, and 26 to 23 are buffer circuits. 29 is a negative logic NAND circuit, 30 and 31 are inverter circuits, 32 is a control circuit, and 33 is an address and data bus switching circuit.

Claims (1)

[Claims] 1. CPU to be installed in the target system
an emulation CPU that acts on behalf of the target system; an emulation memory that stores the program of the target system; a tracer that traces the execution history of the emulation CPU every specified cycle from the point when specified conditions are met; and a monitor program. and a monitor for storing information exchanged between the emulation CPU and the main CPU, and the emulator has a configuration in which the emulation CPU accesses the target system in place of the CPU to be installed in the target system, When emulating the target system, the main CPU
Support CPU to manage the emulator under
and; a common bus connected to the emulation memory, tracer, and monitor; and switching the common bus to either the emulation CPU bus connected to the emulation CPU or the support CPU bus connected to the support CPU. conduct,
When a conflict occurs between the emulation CPU and the support CPU for requests to use the common bus, priority is given to the emulation CPU bus to control the common bus occupancy, and the emulation
When the CPU once releases the common bus occupation after executing a specified process, the supporting CPU
An emulator equipped with a bus switching unit on the bus side that controls switching of common bus occupancy. 2. The emulator according to claim 1, wherein the support CPU has the functions of a main CPU and manages the emulator. 3. The emulator according to claim 1 or 2, wherein the bus switching unit includes a mapping circuit, and the mapping circuit performs address conversion before accessing the emulation memory. . 4 The bus switching section is an emulation CPU.
an access target determination circuit that determines whether or not access uses a common bus; emulation;
An address and data bus switching circuit having an access time conversion function that shortens the usage time of the common bus while each CPU processes with its own access time when the CPU or support CPU uses the common bus; 4. The emulator according to claim 1, further comprising a control circuit that controls a bus switching circuit.