JPH01217524A - Data processing system - Google Patents

Abstract

PURPOSE:To attain the display, etc., of a vicariously executing memory without affecting the execution of a user program and to secure immediacy by dividing an emulation memory into plural memory banks and controlling accesses to respective memories. CONSTITUTION:The emulsion memory, which stores the user program to be executed by a target processor TMPU and data, is divided into two memory banks EMEM0 and EMEM1. The EMEM0 is allocated to an even number address space and the EMEM1 is allocated to an odd number address space for the respective memory banks even with being observed from either the TMPU to a host processor HMPU. Namely, the bank to be accessed by an even number address can be accessed from the HMPU during the access of the odd number address of the TMPU and the bank to be accessed by the odd number address of the TMPU can be accessed from the HMPU during the access of the even number address. Accordingly, without stopping the operation of the TMPU, the access can be executed from the emulation memory from the HMPU.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system debugging technique and a technique for evaluating the efficiency of a program to be debugged, and relates to a technique that is effective when applied to, for example, an in-circuit emulator. It is something.

[Prior Art] In the development of microcomputer application equipment, in-circuit emulators are used to debug the application system and perform detailed evaluation of the system. Decline in-circuit emulator 2 is the second
As shown in the figure, a microcomputer (target microcomputer) is connected between a system development device 1 such as a parent computer (host computer) for software development and an application device 3 under development, and is included in the application device 3. It is a microcomputer system development tool that acts as a debugger and supports detailed system debugging. .

As shown in FIG. 3, a conventional in-circuit emulator includes a slave microcomputer 11 for emulation that performs the functions of a target microcomputer, an emulation control unit 12 for realizing emulation and various debugging functions, and a program controller. A breakpoint control unit 13 that sets execution or trace stop conditions and stops the program or trace when the conditions are met, a trace memory unit 14, and is lent when the application equipment (user system) memory is not available. Proxy memory section 15.3 includes a built-in serial interface 16 for data communication between the computer and the microcomputer, a mask microcomputer 17 for controlling them, and the like. (Refer to "rLSI Handbook" published by Ohm Publishing, November 30, 1980, p.562 to p.563).

In such an incircler emulator, the slave microcomputer 11 can be connected to a target microcomputer by connecting the tip of a cable 4 extending from the main body to a socket 71 for a target microcomputer provided in an application device. It has an emulation function that takes over the functions of a computer. Furthermore, it is equipped with a trace function that samples various data and status signals during emulation execution and stores them in a trace memory 15, etc., and a break function that stops the control operation of the application equipment by the slave microcomputer 11. By using these functions to acquire trace data and analyzing it, it is possible to debug application systems and user programs.

[Problem to be Solved by the Invention] When a conventional emulator displays or changes the contents of a proxy memory in which a user program or data is stored, the execution of the user program by the target processor is temporarily interrupted and the host Delegated memory had to be accessed by the processor or target processor.

Therefore, in the conventional method, if the contents of the proxy memory are displayed or changed during emulation, the user program will stop, and if the target microcomputer is controlling a servo motor, the motor may run out of control. If data is being transferred, an overrun error may occur and important data may be lost, or in a system that uses a watchdog timer, a timeout may cause the system to jump to an interrupt routine, leaving the system in a state where it is difficult to recover. There was a problem that there was.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

An object of the present invention is to ensure real-time performance in an emulation system by making it possible to display and change proxy memory without affecting the execution of a user program.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, it takes over the memory of the system that is the target of emulation, divides the memory in which the program to be debugged is stored into two banks, and
A multiplexer is added to each bank so that it can be accessed from either the host processor or the target processor, and this switching is performed by the lowest address signal output from the target processor.

[Action Co. Banks accessed by even addresses are:

Can be accessed by the host processor while accessing odd addresses of the target processor.

Banks accessed by odd addresses of the target processor can be accessed by the host processor while accessing even addresses, so the emulation memory can be accessed by the host processor without stopping the operation of the target processor. .

[Example] An embodiment of the present invention will be described below.

First, the configuration of the emulator system according to this embodiment is explained in the first section.
The explanation will be given according to the block diagram shown in the figure.

In FIG. 1, the symbol HMPU is shown as
This is a host processor that controls the entire emulator system. Further, the reference numeral TMPU indicates a target processor, and this target processor TMPU executes a user program by acting as a microprocessor in a microprocessor application system (not shown) developed by a user.

In this embodiment, the emulation memory for storing user programs and data to be executed by the target processor TMPU is comprised of two memory banks EMEMO and EMEMO.
divided into MEMI and boss processor I-I M P
The host data bus HD B and the target data bus T are connected via multiplexer MPX3 so that they can be accessed from either side of U and the target processor TMPU.
Each is connected to the DB. Moreover, two memory banks E M E M O! ; and EMEMI, the memory bank EMEMO is allocated to the even address space and the memory bank EMEMI is allocated to the odd address space from the perspective of any processor.

Multiplexers MPX4 to MPX7 switch connections between the two memory banks EMEMO and EMEMI, the target address bus TAB, and the host data bus HDB.

These multiplexers MPX4 to MPX7 and the multiplexers MPXO to MPX3 are switched by the least significant bit TAO of the address signal output from the target processor TMPU. That is, when the lowest address bit TAO is 0" (even address), the target processor TMPU, the even memory bank EMEMO, and the host processor HM P
Connect U to the odd memory bank E M E M 1, and the lowest address bit TAO is 1 (odd address)
At the time, TMPU and EMEMI, HMPU and EMEMO
Connect each.

The latch circuit LATO-LAT3 is the host processor)
(This is a latch circuit arranged in the address space of MPU, and access to memory bank EMEM0.1 by target processor HMPU is performed via these 7 latch circuits in synchronization with the timing of target processor TMPU. , the above latch circuit LATO~LA
Of T3, LATO writes write data to memory bank EMEM0.1, and LATI writes data to memory bank EMEM0.1.
1, LAT2 holds the data transfer direction, and LAT3 holds the address to be accessed.

The timing controller C0NT receives bus use signals T, AS, and TM from the target processor TMPU.
Memory bank EMEM0.
1 chip select signal C○N"l", C0NTl and latch signal C0NT2 of latch circuit LAT2 are created.

The host decoder HDEC is the host processor HMP
A latch circuit LATO-LAT that decodes the address signal output from U and exists in the address space on the host side.
3 and the signals HS O-HS4 for selecting the timing controller C0NT are created.

On the other hand, the target decoder TDEC decodes the memory bank EM'E in the address space on the target side based on the address signal output from the target processor TMPU.
The range in which MO,l exists is decoded to create a signal TSO that controls the output timing of multiplexer MPX3.

In the emulator system configured as described above, the target processor TMPU is connected to the memory bank EMEM.
0.1, first output the address to be accessed onto the target address bus TAB and a signal specifying the access direction, read or write, onto the read/write bus TR/W. Asserts the signal TAS indicating that it is in use. If the least significant bit TAO of the address signal output at this time is II OII, the signals on buses TAB and TR/W are respectively sent to multiplexers MPX5. It is applied to the even-numbered memory bank EMEMO via MPX4. At this time, read/write signal T
If R/W is “O”, the write data output from the target processor TMPU onto the data bus TDB is sent to the memory bank EMEMO via the multiplexer MPXO.
is supplied and written to. On the other hand, read/write signal T
If R/W is 1", the read data read from the memory bank EMEMO is output onto the target data bus TDB via the multiplexer MPX3. Also, when the lowest bit TAO of the address signal is It I II, the read data read from the memory bank EMEMO is output to the target data bus TDB via the multiplexer MPX3. M P X 7, M P I3.MP
Odd number side memory bank E M E via XI and MPX3
M1 is similarly accessed.

Next, the host processor HMPU connects the memory bank EMEM.
The operation when accessing 0.1 will be explained.

First, the host processor HMPU monitors the control signal Q4 from the timing controller C0NT, and Q4
Wait until it becomes II. The control signal Q4 is a flag indicating the usage state of the memory bank to be accessed.When Q4 is ``II O'', it indicates that the memory can be accessed by the host processor I-(MPU), and when Q4 is LL I II When , it indicates that access is impossible. However, the initial state is Q4=10''.

When the control signal Q4 becomes O, the host processor I-I
MPU provides the address to the latch circuit LAT3 and the direction of access (read/write) to the latch circuit LAT2.
Set each. When the latch circuit LAT2 is designated to the write state, write data is set in the latch circuit LATO.

Thereafter, the host processor HMPU inputs "1" to the input terminal D4 of the timing controller C0NT to start the timing controller C0NT. Timing controller C0NT outputs control signal Q4 at startup.
1” as inaccessible to the host processor II M
Notify PU.

At the same time, when activated, the timing controller C0NT monitors the least significant bit LAO of the latch circuit LAT3, the least significant bit TΔO of the address of the target processor TMPU, and the bus use signal TAS, and (LAO@
Wait until TAO)-TAS=1. In other words, when the host processor HMPU wants to access an even address, it waits for the target processor TMPU to access an odd address, and when the host processor HMPU wants to access an odd address, it waits for the target processor TMPU to access an even address. wait. When this condition is met, the host processor HM P T
Memory banks EMEM0 and EMEM1 can now be accessed by J.

When the above conditions are met, the timing controller C0
NT outputs the control signal C0NT1 if the address least significant bit TAO is It OII, and if TAO is II I I
If T, assert control signal C0NTO.

Memory bank EMEMI or memory bank EMEMO
access. Also, when the latch circuit LAT2 is set to the read state, at the same time, the control signal C0
NT2 is asserted to latch the read data from memory bank EMEM0.1 into latch circuit LAT1.

When target processor TMPU has finished using the bus, bus use signal TAS is negated (level indicating non-use state).
When the controller C0NT outputs the control signal C0NTO
~ Negate C0NT2 and save memory bank EMEM0
．． 1's access is terminated. At the same time, control signal Q4
is set to '0' and notifies the host processor HMPU of the end of the access.

On the other hand, the host processor HMPU has a latch circuit LAT.
When lead is set to 2, timing controller C
After waiting for the output Q4 of 0NT to become II O11, the latch circuit LAT1 is read.

Data can be obtained from memory bank EMEM0.1.

In this way, in the above embodiment, when access requests to the emulation memory between the target processor and the host processor conflict, the target processor is always given priority, and after the target processor starts accessing one memory, the host processor starts accessing the other memory. The controller takes control to allow access to the memory.

As explained above, in the above embodiment, the memory of the system that is the target of emulation is substituted,
2. Memory where the program to be debugged is stored.
In addition to dividing the system into two banks, a multiplexer was added to each bank so that it could be accessed from either the host processor or the target processor, and this switching was performed by the lowest address signal output from the target processor. Therefore, when a user program is being executed by the target processor, in bus cycles in which the target processor is accessing memory banks with even addresses, the host processor is accessing memory banks with odd addresses, and the target processor is accessing memory banks with odd addresses. In the bus cycle during which the host processor is accessed, each of the memory banks at even addresses can be accessed. Therefore, the emulation memory can be accessed by the host processor without stopping the execution of the user program by the target processor.

This makes it possible to display or change the contents of the emulation memory during execution of the user program without stopping execution of the user program. As a result, the efficiency of system debugging and system evaluation using the emulator is significantly improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, in the above embodiment, the host processor HMPU emulates the emulation memory E.
The address for accessing MEMO and EMEMI is provided by the latch circuit LAT3 via the host data bus HDB.
Although the configuration is such that the data is latched once and then supplied to the memory, it is also possible to supply it to each memory via the host address bus HAB. Further, in the above embodiment, the emulation memory is divided into two memory banks, but it may be divided into three or more banks.

In the above explanation, the present invention is applied to an emulator, but the present invention is not limited thereto, and can be widely applied to a system including a memory that can be accessed by a plurality of data processing devices. For example, if the present invention is applied to a video RAM system accessed by a microprocessor and a CRT controller, a display system that is free from flickering due to access contention can be created. INDUSTRIAL APPLICABILITY The present invention is applicable to a system where one memory is shared by at least two data processing devices, and it is desired to allow the shared memory to be accessed by one data processing device without affecting the operation of the other data processing device. can.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, in an emulation system.

The proxy memory (emulation memory) can be accessed by the host processor without stopping the operation of the target processor, and thus the contents of the emulation memory can be displayed and changed without stopping the execution of the user program. This makes it possible to prevent the microcomputer application system to be debugged from going out of control due to operations that display or change the contents of the emulation memory, and falling into a state in which it is difficult to recover.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of an emulator according to the present invention, FIG. 2 is a block diagram showing the overall configuration of a system development device, and FIG. 3 is a block diagram showing an example of the configuration of a conventional in-circuit emulator. It is. HMPU...Host processor, TMPU...
Target processor, EMEMO...even memory bank O, EMEMI...odd memory bank 1, C
0NT...Timing controller, MPXO-M
PX7...Multiplexer, HDEC...Host decoder, TDEC...Target decoder, L
ATO-LAT3...Data latch circuit. Figure 1

Claims (1)

[Scope of Claim] A data processing system comprising one or two data processing devices and a memory that can also be accessed from those data processing devices, wherein the memory is constituted by a plurality of memory banks, and Prioritizing access to the memory by one data processing device, the first
1. A data processing system comprising: control means for controlling a second data processing device to access another memory bank while a second data processing device is accessing one memory bank. 2. The data processing system according to claim 1, wherein the first data processing device is an emulation microcomputer that performs functions of a microcomputer of a system to be debugged. 3. The memory is divided into memory banks accessible by even addresses and memory banks accessible by odd addresses, and the connection to the data processing device is switched by the address signal output from the first data processing device. 3. The data processing system according to claim 1, wherein the processing is performed based on the least significant bit.