JP2572736B2 - Data bus conflict avoidance circuit for in-circuit emulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a microprocessor for a tester (hereinafter referred to as CP
U. In the in-circuit emulator (hereinafter referred to as ICE) that emulates the behavior of the tester and debugs the program of the tester, the data bus between the tester and the ICE generated when the data bus buffer between the tester and the CPU is deleted. This is a circuit for avoiding contention.

(B) Conventional Techniques and Problems Next, a block diagram of a conventional ICE will be described with reference to FIG.

4 is a memory for ICE control, 3 is a memory for mapping an emulation memory, 4 is an emulation memory (hereinafter simply referred to as a memory), 5 is a buffer, and 10 is a CPU.

The CPU 10 is of the same type as the target CPU of the tester. When the CPU 10 accesses an external memory, if it is a memory read, it issues an address signal to the address bus 11 and simultaneously sets the read / write signal 17 to the H level. I do. Then, the strobe signal 13 is set to L level, and the address bus 11
To the outside that is valid.

Since the external memory responds by returning data to the data bus 12, the CPU 10 takes in the data from the data bus 12, returns the strobe signal 13 to the H level, and completes the read cycle.

Similarly, during a memory write, the CPU 10 outputs address information to the address bus 11, outputs data information to the data bus 12, outputs an L level to the read / write signal 17, and then sets the strobe signal 13 to the L level. Inform the outside that a memory write cycle has occurred.

The external memory responds by writing the data to the specified address of the memory, and the CPU 10 returns the strobe signal 13 to the H level to complete the write cycle.

Memory 2 is accessed from CPU 10 but CPU 10
Mode, that is, without executing the tester program,
This is accessed when the ICE is in the control state.

In other words, the memory 2 stores programs and data necessary for the CPU 10 to control the inside of the ICE.

The memory 3 and the memory 4 are also accessed from the CPU 10,
The memories 3 and 4 are used in place of the memory of the tester because the CPU 10 is in the RUN mode, that is, the state in which the program of the tester is executed, and sometimes the memory of the specific address is not mounted in the tester. is there.

 Next, a configuration diagram of the memory 3 is shown in FIG.

In FIG. 5, the address bus 11 and the mode switching signal 16 from the CPU 10 are applied to the input of the memory 3 as address signals. A map signal 14, an access signal 15, and an enable signal 18 are taken out as outputs by a combination of input signals to the memory 3.

The map signal 14 and the enable signal 18 are further stored in the memory 4
And has a function of arranging the memory 4 having a limited capacity at an arbitrary address in the large address space of the CPU 10.

The access signal 15 has a function of notifying the buffer 5 of whether to access the memory of the tester based on the map information of the memory 4 and the mode switching signal between the RUN mode and the ICE mode.

If the access signal 15 is at the L level, the buffer 5 is enabled to access the tester, and data flows in the direction determined by the read / write signal 17.

On the other hand, if the access signal 15 is at the H level, it indicates an ICE mode or emulation memory access, and data is not exchanged with the tester, so that the buffer 5 is disabled.

Further, in the RUN mode, the mode switching signal 16 opens the gate 6, and the strobe signal 13 is supplied to the tester as a data strobe signal (hereinafter, referred to as a DS signal).

By the way, since the ICE removes the CPU of the tester and operates instead, the timing of the probe portion of the ICE is preferably as close to the CPU 10 as possible.

However, in the case of the conventional ICE, the timing of the data bus is delayed by about 10 nsec due to the buffer 5 inserted between the CPU 10 and the tester.

For this reason, the tester may operate only with the CPU, but when the ICE is connected, the data bus setup time may be increased by about 10 ns, and the tester may not operate.

Sometimes, when the bus cycle of the CPU 10 is only about 60 to 100 nsec in total, even 10 nsec is a large loss.

Therefore, it is desirable to delete the buffer 5 if possible.

While the CPU 10 is accessing the memory 2 in the ICE mode, the DS signal is not supplied to the tester because the gate 6 is closed. Therefore, even if the buffer 5 is not provided, only the output data from the memory 2 is loaded on the data bus 12, so that the buffer 5 may be deleted.

Also, even when the CPU 10 is accessing the memory of the tester, there is no problem even if the bus buffer 5 is not provided because only the data from the tester is stored in the data bus 12.

However, when the CPU 10 is reading data from the memory 4, the DS signal is supplied to the tester, so that the data is output from the tester, and the data is also output from the memory 4. Otherwise, both data will collide on the data bus 12 and will compete.

FIG. 6 shows the operation when the CPU 10 accesses the memory 4, and shows that the buffer 5 cuts data coming from the target and prevents data competition on the data bus 12.

As described above, in order to prevent the data bus 12 from competing when accessing the memory 4, the buffer 5 cannot be deleted conventionally, and it is difficult to realize a high-speed CPUT ICE. Was.

(C) Object of the Invention The present invention prevents the contention of the data bus by shifting the respective access cycles of the tester and the memory 4 by using the retry signal of some CPUs. The purpose is to enable the buffer 5 shown in the figure to be deleted.

(D) Embodiment of the Invention Next, FIG. 1 shows a configuration diagram of an embodiment according to the present invention.

FIG. 1 is a diagram corresponding to FIG. 6, and is a block diagram when the memory 4 is accessed.

Therefore, in realizing the actual ICE, the fourth
It is necessary to add the memory 2 and the like shown in FIG. 1 to FIG. 1. However, the memory 2 and the like are not shown in FIG.

The CPU 1 in FIG. 1 is almost the same as the CPU 10 in FIG. 4, but is different from the CPU 10 in FIG. 4 in having a retry signal input terminal.

The retry terminal is a function of the CPU such as GMICRO / 200.When the CPU1 completes the current memory access cycle by inputting a retry signal from the outside while the memory access cycle is being executed, the CPU1 Run the cycle.

If the retried bus cycle is a read cycle, the data read first becomes invalid, and the read data in the retry cycle becomes valid.

The memory 4 and gate 6 in FIG. 1 are the same as those in FIG.

The map control unit 7 corresponds to the memory 3 shown in FIG. 6, but the operation thereof is different. FIG. 2 shows a configuration diagram of an embodiment of the map control unit 7.

The map control unit 7 in FIG.
11 and a retry signal 19 which is the output of the map control unit 7 itself.
The retry cycle signal 20 sampled at the rising edge of the strobe signal 13 of the CPU 1 is input as an address, and the map signal 14 to the memory 4, the enable signal 18, the retry signal 19 to the CPU 1 and the mask signal 31 are output as data.

Next, the operation of reading data from the memory 4 of FIG. 1 will be described with reference to the time chart of FIG.

When the CPU 1 starts a memory read cycle, address information is output to the address bus 11, and subsequently, a strobe signal 13 is output.

At this time, since it is not yet known whether the address accessed by the CPU 1 is the tester side or the memory 4 side, the strobe signal 13 is output to the tester as it is as a DS signal.

Next, the map control unit 7 determines the address information, and when it is determined that the access is on the memory 4 side, a retry signal 19 is issued to the CPU 1.

Then, the CPU 1 invalidates the data read after completion of the current bus cycle and generates the same bus cycle again.

This time, since the retry cycle signal 20 obtained by sampling the retry signal 19 is at the L level inside the map control unit 7, the enable signal 18 = L, the retry signal 19 = H, and the mask signal 31 according to the preset data. = H, the memory 4 is enabled,
The data in the memory 4 is output to the data bus 12.

At the same time, the strobe signal 13 is masked by the mask signal 31, no DS signal is output to the tester, and no data is output from the tester.

In this way, the tester and the memory 4 are accessed in a time-division manner, and the memory 4 can be accessed without a data conflict even without the buffer 5 shown in FIG.

(E) Effect of the Invention According to the present invention, the buffer can be deleted without competing for the data bus.
The delay time of 10 ns can be eliminated, and the following effects can be obtained.

(A) The ICE can be operated at the same timing as when the CPU is used alone, and it is possible to prevent an accident that the ICE operates only with the CPU alone but does not operate when the ICE is connected.

(A) An ICE that can follow the high-speed operation of the CPU can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment according to the present invention, FIG. 2 is a block diagram of an embodiment of a map control unit 7, FIG. 3 is a time chart for reading data from the memory 4 in FIG. Is a block diagram of a conventional ICE, FIG. 5 is a configuration diagram of a memory 3,
FIG. 6 is an explanatory diagram of the operation when the CPU 10 accesses the memory 4. 1 ... CPU, 2 ... ICE control memory, 3 ... memory,
4 ... Emulation memory, 5 ... Buffer, 6 ...
... gate 7, map control unit 11, address bus,
12 data bus, 13 strobe signal, 14 map signal, 15 access signal, 16 mode switching signal, 17
…… Read / write signal, 18 …… Enable signal, 19 ……
Retry signal, 20 ... Retry cycle signal, 21 ... F
F, 31 ... Mask signal.

Claims (1)

(57) [Claims] An address bus (1) and a strobe signal (1)
3) as input, map signal (14), enable signal (1
8), a map controller (7) for outputting a retry signal (19) and a mask signal (31), an address bus (11), a map signal (14), and an enable signal (18). A memory (4) connected to the bus (12); an address terminal connected to the address bus (11); a data terminal connected to the data bus (12); and a strobe signal (13) which becomes active when a bus cycle occurs. And output
CPU (1) to input retry signal (19), strobe signal (13) and mask signal (31) as inputs,
When there is no mask signal (31), the strobe signal (13)
A gate for outputting a data strobe signal as a data strobe signal.