JPH02307126A - In-circuit emulator - Google Patents

Abstract

PURPOSE:To shorten the overall access time of an emulation memory by using plural emulation RAMs in place of a target memory. CONSTITUTION:Plural emulation RAM 3 - 5 are used in place of a target memory. Then an address outputted from a target microprocessor 1 is partly decoded for acquisition of a chip selection signal used for selection of the RAM 3 - 5. The addresses of the RAM 3 - 5 are limited to some of those addresses outputted from an address mapping RAM 2 and the processor 1. Thus it is possible to neglect the transmission delay of an address decoder 6 despite the incorporation of an emulation memory having large capacity and to attain the emulation of an access time at a degree approximately equal to that secured with small capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an improvement in the emulation function of an in-circuit emulator for a microprocessor.

<Prior Art> Conventionally, there have been in-circuit emulators for microprocessors (μP) used when developing and debugging programs for applied equipment. This in-circuit emulator is equipped with an emulation memory that acts as the memory of a device to be debugged (referred to as a target).

Emulation memory has the function of acting as a substitute for target memory when debugging a single piece of software when the target hardware is not yet completed. Random rewritable to allow 10g corrections (batches)
It also has the function of acting as an emulation memory made up of access memory (RAM).

A typical configuration of such emulation memory is shown in FIG. 5. Generally, emulation memory cannot have a capacity large enough to cover the entire memory address space of the target microprocessor. Address mapping RAM is used which allows a limited capacity of emulation memory to be placed at any address of the target microprocessor. A part of the target address bus signal (usually the upper bits) is input to the address mapping RAM, and a preset conversion address is output to the emulation RAM. Address mapping RAM propagation delay tdl
, if the access time of the emulation RAM is td3, the total access time of the emulation memory with the configuration shown in FIG. 5 is tdl+td3.

On the other hand, in recent target systems using 16-bit or 32-bit microprocessors, the memory capacity and speed have rapidly increased, and emulation memory has also been required to have a larger capacity and faster speed.

To increase the emulation memory capacity 1, the number of output bits of the mapping memory is usually added as shown in Figure 6, and the added bits (EA2) are transferred to the address decoder 6.
and multiple emulation memories (EA
I, EA2. , , , BAn) so that one of 3 to 5 is selected.

<Problems to be Solved by the Invention> However, in the conventional configuration as shown in FIG. 6, the access time of the entire emulation memory is tdl+td2+td3 as shown in FIG. 7, where td2 is the propagation delay of the address decoder 6. There was a problem that the access time was longer than that of the emulation memory having the configuration shown in FIG. 5, and that it could not keep up with the increase in speed of the target microprocessor.

The purpose of the present invention has been made in view of the above points, and the purpose of the present invention is to make the transmission delay of the address decoder negligible even though a large capacity emulation memory is implemented, and to reduce it to the same level as when the memory capacity is small. An object of the present invention is to provide an in-circuit emulator capable of emulating the access time of .

Means for Solving the Problems> In order to achieve such objects, the present invention provides an in-circuit emulator for a microprocessor that has an emulation memory that acts as a target memory, in which a translation address is set in advance and the microprocessor An address mapping RAM that receives a part of the processor's address bus as input and outputs a preset converted address; an address decoder that decodes the other part of the target microprocessor's address bus; and one of the address decoders. The two outputs are connected to a chip select, and the converted address output from the address mapping RAM and the address bus of the target microprocessor that is not input to the address mapping RAM and the address decoder are connected to the data input section. It is characterized by having a plurality of emulation RAMs that are connected to each other and act as target memories.

Effects> In the present invention, a part of the address output by the target microprocessor is directly decoded and used as a chip select signal for emulation RAM selection.

Further, as the address of the emulation RAM, the output of the address mapping RAM and a part of the address output from the target microprocessor are used as in the conventional case.

By doing this, the access time of the entire emulation memory is the smaller of the sum of the address mapping RAM propagation delay tdl and the emulation RAM access time td3, or the sum of td3 and address decoder propagation delay td2. Become.

However, since tdl>td2 normally, the access time of the entire emulation memory is tdl+
It becomes td3. That is, the transmission delay of the address decoder can be ignored, and it is possible to emulate access times comparable to those of a small capacity.

<Example> The present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an in-circuit emulator according to the present invention. In the figure, reference numeral 1 denotes a target microprocessor, and an address bus A-BUSI connected to the address output terminal ADH has a part of its upper bits connected to the address mapping RAM 2 through a 3-state buffer 8. The other part is connected to the address decoder 6 through a 3-state buffer 9. Also, the lower bit part of the address bus is 3
It is connected through the state buffer 10 to the lower bit portions of the addresses of all emulation RAMs (3 to 5).

Target microprocessor 1 data bus D-R
US1 is commonly connected to data input/output terminals of emulation RAMs 3 to 5 through a bidirectional buffer 15.

7 is a control CP that controls the emulator
At U, its address bus A-BUS2 is connected to the address mapping RAM 2 through a 3-state buffer 11, to the address decoder 6 through a 3-state buffer 12, and to the address decoder 6 through a 3-state buffer 13.14.
It is connected to the emulator RAMs 3 to 5 through the emulator RAMs 3 to 5.

In addition, the data bus D-BUS2 of the control CPU7
is the emulation RA through the bidirectional buffer 16.
It is commonly connected to the data input/output terminals of M3 to M5, and is connected to the data output of the mapping RAM 2 through the bidirectional buffer 17.

The converted address output by the address mapping RAM 2 is connected to the upper bit portions of the addresses of the emulation RAMs 3 to 5. The output of the address decoder 6 is connected to the chip selects of the emulation RAMs 3-5.

The three-state buffers 8 to 10 and the bidirectional buffer 15 are turned on while the target microprocessor is executing, and turned off when the target microprocessor breaks.

Three-state buffers 11-14 and bidirectional buffers 16.17 are turned off during execution of the target microprocessor and control CPU 7 uses mapping RAM.
2 or turns on when accessing the emulation RAM.

The operation in such a configuration will be explained next.

In addition, in order to make the operating state easier to understand, mapping R is shown in FIG.
An example will be explained in which the input of AM2 and the input of address decoder 6 are both 1 bit, two emulation RAMs are prepared, and each input is 2 bits. It is also assumed that the mapping RAMs 3 and 4 have previously stored data as shown by the control CPU 7, respectively. Target microprocessor 1 starts execution and reads data sequentially starting from address 0 (
READ)! , the correspondence between the addresses Ao to A3 of the target microprocessor and the inputs of the emulation RAM is shown in Table 1.

Table 1 Therefore, the data in the emulation RAMs 3 and 4 is read out 11n times as shown in FIG. 3, and continuous data can be read, allowing normal emulation of the target microprocessor.

The transmission delay of address mapping RAM2 at this time is t
dl, the propagation delay of the address decoder 6 is td2, the access time of the emulation RAMs 3 to 4 is td3, the 3-state buffers 8 to 9 and the bidirectional buffer 15
The access time of the entire emulation memory when ignoring the propagation delay is tdl+td3 or td2+
The time is the larger of td3.

However, since the memory access time is usually larger than the decoder propagation delay, tdl>td2, the resulting access time is tdl to td3, as shown in FIG. Therefore, the propagation delay td2 of the address decoder does not affect the access time.

<Effects of the Invention> As explained in detail above, according to the present invention, even though a large capacity emulation memory is implemented, the propagation delay of the address decoder can be ignored, and the An in-circuit emulator capable of emulation with comparable access time can be realized.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts showing an embodiment of an in-circuit emulator according to the present invention, FIG. 2 is a block diagram of a specific example used to explain the operation, and FIG. 3 is an example of data read from the emulation RAM. 4 is a time chart showing the propagation delay, FIG. 5 is a diagram for explaining the configuration of a conventional emulation memory, and FIG. 6 is a diagram showing the configuration of a conventional emulation memory. Configuration diagram of emulation memory,
FIG. 7 is a time chart showing the propagation delay in the configuration of FIG. 6. DESCRIPTION OF SYMBOLS 1... Target microprocessor, 2... Address mapping RAM, 3, 4.5... Emulation RAM, 6... Address decoder, 7... Control CPU, 8, 9, 10, 11 .1,2゜13
．． 14...3 state buffer, 15.16°17.
...Bidirectional buffer. Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6 Fig. Bottom 7

Claims (1)

[Claims] In an in-circuit emulator for a microprocessor having an emulation memory acting as a target memory, a translation address is set in advance, a part of the address bus of the microprocessor is input, and the preset translation address is set as an input. an address decoder for decoding another part of the address bus of the target microprocessor; one output of the address decoder is connected to a chip select; the address mapping RAM outputs a translated address; and an address bus that is not input to the address mapping RAM and address decoder among the address buses of the target microprocessor are respectively connected to the data input section, and a plurality of emulation RAMs acting as target memories are provided. An in-circuit emulator that features short overall memory access time.