JPH06275065A - Memory access method and its controller - Google Patents

Abstract

PURPOSE:To attain performing write operation immediately after read operation in the state when no precharge time of RAS exists in a memory where the input pin and the output pin of data are connected. CONSTITUTION:In an address multiplex type memory without the eable control of a data output, whose input pin and output pin of the data are connected and capable of accessing in a first page mode, a row address strobe (RAS) is made low as it is continuously even after a column address strobe (CAS) is returned to high for ending a read cycle. Then, a write enable anti WE is made low to be held immediately after a data output pin becomes high impedance, and data write operation is performed at the fall edge of the CAS.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access method capable of performing an early write operation even when a row address strobe precharge time is not sufficient immediately after a read operation.

[0002]

2. Description of the Related Art Hereinafter, the row address strobe is abbreviated as RAS and the column address strobe is abbreviated as CAS.

When a data input pin and a data output pin of a conventional DRAM are connected to form an input / output data bus and a write operation is performed after a read operation, the RAS precharge time is sufficient after the read operation is completed. It was secured, and then the early rewrite operation was executed.

[0004]

However, in the above structure, when the read modify write operation is performed, the data input pin and the data output pin of the DRAM are connected and connected to the input / output data bus. As shown in the area R of the above, collision of input data and output data occurs on the input / output data bus.

On the other hand, if the RAS precharge time is sufficient, RAS is set high to complete the read operation as in step A of FIG. 4 and after RAS is precharged as in step B. Then, if RAS is made low again as in step C, the early write operation can be performed, but if the precharge time of RAS is insufficient, writing immediately after read was impossible.

In view of the above point, the present invention provides a memory access that is equivalent to a read-modify-write in a state where the data input and the data output of the memory are connected and the RAS precharge time is insufficient. The purpose is to provide a method.

[0007]

According to the present invention, there is provided an address multiplex type memory which has no data output enable control, has data input pins and data output pins connected to each other, and is accessible in a first page mode. An access method, which keeps the row address strobe low after returning the column address strobe high to end the read cycle and holding the write enable low after the data output pin goes high impedance. However, the memory access method is characterized in that the data write operation is performed at the falling edge of the column address strobe.

[0008]

According to the present invention, by the above method, the RAS precharge time is not sufficient immediately after the read operation,
Since the early write operation can be continuously performed, the memory access equivalent to the read modify write can be performed by using the DRAM in which the data input pin including the SIMM and the data output pin are connected.

[0009]

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention. In FIG. 1, a system 11 is a memory board having a memory access by the method according to the present invention and having a memory reflection function, and a system 12 and a system 13 are CPU boards having a cache snoop function. The system 11, system 12 and system 13 are connected via a bus 14.

In the above structure, when the CPU board of the system 12 first causes a cache miss, the address addr0 is sent from the memory board of the system 11 onto the bus 14.
, A memory board of the system 11 starts a data read operation of the row address raddr0 and the column address caddr0 from the DRAM 16.

Latest data D-va at address addr0
The cache 13A of the system 13 holding the lid
Issues a signal xown indicating ownership of data to the bus 14.

The memory board of the system 11 is xown.
When the signal is asserted, the data read operation currently being executed from the DRAM 16 is abandoned and the latest data D
-Start the operation of writing valid into the address addr0 of the memory board.

First, since the CPU of the system 12 reads data from the memory board of the system 11,
At time t0, RAS is dropped and row address raddr is set.
To the DRAM.

Next, at time t1, CAS is lowered and the column address caddr is fetched into the DRAM 16, and at time t1 + dt, the data D-invalid from the DRAM 16 is fetched.
Output d.

At this time, the CPU of the system 13 has a signal xow indicating that it has the latest data in the cache.
Assert n, which causes the memory board to raise CAS at time t2 to abandon the data read operation. As a result, the data output D-i from the DRAM 16
nvalid disappears at time t2 + dt and enters a high impedance state.

Next, RAS is held low and the value of the column address caddr is also held. At time t3, the write signal WE is set low to start the early write operation. Valid data D-valid is confirmed at time t4, and CAS is stopped at time t5 to DR this data.
Write to AM16.

In this embodiment, a DRAM is used as the memory.
It has been described that the row address and the column address are determined when RAS and CAS are low and the writing is permitted when the write enable is low, but this does not limit the present invention. Needless to say.

[0018]

As described above, according to the memory access method of the present invention, it is possible to perform access similar to read-modify-write with the data input pin and the data output pin of the memory being connected to each other. High-speed memory access is possible without separating the upper data bus on the input side and the output side.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of the present invention.

FIG. 2 is a timing diagram showing a transition of operations in the embodiment.

FIG. 3 is a timing chart showing a state of data collision that occurs when a read-modify-write operation is performed with the data input and data output of the DRAM connected.

FIG. 4 is a timing diagram showing an early write operation after a read operation in a conventional example.

[Explanation of symbols]

11 memory system 12 CPU system 13 CPU system 13A cache 14 bus system 15 DRAM access control unit 16 DRAM chip D-valid valid latest data xown bus signal indicating that the latest data is owned in the cache raddr valid row address caddr Timing column where valid column address R data collides

Claims (2)

[Claims] 1. A method of accessing an address multiplex type memory, which has no data output enable control, has data input pins and data output pins connected to each other, and can be accessed in a first page mode, comprising a read cycle. After the column address strobe is returned to the indeterminate state to terminate the write, the row address strobe is still held in the fixed state, and the write enable is held write-enabled and held after the data output pin becomes high impedance. A memory access method characterized in that a data write operation is performed at an edge of a transition in which an address strobe transits to a definite state. 2. An access control device for an address multiplex type memory, which has no data output enable control, has data input pins and data output pins connected to each other, and can be accessed in a first page mode. After returning the column address strobe to the indeterminate state to end the cycle, the row address strobe is still held in the committed state, and the write enable is held as write enable after the data output pin becomes high impedance. A memory access control device comprising memory access control means for performing a data write operation at an edge of a change in which a column address strobe makes a transition to a definite state.