KR100333648B1 - Write scheme of DDR SDRAM synchronized with the falling edge of Data Strobe Signal - Google Patents

Abstract

In the DDR SDRAM, in particular, to provide a stable operation during the write operation, the present invention is to provide a data signal input from the outside of the chip to the rising edge of the rising data signal and the data strobe signal synchronized with the rising edge of the data strobe signal. A data input unit for generating synchronized polling data signals and then aligning the rising data signal and the polling data signal at the polling edge of the data strobe signal to a global data line, and receiving a command from an external chip. A cas signal generator for generating a write cas signal in synchronization with a polling edge of the data strobe signal during a write operation; and a global data line for the rising data signal and the falling data signal from the data input part in response to the write cas signal. Number of global data lines to be sent It includes a.

Description

Write scheme of DDR SDRAM synchronized with the falling edge of Data Strobe Signal}

The present invention relates to DDR SDRAM (Double Data Rate Synchronous DRAM), in particular to the falling edge of the data strobe signal (DQS) input to the data strobe pin (data strobe pin) during write operation in the DDR SDRAM The present invention relates to a DDR SDRAM for performing a write operation synchronously to speed up a write operation in a DRAM.

As is well known, unlike SDRAM, which is synchronized to the rising edge of the clock and writes and reads one data per clock, DDR SDRAM is synchronized to the clock's rising and polling edges so that it is two per clock. A DRAM that doubles the bandwidth by writing and reading data.

1 is a diagram illustrating the configuration of an external signal input terminal of a general DDR SDRAM. First, a data input unit for generating internal data includes data DQ, a clock CLK, a command COM, and a data input from an external chip. The generation and flow of the signals related to the write operation from the data strobe signal DQS are well illustrated.

Referring to FIG. 1, after the buffered write data DQ is externally input, the rising data (rising_data) and the falling data latched in synchronization with the rising edge detection pulse signal dsrp and the falling edge detection pulse signal dsfp, respectively. A buffer / latch unit 14 that generates (falling_data) and alignment data (align_data) synchronized with the falling edge detection pulse signal (dsfp) and aligning the rising data (rising_data) with the falling data (falling_data). ) Is then synchronized with the internal clock pulse signal iclk, and the alignment unit 17 for aligning the alignment data (align_data) and the falling data (falling_data) with the internal clock pulse signal iclk. Is made of.

The DDR SDRAM includes an internal clock signal generator 24 which generates an internal clock pulse signal iclk in synchronization with the rising edge of the external clock signal CLK after receiving and buffering an external clock signal CLK; After buffering an external command signal COM, the commander input unit 27 for latching in synchronization with the internal clock pulse signal iclk, and the rising edge sensing pulse signal after buffering the data strobe signal DQS from the outside (dsrp) and a data strobe input unit (31) for generating a falling edge detection pulse signal (dsfp), and a casing for generating a signal for executing an incoming command from the outside and an internal signal for performing a read and write command. A generation unit 21 and a global data line 32 for receiving the internal data in response to the data transfer signal data_strobe are provided.

FIG. 2A is a diagram illustrating a general write timing diagram, and FIG. 2B is a diagram illustrating a timing diagram of cell data when a precharge signal PCG is input as part 'A' of FIG. 2A.

A general write operation in a DDR SDRAM will be described with reference to FIGS. 1, 2A, and 2B.

The buffer / latch unit 14 buffers the externally input write data DQ to the CMOS level by the data buffer unit 10A, and the rising data latch unit 12 rises the data strobe signal DQS. The latched rising data (rising_data) is generated in synchronization with the rising edge sensing pulse signal dsrp generated at the edge, and the falling data latch unit 13 detects the falling edge generated at the falling edge of the data strobe signal DQS. The latched falling data (falling_data) is generated in synchronization with the pulse signal dsfp.

The first data alignment unit 15 receives the latched rising data (rising_data) and generates alignment data (align_data) synchronized with the falling edge detection pulse signal dsfp, and the second data alignment unit 16 generates the alignment data. Two internal data (internal_data) which are aligned by mutually aligning the alignment data (align_data) and the falling data (falling_data) in synchronization with the internal clock pulse signal (iclk) synchronized with the rising edge of the external clock (CLK). ) Is transmitted until just before the global data line 32.

As described above, in the write operation of the DDR SDRAM, since the write data DQ is input in synchronization with the rising edge and the falling edge of the data strobe signal DQS, the write data DQ has a latency of one clock, and the clock rises internally. Since data is transferred in synchronization with the edge, the internal write latency is two clocks.

On the other hand, the cas active command signal input from the pad is buffered at the CMOS level by the command buffer unit 25, and then latched in synchronization with the internal clock pulse signal iclk by the command latch unit 26. The signal is sent to the instruction decoder unit 19 as a signal. The command decoder 19 detects an internal precharge signal pcg generated when an external precharge command is received and the CAS active command signal from the inside to the rising edge of the external clock CLK. Generate a synchronized internal cas signal excasp. In addition, the cas signal generator 21 generates an internal signal for performing a read / write command so that the cas signal generator 21 is commonly used for read and write operations according to a burst length at the rising edge of the external clock CLK. An increased cas signal (icasp) is generated at the to control the write operation.

If the CAS active command is a write command, as described above, since the write latency is 2 clocks in the interior, the CAS signal generation unit 21 writes 2 clocks after the occurrence of the internal casing signal (excasp). The write signal is controlled by generating a cas signal casp_wt and the cas signal icasp. The write cas signal casp_wt and the cas signal icasp then receive a data transfer signal data_strobe, which is an input data strobe signal. The internal data (data) generated and coming up to immediately before the global data line 32 is transmitted to the global data line 32. In addition, the write cas signal casp_wt and the cas signal icasp generate a signal YI corresponding to an input address and an internally increased column address so that data is written to the corresponding cell.

As can be seen from the above description, when the write operation is performed internally, the write operation is synchronized with the rising edge of the external clock CLK so as to match the timing of the write data inputted with the data strobe signal DQS. The write data DQ should be aligned with the falling edge of the data strobe signal DQS and then again aligned with the rising edge of the clock CLK to transmit data.

In addition, the internal write operation controlled by the address transfer method and the data transfer method as described above may interrupt the write data DQ with a precharge command or a precharge command that can be entered as soon as possible without data loss. When the last write data (DQ) to be written is high data is written to the cell as low as ΔV and low data is written to the cell as ΔV, as shown in Figure 2b has a fatal effect on subsequent operation of the chip.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and executes an internal write operation in synchronization with the polling edge of the data strobe signal DQS, so that the polling edge of the data strobe signal DQS can be solved. Since the write operation can be executed as fast as the time difference between the rising edge of the external clock, the purpose of the present invention is to provide a dial SDRAM for securing a certain amount of time for the last data written to the cell.

1 is a diagram showing the configuration of an external signal input terminal of a general DDR SDRAM;

2A is a diagram showing a general write timing diagram;

2B is a timing diagram of cell data when a precharge signal is input;

3 is a diagram showing the configuration of an external signal input terminal of a DDR SDRAM according to an embodiment of the present invention;

4A is a diagram showing a write timing diagram according to the invention;

4B is a view showing a timing diagram of cell data when a precharge signal is input according to the present invention;

5 is an exemplary view showing an internal circuit diagram of a write casing signal generation unit according to the present invention;

6 is a timing diagram of a write casing generator according to the present invention;

* Description of the main parts of the drawing

160: data input unit

200: cas signal generator

230: internal clock generator

260 command input unit

300: data strobe input unit

310: Global Data Line

1000: input unit

2000: latch 1

3000: first transfer gate part

4000: second latch portion

5000: second transfer gate portion

6000: output unit

According to the present invention for achieving the above object, in the DDR SDRAM, a data signal input from the outside of the chip is generated as a rising data signal synchronized with the rising edge of the data strobe signal and a falling data signal synchronized with the falling edge of the data strobe signal. Data input means for aligning the rising data signal and the falling data signal at a falling edge of the data strobe signal to a global data line; A cas signal generation means for receiving a command from outside the chip and generating a write cas signal in synchronization with a polling edge of the data strobe signal during an internal write operation; And global data line means for transmitting the rising data signal and the falling data signal from the data input means to a global data line in response to the write casing signal.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

FIG. 3 is a diagram illustrating the configuration of an external signal input terminal of a DDR SDRAM according to an embodiment of the present invention, wherein data (DQ), clock (CLK), command (COM), and data strobe signal (DQS) are respectively input from an external chip. Shows the generation and flow of signals related to write operation.

Referring to FIG. 3, a rising data signal (rising_data) synchronized with the rising edge of the data strobe signal (DQS) and a falling data signal (falling_data) synchronized with the falling edge of the data strobe signal (DQS) are respectively generated from outside the chip. And a data input unit 160 for aligning the rising data signal rising_data and the falling data signal falling_data at the falling edge of the data strobe signal DQS to the global data line 310, and a chip. A cas signal generation unit 200 which receives a command COM from the outside and generates a write cas signal cas_pulse synchronized with a polling edge of the data strobe signal DQS in an internal write operation, and the write cas signal cas_pulse. In response to the global data line, the rising data signal rising_data and the falling data signal falling_data from the data input unit 160 are transmitted to the global data line. It is provided with an italy line portion 310.

A detailed configuration will be described with reference to FIG. 3.

The data input unit 160 may buffer the data buffer unit 110 for buffering the data signal DQ input from the outside of the chip, and the data signal from the data buffer unit 110 may rise in the data strobe signal DQS. Rising data latch unit 120 for generating a latched rising data signal (rising_data) in synchronization with the edge detection signal (dsrp) and the data signal from the data buffering unit 110 to the data strobe signal (DQS) Falling data latch 130 for generating a falling data signal (falling_data) latched in synchronization with the falling edge detection signal (dsfp) and the rising data signal (rising_data) falling edge detection of the data strobe signal (DQS) And an alignment unit 150 for aligning in synchronization with the signal dsfp.

In addition, the casing generator 200 may be configured to generate a read cas signal signal casp_rd synchronized with a rising edge of a clock during a read operation and a polling edge of the data strobe signal DQS during a write operation. And a write cas signal generator 190 for generating a write cas signal (casp_pulse) in synchronization with the.

The clock signal buffer unit 210 which receives and buffers the external clock signal CLK and the internal clock pulse which synchronizes the clock signal from the clock signal buffer unit 210 with the rising edge of the external clock signal CLK. The internal clock signal generator 230 generating the signal iclk, the command buffer 240 buffering the external command signal COM, and the command signal from the command buffer unit 240 receive the internal clock pulse signal ( an instruction input unit 260 having an instruction latch unit 250 latching in synchronization with iclk, a data strobe buffer unit 270 that receives and buffers the data strobe signal DQS from the outside of the chip, and the rising edge detection signal The data strobe signal input unit 300 includes a rising edge detection signal generation unit 280 for generating a dsrp and a falling edge detection signal generation unit 290 for generating the falling edge detection signal dsfp.

4A is a diagram showing a write timing diagram according to the present invention, and FIG. 4B is a diagram showing a timing diagram of cell data at the time of inputting a precharge signal according to the present invention.

The write data DQ input from an input data pad is buffered by the data buffer unit 110 and then synchronized with the rising edge detection signal dsrp of the data strobe signal DQS by the rising data latch unit 120. The latch is generated as the rising data (rising_data), and the latching data latch 130 generates the falling data (falling_data) by being latched in synchronization with the falling edge detection signal dsfp of the data strobe signal DQS. . After the data alignment unit 150 aligns the rising data rising_data with the falling edge detection data dsfp of the data strobe signal DQS, the data alignment unit 150 aligns the falling data falling_data with the global data line 310. It is delivered until just before). The alignment data (align_data) and the falling data (falling_data) are transmitted to the global data line unit 700 in response to a data transfer signal data_strobe.

The CAS active command generates the internal cas signal excasp and the internal precharge signal pcg generated by combining the signal from the command input unit 260 in the command decoder 170. . In addition, the read cas signal generator 180 generates a read cas signal (casp_rd) for performing a read operation in response to the internal clock pulse signal (iclk), the write cas signal generator 190 is the internal The cas signal excasp and the internal precharge signal pcg are input to generate a write cas signal csa_pulse synchronized with the falling edge of the data strobe signal DQS, and the write cas signal cas_pulse signal is the data. The strobe signal data_strobe is generated and an address is detected to generate an internal address signal YI.

As described above, in the conventional write data DQ transmission scheme, the data is transferred in synchronization with the rising edge of the clock CLK by the falling edge of the data strobe call DQS. Alternatively, the write data DQ is polled by the data strobe signal DQS by synchronizing the control signal generated during the write operation with the rising edge of the clock CLK to the falling edge of the data strobe signal DQS. It is written as fast as the time difference [Delta] T between the edge and the rising edge of the clock CLK.

The read operation separates the circuit which makes the internal signal used in the write / read operation so that it can be used in synchronization with the rising edge of the clock CLK.

FIG. 5 is an exemplary diagram illustrating an internal circuit diagram of the write cas signal generation unit 190, and responds to the internal precharge signal pcg, the internal cas signal excasp, and the internal clock pulse signal iclk. An input unit 1000 for outputting a first signal, a first latch unit 2000 for latching a first signal from the input unit 1000, an output terminal N1 of the first latch unit 2000, The drain-source path is connected between the ground power supply terminals, and the NMOS transistor MN3 receives a gate input of a power-up signal pwrup, which is a signal for initializing the circuit, and the internal clock pulse signal iclk is responded to. The first transmission gate 3000 transferring the output signal of the first latch unit 2000 and the signal output from the first transmission gate 3000 are initialized to the second signal by the internal precharge signal pcg. The second latch unit 4000 for latching the internal clock pulse signal ic In response to lk, a second transfer gate 5000 for transferring a signal output from the second latch unit 4000 and an output signal from the second transfer gate 5000 are inverted to write a light enable signal ( An inverter INV5 for generating WT_enable and an output unit 6000 for outputting a write casing signal cas_pulse in response to the falling edge detection signal dsfp of the data strobe signal DQS.

Specifically, the input unit 1000 is connected between a power supply voltage terminal and a ground power supply terminal, and receives a first PMOS transistor MP1 that receives the internal precharge signal pcg, and the first PMOS transistor MP1. And a drain-source path connected to a common drain terminal and receiving the internal cas signal excasp through a gate input, and between a source terminal and a power ground terminal of the first N-MOS transistor MP1. And a second NMOS transistor MN2 connected to and receiving the internal clock pulse signal iclk through a gate input.

The second latch unit 4000 may receive an output signal of the first transfer gate 3000 at one input terminal and a negative logic gate NAND1 receiving the internal precharge signal pcg at a type force stage. The output terminal of the negative logical gate NAND is inverted and the output terminal is configured as an inverter INV4 connected to one input terminal of the negative logical gate NAND. The output unit 6000 includes the data strobe signal DQS. And a negative logic gate NAND2 that receives the write enable signal WT_enable and outputs a write cas signal cas_pulse in response to the polling edge detection signal dsfp.

6 is a diagram illustrating an operation timing diagram of the write cas signal generation unit.

5 and 6, when a write command is received from the outside, the first transmission gate 2000 is applied while the node 1 N1 transitions from low to high and the internal clock pulse signal iclk is high. When the internal clock pulse signal iclk becomes high again, the node is input to the falling edge detection signal dsfp with the write enable signal WT_enable high. And generates the write cas signal (cas_pulse) for performing the write operation. When the precharge signal PCG is input from the outside, the internal precharge signal pcg synchronized with the internal clock pulse signal iclk is generated to return the circuit to the initial state.

As a result, the write cas signal cas_pulse is generated in synchronization with the polling edge of the data strobe signal DQS.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention as described above, the write operation is performed according to the falling edge of the data strobe signal to be internally performed and the input data is aligned once, so that the write operation is performed by the falling edge of the data strobe signal and the rising edge of the clock. By making the difference as fast as possible, the cell data can be stabilized by lengthening the time that the last written data can be written.

Claims (7)

In DDR SDRAM, A data signal input from outside the chip is generated as a rising data signal synchronized with the rising edge of the data strobe signal and a falling data signal synchronized with the falling edge of the data strobe signal, respectively, and then the rising data signal and the falling data signal are generated. Data input means for aligning each other at the falling edge of the strobe signal to the global data line; A cas signal generation means for receiving a command from outside the chip and generating a write cas signal in synchronization with a polling edge of the data strobe signal during an internal write operation; And Means for transmitting said rising data signal and said falling data signal from said data input means to a global data line in response to said write cas signal; DDR SDRAM consisting of. The method of claim 1, The data input means, A buffer unit for buffering a data signal input from the outside of the chip; A rising data latch unit for generating a data signal from the buffer unit as a rising data signal latched in synchronization with the rising edge detection signal of the data strobe signal; A polling data latch unit for generating a data signal from the buffer unit as a polling data signal latched in synchronization with a polling edge detection signal of the data strobe signal; And An alignment unit for aligning the rising data signal in synchronization with a falling edge detection signal of the data strobe signal DDR SDRAM, characterized in that consisting of. The method of claim 1, The cas signal generation means, A read cas signal generator for generating a read cas signal in synchronization with the rising edge of the clock during a read operation; And Write casing signal generation section that generates a write casing signal synchronized with the falling edge of the data strobe signal during a write operation DDR SDRAM, characterized in that consisting of. The method of claim 3, The write cas signal generator, An input unit configured to output a first signal in response to an internal signal for performing a write operation; A first latch unit for latching the first signal; An NMOS transistor connected with a drain-source path between an output terminal of the first latch unit and a ground power supply terminal, and receiving a power-up signal for setting an initial value of a circuit to a gate input; A first transfer gate to transfer an output signal of the first latch unit in response to the internal clock pulse signal; A second latch unit for initializing and latching an output signal from the first transfer gate to a second signal by an internal precharge signal; A second transfer gate for transferring an output signal from the second latch unit in response to the internal clock pulse signal; An inverter configured to invert the output signal of the second transfer gate to generate a write enable signal; And A negative logic gate for outputting a write casing signal in response to a polling edge detection signal and a write enable signal of the data strobe signal. DDR SDRAM characterized in that the The method of claim 4, wherein The input unit, A first PMOS transistor connected to a power voltage terminal and a source-drain path and receiving the internal precharge signal through a gate input; A first N-MOS transistor having a common drain connected to the first PMOS transistor and receiving the internal CAS signal through a gate input; And A second N-MOS transistor connected with a source-drain path between a ground power supply terminal and a drain terminal of the first N-MOS transistor and receiving the internal clock pulse signal through a gate input; DDR SDRAM characterized in that provided with. The method of claim 4, wherein The first latch unit, A first inverter receiving the first signal and inverting the first signal; And A second inverter in which an output signal of the first inverter is received and its output terminal is connected to an input terminal of the first inverter DDR SDRAM characterized in that provided with. The method of claim 4, wherein The second latch unit, A negative logic gate receiving the output signal of the first transmission gate at one input terminal and the internal precharge signal at a type power stage; And An inverter having an output signal of the negative logical gate and its output terminal connected to one input terminal of the negative logical gate DDR SDRAM characterized in that provided with.