KR100728971B1 - Circuit for controling clock of data output according to cal latency - Google Patents

Abstract

A circuit for controlling a data output clock according to CAS latency is provided to assure normal data output even when CAS latency is less than delay time due to the logic configuration in a DRAM, by synchronizing data output to rising edge of an internal clock. A circuit is for controlling a data output clock by delaying an internal clock according to a CAS latency signal in a semiconductor memory. A delay part(delay) receives the internal clock and the CAS latency signal, and delays the internal clock when the CAS latency signal is enabled. The CAS latency signal is enabled when data output delay time generated by a data output path in the semiconductor memory is greater than CAS latency, in case where a read command from the outside is applied.

Description

Circuit for controling clock of data output according to CAL Latency}

1 is a block diagram of a DRAM performing a conventional read command;

2 is a data output timing diagram according to cas latency in the block of the DRAM of FIG.

3 is a block diagram illustrating a DRAM performing a read command according to an embodiment of the present invention;

4 is a detailed circuit diagram illustrating the data output clock control circuit of FIG. 3;

5 is another detailed circuit diagram illustrating the data output clock control circuit of FIG. 3;

6 illustrates another embodiment of the floating node protection circuit of FIG. 4 or 5;

FIG. 7 illustrates another embodiment of the floating node protection circuit of FIG. 4 or 5;

8 is a data output timing diagram according to cas latency in the block of the DRAM of FIG. 3.

The present invention relates to a data output clock control circuit, and more particularly, to a circuit for adjusting the data output time by controlling the data output clock according to the cas latency.

In general, CAS latency (CL) refers to a delay time caused by logic configuration inside a dynamic random access memory (DRAM) when a read command is applied from the outside.

The delay time caused by the logic structure inside the DRAM does not change even when the clock frequency changes.When the clock frequency changes, the CAS latency can be changed through the mode register set (MRS), which allows the DRAM internal logic to perform normal operation. Make sure

Here, the mode register set (MRS) is to extend the memory operability by setting the cas latency (CL), burst type (Burst Type), burst length (BL) and the like according to the user's environment. It has been applied since SDRAM (Synchronous DRAM) products.

The mode register set MRS is set when an MRS command and an address A0 to A11 of a state machine for decoding the control signals / RAS, / CAS and / WE are input.

For example, in accordance with the specification of the SDRAM, addresses A0 to A2 determine the burst lengths BL2, BL4, and BL8, addresses A3 determine the burst type (sequential, interleave), and A4 to A6 indicate the cascade latency ( CL2, CL3, CL4, etc.), and A7 determines whether it is a test mode or a normal operation mode.

1 is a block diagram illustrating a DRAM for performing a conventional read command. Referring to FIG. 1, a block of a DRAM that performs a conventional read command has a configuration in which data iData is output to the data terminal DQ in synchronization with the same internal clock dCLK even if the cas latency CL changes. .

In other words, the input / output control unit (I / O control) receives an external clock (CLK) internally regardless of whether the cascade latency (CL) is changed to 2, 3, 4, etc. from the mode register. Generate a clock dCLK. Therefore, the data I / O buffer synchronizes the data iData with the data terminal DQ in synchronization with the internal clock dCLK output from the I / O control regardless of the cascade latency CL. Will be printed).

However, when the clock is speeded up, a block configuration of a DRAM that performs a conventional read command may output abnormal data when the cas latency CL is not sufficient compared to a delay caused by a logic configuration inside the DRAM. . Hereinafter, the conventional problem will be described in more detail with reference to FIG. 2.

 FIG. 2 is a data output timing diagram according to cas latency in the block of the DRAM of FIG. 1. Referring to FIG. 2, the data iData is rising at the rising edge of the internal clock dCLK when the cas latency CL is sufficient CL = 3 and CL = 4 compared to the delay time caused by the logic configuration inside the DRAM. In synchronization with the edge, the data terminal DQ can be accurately transmitted to the data terminal DQ.

However, when the cas latency (CL) is CL = 2, which is not sufficient compared to the delay caused by the logic configuration inside the DRAM, the data (iData) is not accurately synchronized to the rising edge of the internal clock (dCLK). Because of this, it can be transferred to the data terminal DQ in an abnormal state.

That is, when the cascade latency CL is smaller than the delay caused by the logic configuration inside the DRAM, the valid data window is out of the rising edge of the internal clock dCLK, thereby outputting a normal data signal. This is not guaranteed.

In particular, this can cause serious problems in the case of SDRAM which inputs the clock into the memory and controls all the input / output signals in synchronization with the rising edge of the clock so that the system clock can operate the memory.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a data output clock control circuit for controlling a data output time by controlling a data output clock according to cas latency.

In order to achieve the above object, the present invention is a data output clock control circuit for delaying and outputting the internal clock according to the cascade latency signal in a semiconductor memory, the internal clock and the cascade latency signal is received, When enabled, a delay unit for delaying and outputting the internal clock by a predetermined time, wherein the cas latency signal has a data output delay time generated by a data output path inside the semiconductor memory when a read command is applied from the outside. It is preferred to be enabled when greater than cas latency.

Here, the predetermined time is preferably larger than the difference between the data output delay time and the cascade latency.

The present invention may further include a first transfer gate which is turned on when the cas latency signal is enabled and transmits the internal clock to the delay unit, and a second gate which is turned on when the cas latency signal is enabled and receives and outputs the output of the delay part. And a third transfer gate that is turned on to receive and output the internal clock when the transfer gate and the cas latency signal are disabled.

The present invention also provides a first NMOS transistor including a drain connected to a connection node of the first transfer gate and the delay unit, a source connected to a ground voltage, and a gate turned on when the cas latency signal is disabled. And a first latch connected to a connection node of the delay unit or a drain connected to the connection node of the first transfer gate and the delay unit, a source connected to a power supply, and a gate turned on when the cas latency signal is enabled. It further includes a transistor.

In addition, the present invention is the first inverter for inverting the phase of the internal clock when the cas latency signal is enabled and input to the delay unit, when the cas latency signal is enabled is turned on to invert the phase of the output signal of the delay unit A second inverter for outputting, a third inverter for inverting the phase of the internal clock when the cas latency signal is disabled, and an inverting phase of the output signal of the third inverter when the cas latency signal is disabled A fourth inverter is further included.

The present invention also provides a second NMOS transistor including a drain connected to a connection node of the first inverter and the delay unit, a source connected to a ground voltage, and a gate turned on when the cas latency signal is disabled, the third inverter and the third inverter. And a third NMOS transistor having a drain connected to a connection node of a fourth inverter, a source connected with a ground voltage, and a gate turned on when the cas latency signal is enabled.

The present invention further includes a second latch connected to a connection node of the first inverter and the delay unit, and a third latch connected to a connection node of the third inverter and the fourth inverter.

The present invention also provides a second PMOS transistor including a drain connected to a connection node of the first inverter and the delay unit, a source connected to a power supply voltage, and a gate which is turned on when the cas latency signal is enabled. And a third PMOS transistor having a drain connected to a connection node of an inverter, a source connected to a power supply voltage, and a gate turned on when the cas latency signal is disabled.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating a DRAM for performing a read command according to an embodiment of the present invention. As shown in FIG. 3, a DRAM performing a read command according to an embodiment of the present invention may include a state machine 10, an address buffer 20, a row decoder 30, a column decoder 40, and a memory cell array. 50, a mode register 60, an input / output control unit 70, a data output clock control unit 80, and a data input / output buffer 90.

The state machine 10 receives a clock CLK, a clock enable signal CKE, and a control signal / CS, / RAS, / CAS, / WE to determine the state of the DRAM.

The state machine 10 has a / CS signal 'LOW', a / RAS signal 'LOW', a / CAS signal 'LOW' and a / WE signal 'LOW'. In this case, according to an embodiment of the present invention, it is preferable to output a mode register set command (MRS) to change the cascade latency using the mode register 60 to the mode register 60.

The state machine 10 further includes an active command ACTIVE for activating a word line of a memory cell according to a combination of levels of control signals, a read command READ for inputting and outputting data of the memory cell, a write command WRITE, and the like. Can be generated.

The address buffer 20 receives addresses A0 to An and bank addresses BA0 and BA1 and outputs them to the row decoder 30, the column decoder 40, and the mode register 60.

The row decoder 30 activates a word line corresponding to the address of the address buffer 20 according to the active command ACTIVE of the state machine 10.

The column decoder 40 selects a bit line corresponding to the address of the address buffer 20 according to a read command of the state machine 10 and selects the data iData of the selected memory cell from the data input / output buffer 90. )

The memory cell array 50 is a collection of memory cells in which data is stored. Each memory cell is specified by a word line selected by the row decoder 30 and a bit line selected by the column decoder 40 to exchange data iData with the data input / output buffer 90.

When the mode register 60 receives an MRS command from the state machine 10, the mode register 60 is set according to the address A0 to An, BA0, and BA1 information of the address buffer 20.

The mode register 60 can change the cas latency, for example, CL = 1 if data of A6, A5, A4 is "001", CL = 2 if "010", CL = if "011". 3, CL = 4.

That is, the mode register 60 receives an MRS command and addresses A0 to An, BA0, and BA1 to change and set a cas latency, and generates the cas latency information as a cas latency signal CLsig. ) And the data clock control unit 80.

The I / O control 70 receives an external clock CLK and generates an internal clock dCLK necessary for input / output of data iData.

The data output clock control unit 80 receives the internal clock dCLK from the input / output control unit 70 and the cas latency signal CLsig from the mode register 60. The CL internal clock dCLK_CL is considered and output to the data input / output buffer 90.

Here, the CL internal clock dCLK_CL refers to a clock which delays the internal clock dCLK when the cas latency is not sufficient compared to the delay time caused by the logic configuration in the DRAM.

Accordingly, the data output clock controller 80 guarantees output of normal data (iData) even when the cas latency is smaller than a delay time due to a logic configuration in the DRAM.

The data I / O buffer 90 synchronizes the data iData output from the memory cell array 50 to the CL internal clock dCLK_CL of the data output clock controller 80 so as to synchronize the data terminal DQ. )

4 is a detailed circuit diagram illustrating the data output clock control circuit of FIG. 3. As shown in FIG. 4, the data output clock control circuit of FIG. 3 is driven when the cas latency signal CLsig is enabled with 'HIGH' to delay the internal clock dCLK by a predetermined time, and then, this is performed. When the transfer gates TG1 and TG2 that are output to the CL internal clock dCLK_CL and the delay and cas latency signals CLsig are deactivated to LOW, the internal clock dCLK is delayed. It includes a transfer gate (TG3) that transmits without the output to the CL internal clock (dCLK_CL). The delay unit may include at least one inverter (not shown) for delaying and outputting an input signal.

Hereinafter, in consideration of the convenience of description, when the cas latency is 2, it is assumed that the cas latency is smaller than the delay time due to the logic configuration inside the DRAM, so that abnormal data output may occur. That is, the cas latency signal CLsig is enabled when the cas latency is 2, and is disabled when the cas latency is greater than 2.

In this case, a predetermined time for the delay delaying the internal clock dCLK is used to compensate for the difference in delay caused by the cascade latency and the logic configuration inside the DRAM, and the cas latency (CL = 2) and the internal DRAM. It is desirable to be larger than the difference in latency caused by the logic configuration. The predetermined time at which the delay delays the internal clock dCLK may be selected to be optimal by the experimental value.

On the other hand, the cascade latency signal CLsig is not limited to the cascade latency of 2, for example, when the cascade latency is 3, the cascade latency is not sufficient compared to the delay caused by the logic configuration inside the DRAM. The cas latency signal CLsig may be enabled when the cas latency is less than or equal to 3, and may be disabled when the cas latency is greater than three. At this time, it is preferable that a predetermined time for the delay delaying the internal clock dCLK is set to ensure stable output of data (iData) not only when the cas latency is 3 but also when the cas latency is 2. Do.

The data output clock control circuit may further include a floating node prevention circuit that prevents the node 1 ND1 from floating on the node 1 ND1, which is a connection portion between the transfer gate TG1 and the delay unit. desirable.

The floating node protection circuit connected to node 1 may be an NMOS transistor N1 having a node 1 (ND1) connected to a drain, a ground voltage (GND) connected to a source, and a cas latency signal CLsigB applied to a gate thereof. .

The NMOS transistor N1 is turned on when the cas latency signal CLsig is set to 'LOW' and the transfer gates TG1 and TG2 and the delay unit are not driven, thereby turning on the node 1 (ND1). The potential is fixed at the ground voltage (GND) level. Therefore, the floating node prevention circuit prevents current consumption by the inverter of the delay unit when the node 1 ND1 is floated.

FIG. 5 is another detailed circuit diagram illustrating the data output clock control circuit of FIG. 3. As shown in FIG. 5, the data output clock control circuit of FIG. 3 is driven when the cas latency signal CLsig is enabled with 'HIGH' to delay the internal clock dCLK by a predetermined time, and then, this is performed. When the inverters INV1 and INV2 output to the CL internal clock dCLK_CL, the delay unit, and the cas latency signal CLsig are deactivated to 'LOW', the internal clock dCLK is driven without delay. It includes inverters INV3 and INV4 that transmit and output to the CL internal clock dCLK_CL. Since the configuration of the delay unit and the predetermined time at which the delay unit delays the internal clock dCLK are the same as those described with reference to FIG. 4, a detailed description thereof will be omitted.

The inverter INV1 positioned in the same path as the delay unit has a PMOS transistor P1 to which a power supply voltage VCC is applied as a source, and a cas latency signal CLsigB is input to a gate, and a PMOS transistor as a source. An NMOS transistor P2 connected to the drain of P1, to which an internal clock dCLK is applied as a gate, and a drain connected to the drain of the PMOS transistor P2 to a gate, and an internal clock dCLK to a gate thereof. And an NMOS transistor N2 connected to the source of the nMOS transistor N2, the ground voltage GND is applied to the source, and the cas latency signal CLsigB is input to the gate. . At this time, the connection portion between the drain of the PMOS transistor P2 and the drain of the NMOS transistor N2 operates as an output terminal of the inverter INV1.

The inverter INV2 has the same configuration as the inverter INV1, but is inverted by the inverter INV1 to the gates of the PMOS transistor P2 and the NMOS transistor N2 and then delayed by the delay unit delay. dCLK) is applied.

Inverter INV3, which is not located in the same path as the delay unit, has the same configuration as inverter INV1, but the cascade latency CLsig is applied to the gate of PMOS transistor P1, and the NMOS transistor N3 The cas latency bar signal CLsigB is applied to the gate. The inverter INV4 has the same configuration as the inverter INV3, but the internal clock dCLK inverted by the inverter INV3 is applied to the gates of the PMOS transistor P2 and the NMOS transistor N2.

In addition, the data output clock control circuit includes a node 2 (ND2) and a node 2 (ND2) to which the inverter INV1 and a delay unit are connected, and a node 2 (ND2) and a node 3 (ND3) to which the inverter INV3 and the inverter INV4 are connected. Preferably, the node 3 further includes floating node preventing circuits N1 'and N1 "which prevent the node 3 ND3 from floating.

The floating node protection circuits N1 ′ and N1 ″ may be the floating node protection circuit described with reference to FIG. 4. However, the floating prevention circuit N1 ″ ″ connected to the node 3 ND3 may have a cas latency signal CLsig at its gate. Is preferably an NMOS transistor N1 " that is turned on when the cas latency signal CLsig is 'HIGH'.

FIG. 6 is a diagram illustrating another embodiment of the floating node protection circuit of FIG. 4 or 5. As shown in FIG. 6, the floating node prevention circuit 'high' or 'low' sets the potential of the node 1, the node 2, and the node 3 (ND1, ND2, ND3) regardless of whether the delay unit is driven. It may be a latch circuit that is fixed at the 'level. Accordingly, the floating node prevention circuit prevents current consumption by the inverter of the delay unit when the nodes ND1, ND2, and ND3 are floated.

FIG. 7 is a view showing another embodiment of the floating node protection circuit of FIG. 4 or 5. As shown in FIG. 7, the floating node protection circuit is supplied with a power supply voltage VCC to a drain, and a source is a node. It may be a PMOS transistor connected to 1 (ND1) or node 2 (ND2) and to which a cas latency signal CLsig is applied to a gate. In addition, when the source is a PMOS transistor connected to the node 3, it is preferable that the cas latency bar signal CLsigB is applied to the gate.

In contrast to FIG. 4, when the floating node protection circuit is configured as a PMOS transistor, the floating node protection circuit fixes the potentials of the nodes ND1, ND2, and ND3 to the power supply voltage VCC level. Therefore, the floating node prevention circuit prevents current consumption by the inverter and the inverters INV1, INV2, INV3, and INV4 of the delay unit when the nodes ND1, ND2, and ND3 are floated.

Hereinafter, an operation of a block of a DRAM that performs a read command according to an embodiment of the present invention will be described with reference to a data output timing diagram according to cas latency.

8 is a data output timing diagram according to cas latency in the block of the DRAM of FIG. 3. As shown in FIG. 8, a DRAM block that performs a read command according to an embodiment of the present invention operates using an internal clock or a delayed internal clock according to cas latency.

First, the case where the cas latency is 2 will be described. When the cas latency is 2, the cas latency signal CLsig is enabled as 'HIGH' and is input to the data output clock controller 80.

The data output clock controller 80 outputs the CL internal clock dCLK_CL to the data input / output buffer 90, which is generated by delaying the input internal clock dCLK for a predetermined time through a delay unit. That is, when the cascade latency is 2, the data output input / output buffer 90 normally outputs the data iData to the data terminal DQ in synchronization with the rising edge of the CL internal clock dCLK_CL, which is a delayed internal clock. .

Therefore, when the conventional CAS latency is 2, the CAS latency is less than the delay time caused by the logic configuration inside the DRAM, thereby eliminating the problem that the output of data is not synchronized to the rising edge of the internal clock dLCK. .

Next, the case where the cas latency is larger than 2 will be described. When the cas latency is greater than 2, that is, when the cas latency is 3 or 4, the cas latency signal CLsig is disabled as 'LOW' and is input to the data output clock controller 80.

The data output clock controller 80 outputs the internal clock dCLK without delay as the CL internal clock dCLK_CL to the data input / output buffer 90 as it is. That is, when the cas latency is greater than 2, the data input / output buffer 90 outputs data iData to the data terminal DQ in synchronization with the rising edge of the CL internal clock dCLK_CL, which is an internal clock without delay.

As described above, the data output clock control circuit of the present invention adjusts the data output time by controlling the data clock according to the cas latency, so that the internal clock is maintained even when the cas latency is smaller than the delay time due to the logic configuration in the DRAM. The output of the data is synchronized with the rising edge to ensure normal data output.

In addition, preferred embodiments of the present invention are disclosed for the purpose of illustration, those skilled in the art will be able to various modifications, changes, additions, etc. within the spirit and scope of the present invention, these modifications and changes should be seen as belonging to the following claims. something to do.

Claims (12)

A data output clock control circuit for delaying and outputting an internal clock according to a cas latency signal in a semiconductor memory, A delay unit configured to receive the internal clock and the cas latency signal and to delay and output the internal clock by a predetermined time when the cas latency signal is enabled, The cas latency signal is enabled when the data output delay time generated by the data output path inside the semiconductor memory is greater than the cas latency when a read command is applied from the outside. Data output clock control circuit. The method of claim 1, wherein the predetermined time is Greater than the difference between the data output delay time and cas Data output clock control circuit. The method of claim 1, A first transfer gate turned on when the cas latency signal is enabled to transfer the internal clock to the delay unit; And a second transfer gate which is turned on when the cas latency signal is enabled and receives and outputs the output of the delay unit. Data output clock control circuit. The method of claim 3, wherein And a third transfer gate which is turned on when the cas latency signal is disabled and receives and outputs the internal clock. Data output clock control circuit. The method of claim 3, wherein And a first NMOS transistor including a drain connected to a connection node of the first transfer gate and the delay unit, a source connected to a ground voltage, and a gate turned on when the cas latency signal is disabled. Data output clock control circuit. The method of claim 3, wherein And a first latch connected to a connection node of the first transfer gate and the delay unit. Data output clock control circuit. The method of claim 3, wherein And a first PMOS transistor having a drain connected to a connection node of the first transfer gate and the delay unit, a source connected to a power supply voltage, and a gate turned on when the cas latency signal is enabled. Data output clock control circuit. The method of claim 1, A first inverter for inverting a phase of the internal clock and inputting the delayed signal to the delay unit when the cas latency signal is enabled; And a second inverter that is turned on when the cas latency signal is enabled and inverts a phase of an output signal of the delay unit. Data output clock control circuit. The method of claim 8, A third inverter for inverting and outputting a phase of the internal clock when the cas latency signal is disabled; And a fourth inverter configured to invert and output a phase of an output signal of the third inverter when the cas latency signal is disabled. Data output clock control circuit. The method of claim 8, A second NMOS transistor having a drain connected to a connection node of the first inverter and the delay unit, a source connected to a ground voltage, and a gate turned on when the cas latency signal is disabled; And a third NMOS transistor having a drain connected to a connection node of the third inverter and the fourth inverter, a source connected with a ground voltage, and a gate turned on when the cas latency signal is enabled. Data output clock control circuit. The method of claim 8, A second latch connected to a connection node of the first inverter and the delay unit; And a third latch connected to a connection node of the third inverter and the fourth inverter. Data output clock control circuit. The method of claim 3, wherein A second PMOS transistor having a drain connected to a connection node of the first inverter and the delay unit, a source connected to a power supply voltage, and a gate turned on when the cas latency signal is enabled; And a third PMOS transistor having a drain connected to a connection node of the third inverter and the fourth inverter, a source to which a power supply voltage is connected, and a gate which is turned on when the cas latency signal is disabled. Data output clock control circuit.

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