JP3317592B2 - Memory system and image forming system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system using a synchronous DRAM (synchronous dynamic random access memory) as an image memory for storing image data, and further uses the memory system. The present invention relates to an image forming system including an image forming apparatus such as a printer and a copying machine.

[0001]

2. Description of the Related Art Conventionally, an image memory has been constituted by a DRAM of a high-speed page mode and a static column mode in order to realize a large capacity and a low cost.

A high-speed page mode DRAM can perform random access to the same address at a high speed by re-inputting the CAS and the column address while RAS is asserted.

[0003] Static column mode DRAM
The high-speed access to the same row address can be performed as in the high-speed page mode by changing the column address while RAS is asserted. Since there is no need to strobe, the speed can be increased.

In a nibble mode DRAM, after normal access is completed, CAS is toggled while RAS is asserted, so that the data of the address in which the lower 2 bits are incremented is read. It is accessed kenshal. The nibble mode has a feature that, although only four words can be accessed in burst, it is faster than other modes.

[0005] However, even if it can be accessed at high speed, there is naturally a limit, and the cycle time is about 40 nsec (25 MHz). SRAM had to be used. In addition, when the bus width is increased, while speeding up is possible, there are various problems such as a complicated control circuit, an increase in delay time, and an increase in a minimum configuration unit constituting the memory system.

In recent years, a synchronous DRAM has been proposed as described in Japanese Patent Application Laid-Open No. 5-120114. This synchronous DRAM is a completely synchronous type of the conventional DRAM described above.
A row address, column address entry, refresh, etc. are given as commands to the rising edge of the clock.

More specifically, with respect to data reading, the access time until the first data is equal to that of a conventional DRAM.
However, the following data is output every clock. Since the access order at this time is set in the mode setting, there is no need to input a column address for each clock. Regarding data writing, data can be input for each clock from the first data. Since the clock cycle is as fast as 100 MHz, high-speed access is possible.

Further, since the synchronous DRAM is of a completely synchronous type, it is sufficient that an input signal satisfies a setup and a hold time with respect to a clock, and an output signal from the clock can be applied to an output signal. Since it is defined as time, it is relatively easy to realize a control circuit.

[0009]

As described above, by using a synchronous DRAM, it is possible to provide a memory system capable of improving the processing speed of a CPU. When trying to enter power down mode, the clock
A problem arises with the fact that the bull signal (CKE) must be changed at a high speed.

[0010] The clock enable signal (CKE) can be used to invalidate the rising edge of the clock in addition to controlling the power down mode. Not required by the system. In this case, the clock enable signal (CK)
The hardware related to the control of E) can be simplified, but in order to cope with the power down mode, the clock enable is required.
It is necessary to change the bull signal (CKE) at high speed.

In particular, when a large number of synchronous DRAMs are used as in an image memory for storing image data, the load capacity connected to the clock enable signal (CKE) becomes large, and buffering is required. There is. Moreover, unlike the RAS and CAS signals, the clock enable signal must always satisfy the setup and hold time with respect to the rising edge of the clock signal.

For this reason, when the synchronous DRAM control circuit is constituted by an ASIC, it is difficult to assign an external pin of the ASIC as a clock enable signal (CKE) control signal, or to externally provide a high-speed buffer or a D flip-flop. Had to be provided. In addition, there is a problem that there are many signal lines for which attention must be paid to the waveform quality.

On the other hand, when a synchronous DRAM is used as an image memory, it is not necessary that image data always exist in an image forming operation, and therefore it is not necessary to always store the contents of the memory. .

The present invention has been made in view of the above-mentioned technical problem, and an object of the present invention is to reduce the number of signal lines for which attention must be paid to the amount of hardware and waveform quality while reducing the number of signal lines. To provide a memory system and an image forming system capable of setting a power-down mode used as an energy-saving mode only in an area where power must be reduced and a storage content must be held. It is in.

[0015]

In order to achieve the above object, the present invention provides a memory system using a plurality of synchronous DRAMs as storage means for storing image data .
Setting the power down mode by fixing the input of the clock enable terminal of a portion of a synchronous DRA M to the high level
And disable the clock enable pin.
Other synchronous whose input is not fixed to high level
When the DRAM is set to power down mode,
Refresh required for some synchronous DRAMs
Request to invalidate the refresh cycle
The memory system is configured so as not to compensate for the security period .
Further, an image forming system is configured using such a memory system. Note that image data stored in a plurality of synchronous DRAMs is provided from a scanner device or a host device.

[0016]

An embodiment of the present invention will be described. FIG.
FIG. 1 is an overall block diagram showing an embodiment of the present invention.

The CPU 101 is a central processing unit, which controls the entire system, performs image processing, and the like. Also, CPU
101 has a cache memory on-chip.
A program executed by the CPU 101 is stored in the ROM 102,
Various parameters and the like are stored.

The scanner interface 103 interfaces with a scanner device (not shown). The printer interface 105 interfaces with a printer (not shown).

The image memory 106 is composed of a plurality of chips of synchronous DRAM (synchronous dynamic random access memory), and includes scanner data and host data as image information read from a scanner device via a scanner interface. It stores image data as image information read from the apparatus via the host interface. Further, this image memory 106
In addition to simply storing image data, the CPU 101
May be used as a working memory or as a download destination of an instruction (instruction) to execute a program.

The image data stored in the image memory 106 is sent to a printer (not shown) via a printer interface.

When a synchronous DRAM is used as an image memory, the image memory is formed by a plurality of synchronous DRAM chips as described above. Generally, an 8-chip or 12-chip synchronous DRAM is used, depending on the capacity used as an image memory. External access of the CPU 101 is performed via the ASIC 107.

FIG. 2 is an internal block diagram of the ASIC 107 in FIG.

CPU interface unit 201
Manages an interface with the CPU 101, and
When the server 101 issues an external access request,
Request the right to use the bus to 203. If the bus has been acquired, the service for the CPU 101 is started.

The refresh control unit 202 has a counter therein, and requests a refresh to the arbiter 203 when the value of the counter reaches a constant value.

The arbiter 203 comprises a CPU interface unit 201 and a refresh control unit 202.
Arbitration of the request from the synchronous DRAM control unit 204 according to the request content.
Issue an instruction to the I / O control unit 205.

The synchronous DRAM control unit 204
Executes a service for an access request to the synchronous DRAM and a refresh request. The synchronous DRAM control unit is provided with a power-down control register. The power-down mode is a power-saving mode only for a specific area, the power-down mode is canceled, and the refresh request is invalidated. Is possible. I /
The O control unit 205 executes a service for an access request to the I / O space.

FIG. 3 shows a timing chart of a normal refresh execution. When the refresh control unit 202 sets the signal REFREQ to the L (low) level at the 0th clock, a refresh request is issued. I do. The arbiter 203 receives this, and receives the synchronous DR.
After confirming that the AM control unit is in a state in which the refresh request can be accepted, it is determined that there is no request having a high priority, and the signal REFACK is set to L at the first clock.
(B) indicates that the refresh request has been accepted. The refresh control unit 202 recognizes that the refresh request has been acknowledged at the second clock, and negates the refresh request (sets the signal REFREQ to H (high) level).

On the other hand, the synchronous DRAM control unit detects that REFACK is at the L (low) level and issues a refresh command to the synchronous DRAM. In this case, the internal power down is performed. Since the control register is not in the power down mode,
The signals CS0 and CS1 are both set to L (low) level, the signals RAS and CAS are set to L (low) level, and the signal W
By setting E to H (high) level, a command is issued to refresh the entire area (in this embodiment, a two-bank configuration). In the present embodiment, the simultaneous refresh command is issued for two banks, but a configuration may be employed in which a divided refresh is performed. The clock enable signals CKE0 and CKE1 corresponding to the banks 0 and 1, respectively, are always fixed at H (high) level.

FIG. 4 shows a state in which only the area of the bank 0 is in the power down mode and the refresh request is invalidated since the power down mode is being performed. First,
At the 0th clock, the signals RAS, CAS, CS0, CKE0
Is set to the L (low) level, whereby the power down mode is set in the self-refresh state. The clock enable signal CKE1 for the bank 1 is always fixed at H (high). Here, the self-refresh state is
This refers to a state in which refresh is internally performed without giving a refresh command from the outside.

At the second clock, the refresh control unit issues a refresh request, and at the third clock,
The bitter acknowledges this, but the synchronous DRAM control unit does not issue a refresh command because the internal power-down control register is in the power-down mode. Although not shown in FIG. 4, the signal CKE0 is set to H (high) because the CPU has written to the power-down control register at the sixth clock so as to release the power-down mode. ) Set the level and issue a command to release from the power down mode.

As described above, the power in the area of bank 0 is
Since the refresh operation is not performed in the bank 1 area in response to the down mode, the load capacity connected to the CKE signal can be reduced, and the bank 1 area can be consumed without the power down mode. Power can be reduced. It should be noted that the memory contents of the bank 1 are not guaranteed, but no problem occurs if the bank 1 is cleared before use.

[0032]

As described above, according to the present invention,
Only some of the synchronous DRAMs are refreshed, and power consumption can be greatly reduced. Also, while achieving an effect close to the power down mode, which is a power saving mode, the number of signals for which attention must be paid to the amount of hardware and waveform quality as compared to the case of the power down mode is reduced. It can be significantly reduced. In addition, a power-down mode can be applied to an area where the contents of the memory must be held.

[0033]

[Brief description of the drawings]

FIG. 1 is an overall block diagram of an embodiment according to the present invention. FIG. 2 is an internal block diagram of the ASIC 107 shown in FIG. FIG. 3 is a timing chart of the refresh execution. FIG. 4 is a timing chart of another refresh execution.

[0034]

[Explanation of symbols]

 101 CPU 102 ROM 103 Scanner Interface 104 Host Interface 105 Printer Interface 106 Image Memory 107 ASIC 201 CPU Interface Unit 202 Refresh Control Unit 203 Arbiter 204 Synchronous DRAM Control Unit 205 I / O Control unit

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Tomoki Ishii 1-3-6 Nakamagome, Ota-ku, Tokyo Ricoh Co., Ltd. (56) References JP-A-1-260690 (JP, A) JP-A-1 -201890 (JP, A) JP-A-6-255184 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 1/32 G06F 12/00-12/06 G11C 7/00 G06T 1/60

Claims (4)

(57) [Claims] In a memory system using a plurality of synchronous DRAMs as storage means for storing image data, one of said plurality of synchronous DRAMs is provided .
Setting the power-down mode by fixing the input of the clock enable terminal of the synchronous DRAM parts to the high level
And disable the clock enable pin.
Other synchronous D whose power is not fixed to high level
When the RAM is set to the power down mode,
Refresh request for some synchronous DRAMs
Refresh cycle to maintain memory contents by invalidating
A memory system characterized in that the reservation is not compensated . Wherein with use of a plurality of synchronous DRAM as storage means for storing image data, before
Among the plurality of synchronous DRAMs, the input of the clock enable terminal of some of the synchronous DRAMs is fixed at a high level to disable the setting of the power down mode,
The clock enable pin input is fixed at high level.
Other synchronous DRAM is not in power down mode.
When set to the mode, some of the synchronous DRA
Invalidate the refresh request for M
An image forming system, wherein a memory system is configured so as not to compensate for ensuring a refresh cycle for holding, and the memory system is connected to a printer via a printer interface. 3. The image forming system according to claim 2, wherein said image data is based on image information provided from a scanner device. 4. The image forming system according to claim 2, wherein said image data is based on image information provided from a host device.