JPH08101793A - Memory system - Google Patents

Abstract

PURPOSE: To provide the memory system capable or quick access to any access address. CONSTITUTION: In the memory system which uses plural synchronous DRAM chips 201 and 202 as storage means, a control line and a data line from a CPU other than a chip select line are connected to synchronous DRAM chips 201 and 202, and a holding means which holds the address of the synchronous DRAM validated at present and a comparison means which compares the address stored in the holding means with the next request address are provided, and the access to synchronous DRAM chips 201 and 202 is controlled in accordance with the comparison result of the comparison means.

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory system controlled by a CPU. More specifically, the present invention relates to an image memory system used in a printer device, a scanner device, and the like.

[0001]

2. Description of the Related Art As the processing speed of a CPU (central processing unit) increases, the ratio of memory access time to the entire processing increases, and this improvement measure has been studied. 2. Description of the Related Art In recent years, SDRAMs (synchronous DRAMs) for accessing data access commands and read / write access data themselves in synchronization with clock signals have become available. .

This SDRAM has a structure similar to that of a conventional DRAM, but the interface portion is clock-synchronized, and the order of addresses during burst access is internal to the SDRAM. Can be set in a register. Therefore, at the time of burst reading, if an address is given first, the first data can be sampled after the time set in the register (after the time set as CAS latency), and the register is set for each clock from there. Length (the length set as the burst length),
Sequentially accessed data can be sampled in the order set by the register. The same applies to burst write. If an address is given first and write data is given for each clock, continuous writing can be performed with the length and order set by the register.

Therefore, unlike the conventional DRAM, it is not necessary to always give an address or change the strobe signal at the time of burst access, so that high speed data access is possible. SDRAM (synchronous DRA
M) For the configuration of itself, see, for example, JP-A-5-120.
No. 114 and the like.

[0004]

As described above, SDRA
M is a relatively simple control circuit because all data access is performed in synchronization with the clock signal, and only the first address is input and the subsequent access order is determined by the mode set value. It can be realized and high speed access is possible.

However, the time until the first data is obtained is the same as that of the conventional DRAM and requires a predetermined time. In order to improve this, a method corresponding to the conventional page mode, that is, a page different from the page of the bank currently being accessed is accessed instead of performing a precharge each time of access. In this case, a method of performing precharge can be used. In this case, if the same page is being accessed, all that is required is to input the column address, so high-speed access is possible, but a page different from the page of the bank currently being accessed is available. When accessing, execute the precharge after recognizing that it is a different page, and enter the page containing the address you want to access.
However, since it takes a step of inputting the local address of the data and then the column address to perform the reading, there is a problem that it takes extra time.

The present invention has been made in view of the above technical problems, and an object of the present invention is to provide a memory system capable of high-speed access to any access address.

[0007]

In order to achieve the above object, the present invention is directed to a memory system which uses a plurality of synchronous DRAM chips as a storage means, except for a control line and a data line from a CPU except a chip select line. The data line is connected to each chip of the synchronous DRAM, and the synchronous DRAM currently in effect.
To the synchronous DRAM chip according to the comparison result of the comparing means. The holding means holds the address of the holding means and the comparing means for comparing the address stored in the holding means with the next request address. Configured to control access.

[0008]

EXAMPLE An example of the present invention will be described. FIG.
FIG. 3 is a block diagram showing a memory system of one embodiment of the present invention.

The CPU 101 has a cache memory for storing instructions (instructions) and data internally, that is, on a chip, and external access is single read / write or burst read / write. Perform with lights. The CPU in this embodiment is an R40 manufactured by MIPS.
RISC type (Reducible instruction set type) CP based on 00 standard
I'm using U.

The control ASIC 102 controls the access of the low-speed I / O 103 in response to an access request from the CPU 101 and SDRAM (synchronous DRAM) 1
Control for 04 access is performed.

The low speed I / O 103 is composed of a DUART, a ROM, etc. for communicating with the outside.
The DUART is a serial communication device including an interface with a CPU. Reference numeral 104 is an SDRAM (synchronous dynamic random access memory), and is specifically used as an image memory of a printer, a scanner, or the like.

FIG. 2 shows details of the SDRAM 104 in FIG. In this embodiment, 1M * 1
Two 16-Mbit SDRAMs of 6-bit configuration are used. Reference numerals 201 and 202 are both 16 Mbit SD
RAM. As can be seen from FIG. 2, these two SDs
The same control line and data line are connected to the RAM chips 201 and 202 except for the CS (chip select) line. Here, the 16 bus lines of the SDRAM, that is, the D bus (D [15: 0]), which is a 16-bit data bus, is
16 CPUs, that is, a 16-bit SYSAD bus (S
YSAD [15: 0]).

The two SDRAM chips are constructed so that the same contents can be written simultaneously.

Since the CPU uses the SYSAD bus as an address / data bus, an address requested by the CPU may be driven here. Lee
It is natural that the data and the address are controlled so as not to collide with each other.

The other signal lines shown in FIG. 2 are CLK.
Except for the (clock) signal, this is the signal driven by the control ASIC.

Incidentally, SYSAD is abbreviated as SAD in FIGS. 3 and 4 which will be described later.

Since the SDRAM is given a request as a command, the control signal described above may have a different meaning depending on the combination with other signals. Its main uses are as follows.

RA [11: 0] is used for inputting an address, and RAS, CAS, and WE represent an active command, a read command, a write command, a precharge command, etc. by a combination thereof. Used to LDQM and UDQM are used to mask input / output of lower 8 bits and upper 8 bits, respectively. C
The KE (clock enable signal) is used to invalidate the rising edge of the clock and to control the power down mode of the SDRAM. CS is used to enable / disable command input.

FIG. 3 shows a sequence when the CPU issues the burst read request for 4 words twice.
As shown in FIG. FIG. 3 shows a sequence for reading from an active bank.
Shows the sequence when reading from a bank different from the active bank.

3 and 4, SYSCLK is a system clock used in the entire system, and may be abbreviated as CLK in the present application.
SAD and D are originally the same signal, but for convenience of explanation, only the signal (read data) driven by the SDRAM is shown in D. The SAD is used to transfer read / write addresses and read / write data, and is referred to as the SYSCMD bus (referred to simply as C in the drawings and the following description).
Abbreviated as MD. ) Indicates the type, and the VOUT (valid out) signal indicates whether the contents of SAD and CMD are valid. Also, the CMD bus is not only driven by the CPU, but at the time of a read request,
Indicates whether or not there is an error in the data returned to the CPU, and VIN
Assert (valid-in) signal, SAD and CM
Indicates that the contents of the D signal are valid.

In FIG. 3, SYSCLK1 is used to control the CPU.
Drives the status indicating the read address to SAD and the address of the 4-word read request to CMD,
Assert VOUT to L (low) level.

The control ASIC samples this at the rising edge of SYSCLK2, compares this request address with the address stored in the active address holding means in the control ASIC, and reads from the bank that is active. -Judge that it is not possible to do
Drive the low address that reads from CLK3 to RA, set RAS and CS0 to L (low) level, and assert.
And activate the bank containing the read data.
At this time, the address to be accessed is stored in the active address holding means. The active address holding means is composed of a predetermined register group.

A column address is driven from RA to SYSCLK4, CS0 and CAS are asserted, and a read command is issued. Here, the CAS latency (the number of clocks from the sampling of the read command to the sampling of the first read data) is set to 2 and the burst length is set to 4, so that SYSCLK7 Data can be sampled on 10 rising edges.
This data is directly input to the CPU.

To inform the CPU that there is valid data on the SAD bus, the CMD bus is set to indicate error-free status and VIN is asserted from SYSCLK6.

The CPU returns to SCLK again from SCLK11.
The status indicating that the read address is indicated by AD and the read request address of 4 words is indicated by CMD is driven, and VOUT is asserted at L (low) level.

The control ASIC sends this to SYSCLK12.
Sampling is carried out at the rising edge of, and the request address is compared with the address stored in the active address holding means inside the control ASIC. This time, you can read from the active bank, so
A column address for reading from LK13 to RA is driven, CAS and CS0 are asserted to L (low) level, and a read command is issued. Hereinafter, the same operation as the previous time is repeated. As described above, since the read can be performed from the active bank, the read can be performed without waiting for the time to activate the target bank, and the access time can be shortened.

The timing chart of FIG. 4 is almost the same as the timing chart of FIG. 3, but since the address read by the CPU in SYSCLK11 is not the active bank, the SDRAM on the CS1 side can be used. A read operation is performed and a precharge command is issued to the SDRAM on the CS0 side. That is, SYSCLK15
To CS0, RAS, RWE to L (low) level to issue a precharge command. This is SD
The RAM samples at SYSCLK16 and the bank is inactive. The address to be accessed from now on is stored in the active address holding means in the same manner as described above.

By such an operation, the precharge time can be reduced even if the read request address is in an inactive bank, that is, even if the active bank is another address. Read access can be started without waiting.

[0029]

As described above, according to the present invention,
If a read is possible from the bank that is currently active, the read is performed from that bank, enabling high-speed access.
Since it is not necessary to wait for a message, it is possible to read in the normal access time.

[0030]

[Brief description of drawings]

FIG. 1 is a block diagram of a memory system according to an embodiment. FIG. 2 is a diagram showing details of the SDRAM. FIG.
Is an operation timing chart of the memory system.
FIG. 4 is an operation timing chart of the memory system.

[0031]

[Explanation of symbols]

 101 CPU 102 Control ASIC 103 Low-speed I / O 104 SDRAM 201 SDRAM Chip 202 SDRAM Chip

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Tomoki Ishii 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Co., Ltd.

Claims (1)

[Claims] 1. In a memory system using a plurality of synchronous DRAM chips as storage means, a control line and a data line from a CPU except a chip select line are connected to each chip of the synchronous DRAM. At the same time, it has a holding means for holding the address of the currently effective synchronous DRAM, and a comparing means for comparing the address stored in the holding means with the next request address. A memory system for controlling access to the synchronous DRAM chip according to a comparison result.