JP4606725B2 - High speed memory access controller - Google Patents

Description

  The present invention relates to a high-speed memory access control device that performs access control to a high-speed memory such as an SDRAM used as an external storage device.

  A high-speed RAM such as an SDRAM (Synchronous Dynamic Random Access Memory) has a limitation in a high-speed operation in a conventional asynchronous DRAM, and thus enables a higher-speed operation by using a specification different from that of the DRAM. In general, the SDRAM is connected to the CPU via a controller (control device) because it cannot be directly connected to the CPU because the function of the control signal and the data processing method are different from those of the CPU (processor).

  The SDRAM access control using such a controller is performed as disclosed in Patent Document 1, for example. Specifically, the address input to the SDRAM is divided into a row (row) address and a column (column) address, and by controlling each of them, the final control of the access address to the SDRAM is realized. Yes. Japanese Patent Application Laid-Open No. 2004-228561 discloses control in a case where different pages are successively accessed in the same bank in a plurality of banks constituting the memory.

In general, an SDRAM has a burst mode as an operation mode in which data is continuously input / output in order to efficiently access continuous areas. In the burst mode of the SDRAM, when consecutive accesses of a plurality of words are not completed only on the same page and extend to the next page, the column address used for access exceeds the page. Conventionally, in order to execute access for each page, SDRAM controllers add / subtract the determination of column address page crossing (boundary crossing), address calculation for that, and the number of access words before and after page crossing. I went with a vessel.
JP 2002-24083 A (published on January 25, 2002) JP 2000-172560 A (released on June 23, 2000)

  However, in the controller as described above, if the determination that the column address exceeds the page is made while the SDRAM is being accessed, it is difficult to secure a timing margin for determining the calculation and data within the period of the operation clock. Further, if the adder / subtractor performs operations such as determining whether the page is exceeded or determining the number of access words before and after the page, the larger the bit width of the address, the more time is required for the operation. Not only does it cause inconvenience that it cannot cope with a clock with high operation, but also the scale of the comparison / determination circuit and the arithmetic circuit for address calculation becomes large. By performing pipeline processing, it is possible to cope with an operation clock having a high frequency, but there is a problem that the scale of hardware increases.

  In burst access, when the start address is an odd address, the column address set in the SDRAM has a high-order bit fixed, and the least significant bit toggles from “1” to “0” for burst access. Therefore, memory access occurs in order from the higher address to the lower address. In order to continuously access the memory space for such an operation, the controller needs a data alignment buffer for changing the least significant bit of the column address from “0” to “1”. . For this reason, there is a disadvantage that the time required for burst access is prolonged due to the processing time in the buffer.

  Specifically, as shown in FIG. 4B, the least significant bit of the column address serving as the start address is “1” (or “3”), and the least significant bit of the subsequent column address is “0”. (Or “2”), the operation is as follows. In this case, if the burst length is 1 word, the DQM (data mask) operation is inactive (L level) even if the least significant bit of the start address is “1” (or “3”). Access only the start address. As a result, access as expected expected access is possible, and the reverse of the access order as described above does not occur. However, if the burst length is 2 words, since the least significant bit of the start address is “1” (or “3”), the expected effective access is “1, 2” (or “3,4”). Although it should be performed in order, in practice, by accessing a period of two words during which the DQM operation is inactive (L level), “1, 0” (or “3, 2”) Accesses are made in order, and the access order is reversed as described above. This is the same even when the burst length is 3 words or 4 words, and occurs when the burst length is 2 words or more.

  The present invention has been made in view of the above-described problems, and aims to shorten the processing time in burst access of a high-speed memory such as an SDRAM operating at high speed, and further increase the hardware scale resulting from burst access. It is intended to avoid.

  A first high-speed memory control device according to the present invention is a high-speed memory access control device that controls access of a high-speed memory that performs burst access for continuously inputting and outputting a specified number of words. In order to solve the problem, it is determined that the burst access is an exception access over two consecutive pages based on the number of burst words supplied from the outside and the access start address, and the number of access words for burst access to each page Exception access information determining means for determining the address, and address generating means for generating a start address for starting burst access to the high-speed memory and switching the start address for accessing the next page from the page starting burst access And 2 pages with continuous burst access A switching control means for controlling an address switching timing by the address generating means based on the determined number of bursts, and an exception access determination and burst access word by the exception access information determining means Timing control means for controlling the access timing so as to start the access to the high-speed memory after the number is determined.

  In the high-speed memory access control device, it is preferable that the exception access information determination unit has a table for specifying the number of access words based on a start column address specified from the access start address and the number of burst words. .

  Alternatively, when the high-speed memory access control device determines that the start column address for starting access to a page is an odd number, and an odd number determination means for determining whether the column address is an odd number Address change means for changing the start column address to the previous even number, and the timing control means is configured to enable access only for the number of words of burst access specified from the odd column address. It is preferable to control the timing.

  A second high-speed memory access control device according to the present invention is a high-speed memory access control device that controls access to a high-speed memory that performs burst access for continuously inputting / outputting a specified number of data. In order to solve the above problem, an odd number determination means for determining whether or not a start column address for starting access to a page is an odd number, and the start when the column address is determined to be an odd number Address changing means for changing the column address to the previous even number, and timing control means for controlling the access timing so that only the access of the number of words of the burst access specified from the odd number of the column address is valid. It is characterized by having.

  In the first high-speed memory access control device, the address generating means generates a start address for starting burst access to the high-speed memory. When this start address is given, the high-speed memory increments the internal address one by one by an internal address counter. Further, the exception access information determining means determines that the burst access is an exception access and determines the number of access words for burst access to each page. For example, when a 4-word burst access is requested, if the start address is three before the last address of one page, the access is started for 3 words, and the next page is the remaining 1 Word access will be performed.

  Then, the switching control means controls the switching timing of the start address based on the number of access words. In the address generation means, the start address is switched according to the switching timing. As a result, when a page crossing of the start address occurs, a new start address is issued at the head of the next page following the page where the access is started, thus allowing access beyond the page. Also, since the timing control means starts the access to the high-speed memory after the processing by the exception access information determination means described above, it is avoided to determine the exception access during the high-speed memory access, and as a result The timing margin can be given a margin. Therefore, it is possible to prevent the memory access speed from being lowered without increasing the circuit scale for calculation.

  In addition, since the exception access information determining means has the table, the access word number is specified by the start column address and the burst word number for determining the access start position in each page, so that an arithmetic circuit such as an adder / subtractor can be used. It becomes unnecessary, and the circuit scale of the high-speed memory access control device can be reduced.

  In the second high-speed memory access control device, when the odd number determination means determines that the start address is an odd number, the address change means changes the start column address to the previous even number. Access to the actual high-speed memory is enabled so that only the access for the number of words of the burst access specified from the original odd start column address is valid by the timing control means, not the changed even start column address. Timing is controlled. In this timing control, for example, access is performed in the high-speed memory according to the number of words specified from the even start column address, but in the SDRAM or the like, the above number of words is accessed from the odd start column address. As described above, the data mask enable signal given to the high-speed memory from the high-speed memory access control device is activated.

  As a result, the access is realized in the order from the lower address to the higher address where the least significant bit of the start column address changes from “0” to “1”. Therefore, it is not necessary to provide a buffer for aligning the accessed data, the increase in the circuit scale of the high-speed memory access control device can be prevented, and the processing time for data alignment can be reduced to reduce the memory access. It is possible to prevent a decrease in speed.

  The configuration of the second high-speed memory access control device can also be applied to the first high-speed memory access control device. According to such a configuration, the circuit scale of the high-speed memory access control device is further reduced. In addition, access control can be performed without impairing the high-speed accessibility of a high-speed memory such as an SDRAM.

  One embodiment of the present invention will be described with reference to FIGS. 1 to 4 as follows.

  As shown in FIG. 1, the SDRAM controller 1 of this embodiment is a circuit that controls access to the SDRAM 3 based on various signals from the master circuit 2.

  The master circuit 2 is a circuit for giving an instruction such as a memory request to the SDRAM controller 1 or inputting / outputting data when the peripheral device uses the SDRAM 3. The master circuit 2 is a CPU or a DMA (Direct Memory Access) controller. There may be. Data and various control signals are exchanged between the master circuit 2 and the SDRAM controller 1 and between the SDRAM controller 1 and the SDRAM 3 via a 32-bit width interface. The transfer of addresses and various control signals from the SDRAM controller 1 to the SDRAM 3 is performed via the three-state buffer 4. Data exchange between the SDRAM controller 1 and the SDRAM 3 is performed via the I / O buffer 5.

  The master circuit 2 outputs a 23-bit access start address BMA [24: 2] as a start address when accessing the SDRAM 3. Hereinafter, for [a: b] (a and b are natural numbers) added to the codes of each data and each signal, the most significant bit number (a) and the least significant bit number ( b). Further, the master circuit 2 outputs a burst length signal BRST [1: 0] representing the number of access data when performing burst transfer. In addition, the master circuit 2 outputs a chip select signal SDCS_L, a read signal RD_L, a write signal WR_L, and a data byte enable signal BE_L [3: 0] to the control signal generation circuit 13 and write data to the write control circuit 15. DI [31: 0] is output. Further, master circuit 2 receives data interface signal SDRDY_L output from control signal generation circuit 13 and read data DO [31: 0] output from read control circuit 16.

  The SDRAM 3 is constituted by a plurality of banks (for example, 4 banks), and each bank is a memory composed of memory cells arranged in a matrix of m columns (columns) × n rows (rows) (m and n are natural numbers). Has an array. Each row formed of m memory cells connected to each word line constitutes a page, and the data of the memory cell in each page is accessed by a column address in the row selected by the row address. For example, when there are four banks, the address for designating the bank is given in the lower 2 bits of the address A [14: 0] given from the SDRAM controller 1 to the SDRAM 3 (bank address BA [1: 0]).

  In SDRAM 3, at the rising edge of clock signal CLK supplied from control signal generation circuit 13, row address strobe signal / RAS, column address strobe signal / CAS, and write enable signal (write permission) from control signal generation circuit 13 are also used. Signal) / WE and address [14: 0]. The address A [14: 0] is given by multiplexing a row address and a column address in a time division manner. If the row address strobe signal / RAS is in the active state “L” at the rising edge of the clock signal CLK, the address A [14: 0] at that time is taken in as the row address. Subsequently, if the column address strobe signal / CAS is in the active state “L” at the rising edge of the clock signal CLK, the address A [14: 0] at that time is taken in as the column address. A row and column selection operation is performed in the SDRAM 3 according to the fetched row address and column address.

  In order to function as a high-speed memory access control device, the SDRAM controller 1 has an exception access determination circuit 11, an address generation circuit 12, a control signal generation circuit 13, an address control circuit 14, a write control circuit 15, and a read And a control circuit 16.

  As shown in FIG. 2, the exception access determination circuit 11 also includes the 2-bit burst length signal BRST [1: 0] output from the master circuit 2 and the lower 8 bits [9: 2] of the access start address BMA [24: 2]. ] Is a circuit that determines whether the access to the SDRAM 3 is an exception access or a normal access based on a lower address LA [7: 0]. In the present embodiment, since the number of burst words (one word is 32 bits) can be set to 1, 2, 3, and 4, the burst length signal BRST [1: 0] = 1, 2, 3, and 4.

  Exception access is access performed from the page where data is accessed to the next page in burst access. The exception access determination circuit 11 includes an access burst number determination circuit 111 in order to perform the above determination. The access burst number determination circuit 11 includes an address comparison circuit 111a and an access operation information determination circuit 111b.

  The address comparison circuit 111a uses the lower address LA [7: 0] as the last address of one page of COLA [7: 0] constituting the lower 8 bits of the column address COLA [14: 0] described later. : 0] = 0xFF, COLA [7: 0] = 0xFE, which is one address before the last address, and COLA [7: 0] = 0xFD, which is the address two addresses before the last address, respectively. When LA [7: 0] matches any of the last address, the address one previous to the last address, and the address two previous to the last address, the final address data L1, L2, and L3 are output, respectively. Further, the address comparison circuit 111a outputs non-final address data L4 when the lower address LA [7: 0] does not match any of the above three addresses.

  The access operation information determination circuit 111b decodes the last address data L1 to L3 and the burst length signal BRST [1: 0], thereby determining whether the access to be performed is an exception access or a normal access, The result is output as the exception access determination flag ext_acs being active (exception access = 1) / inactive (normal access = 0). Further, the access operation information determination circuit 111b obtains the start page access data number PRE1 to PRE3, which is the number of access data (the number of access data before crossing the page) at the access start page where the access is started, by the above decoding. While outputting as PREBRST [2: 0], the next page access data number POST1 to POST3, which is the number of access data in the next page of the access start page (the number of access data after crossing the page), is added to the postburst signal POSTBRST [2: 0] is output.

  The burst length signal BRST [1: 0] is expressed as shown in Table 1.

  Specifically, the access operation information determination circuit 111b has an access burst number determination table having the last address data L1 to L3 as rows and the burst length signals BRST [1: 0] as columns as shown in FIG. 3, for example. The preburst signal PREBRST [2: 0] and the postburst signal POSTBRST [2: 0] are output. For example, when the last address data L1 and the burst length signal BRST [1: 0] = 2, the access operation information determination circuit 111b determines that the access is exceptional, and the preburst signal PREBRST [2: 0] = 1 and the postburst The signal POSTBRST [2: 0] = 1 is output. Further, in the case where no access page crossing occurs as in the case of the last address data L1 and the burst length signal BRST [1: 0] = 1, the access operation information determination circuit 111b determines that the access is normal, The preburst signal PREBRST [2: 0] = 0 and the postburst signal POSTBRST [2: 0] = 0 are output.

  On the other hand, when the non-last address data L4 is input, the access operation information determination circuit 111b determines that the access to be performed from now is normal access, and pre-burst signal PREBRST [2: 0] = 0 and post-burst signal POSTBRST [ 2: 0] = 0 is output, and the exception access determination flag ext_acs is deactivated. Further, the access operation information determination circuit 111b outputs the burst length signal BRST [1: 0] as it is when it is determined that the access to be performed is a normal access.

  Note that the access operation information determination circuit 111b does not include the access burst number determination table shown in FIG. 3, but a decoder that decodes data combining the last address data L1 to L3 and the burst length signal BRST [1: 0]. You may have.

  The control signal generation circuit 13 has an exception access control circuit 131. When the above-described active exception access determination flag ext_acs is input to the exception access control circuit 131, the number of access words on the access start page determined by the preburst signal PREBRST [2: 0] and the postburst signal POSTBRST [2: The address selection signal ADSEL is switched from “0” to “1” at the timing of switching the access to the next page in accordance with the number of access words on the next page determined by [0]. The exception access control circuit 131 outputs the address selection signal ADSEL of “0” when the inactive exception access determination flag ext_acs is input.

  The exception access control circuit 131 determines the address in the address generation circuit 12 based on the address selection signal ADSEL before the start of the access operation to the SDRAM 3, that is, before the output of various control signals for access. In addition, the output timing of the address selection signal ADSEL is managed by a timing counter. For example, at the time of exception access, when an access page crossing occurs, the address selection signal ADSEL is output at a timing at which the address generation circuit 12 can output a later-described start row address ROWA [14: 0].

  Other functions of the control signal generation circuit 13 will be described in detail later.

  The address generation circuit 12 is a circuit that generates a start row address ROWA [14: 0] and a start column address [14: 0] based on the access start address BMA [24: 2]. A multiplexer (MUX in the figure) 121 and 122 and an adder 123. In the start column address COLA [14: 0], the lower 8 bit COLA [7: 0] is composed of BMA [9: 2] of the access start address BMA [24: 2], and the upper 7 bit COLA [14: 8] is composed of 0 data. .

  The multiplexer 121 receives the lower address LA [7: 0] composed of the lower 8-bit BMA [9: 2] of the access start address BMA [24: 2] and the 8-bit 0 data “0x00”. The multiplexer 121 outputs 0 data “0x00” when the address selection signal ADSEL is “1” (during exceptional access), and the lower address when the address selection signal ADSEL is “0” (during normal access). This is a selection circuit that outputs [7: 0].

  The adder 123 is a circuit that adds 1 to the upper address UA [14: 0] including the upper 15 bits BMA [24:10] of the access start address BMA [24: 2]. The multiplexer 122 outputs the upper address UA [14: 0] from the adder 123 when the address selection signal ADSEL is “1”, and directly from the master circuit 2 when the address selection signal ADSEL is “0”. This is a selection circuit that outputs the input lower address LA [7: 0].

  The address generation circuit 12 latches after the adder 123 so that the upper address UA [14: 0] from the adder 123 can be output at the timing when the address selection signal ADSEL changes from “0” to “1”. have.

  The control signal generation circuit 13 outputs a clock signal CLK as a system clock supplied from the outside to the SDRAM 3 and uses it as an operation clock for each part in the circuit. The control signal generation circuit 13 also includes the row address strobe signal / RAS, the column address strobe signal / CAS, the write enable signal / WE, the chip select signal / CS, the clock enable signal CKE, and the data mask enable signal supplied to the SDRAM 3. In addition to DQM [3: 0], an output enable signal SDCOE_L for controlling validity / invalidity of the output of the 3-state buffer 4 and an output enable signal DQOE_L for controlling validity / invalidity of the output of the I / O buffer 5 are provided. Are generated based on a chip select signal SDCS_L, a read signal RD_L, a write signal WR_L, and a data byte enable signal BE_L [3: 0] supplied from the master circuit 2. The control signal generation circuit 13 generates a write timing given to the write control circuit 15 and a read timing given to the read control circuit 16. The control signal generation circuit 13 controls access so that burst access is performed in units of 2 words. On the other hand, the internal address counter of the SDRAM 3 increments the address by two from the start column address every time two words are accessed.

  In addition to the exception access control circuit 131, the control signal generation circuit 13 includes a start address determination circuit 132, a basic burst access timing defining circuit 133, and an irregular burst timing defining circuit 134.

  The start address determination circuit 132 is a circuit that determines whether the start column address [14: 0] is an even number or an odd number based on the lower address LA [7: 0] output from the master circuit 2. This determination is performed by, for example, a comparator that determines whether the value of the least significant bit of the lower address LA [7: 0] is “1”, but may be performed by other methods.

  The basic burst access timing defining circuit 133 generates a control command for the SDRAM 3 for normal access (normal burst access) when the start address determination circuit 132 determines that the start column address [14: 0] is an even number. It is a circuit that defines the timing to perform. The basic burst access timing defining circuit 133 includes a row address strobe signal / RAS, a column address strobe signal / CAS, a write enable signal / WE, a chip select signal / CS, a clock enable signal CKE, and a data mask enable signal DQM [3: 0. ] Has a command table that defines control commands determined by combinations of logical states such as The basic burst access timing defining circuit 133 is requested by the burst length signal BRST [1: 0], the preburst signal PREBRST [2: 0] and the post burst signal POSTBRST [2: 0] from the exception access determination circuit 11. In order to perform normal access for the number of bursts to be transmitted, each signal / RAS, / CAS, / WE, / CS, CKE from the above table after a predetermined time after the address selection signal ADSEL from the exception access control circuit 131 is determined. , DQM, etc., and instructs the address control circuit 14 to output an address.

  When the start address determination circuit 132 determines that the start column address [14: 0] is an odd number, the irregular burst access timing defining circuit 134 issues a control command for the SDRAM 3 for irregular access (irregular burst access). It is a circuit that defines the timing of occurrence. The irregular burst access timing defining circuit 134 includes a command table defining control commands similar to those of the basic burst access timing defining circuit 133. The irregular burst access timing defining circuit 134 is requested by the burst length signal BRST [1: 0], the preburst signal PREBRST [2: 0] and the postburst signal POSTBRST [2: 0] from the exception access determination circuit 11. In order to perform an irregular access of the number of bursts, the above-mentioned signals / RAS, / CAS, / WE, / CS, CKE, DQM after a predetermined time after the address selection signal ADSEL from the exception access control circuit 131 is determined. And the address are output to the address control circuit 14.

The irregular burst access timing defining circuit 134 is different from the basic burst access timing defining circuit 133 in the following two points (1) and (2).
(1) When the address control circuit 14 is instructed to output an address, the start column address [14: 0] is also instructed to be changed from the odd number to the previous even number.
(2) The data mask enable signal DQM [3: 0] does not mask access to the data of the specified access word number after the data of the originally specified odd start column address [14: 0]. The command table is set so as to mask access for column addresses including start column address [14: 0] changed from odd number to even number other than.

  The address control circuit 14 is loaded with the start row address ROWA [14: 0] and the start column address COLA [14: 0] generated by the address generation circuit 12, and the basic burst access timing defining circuit 133 or the irregular burst access timing. Based on the address output instruction of the defining circuit 134, it outputs in synchronization with the output of each of the above signals / RAS, / CAS, / WE, / CS, CKE, DQM and the like. Further, the address control circuit 14 decrements and outputs one odd start column address [14: 0] based on the address change instruction from the irregular burst access timing defining circuit 134.

  Next, an access control operation of the SDRAM 3 by the SDRAM controller 1 configured as described above will be described. First, the operation in exception access will be described, and then the operation in irregular access will be described.

  When the access start address BMA [24: 2] is output from the master circuit 2, the access to be performed is a normal access or an exception access based on the lower address LA [7: 0] by the access burst number determination circuit 111. Whether or not there is a pre-burst signal PREBRST [2: 0] and a post-burst signal POSTBRST [2: 0] is determined. If it is determined that the access is normal, the inactive exception access determination flag ext_acs, the invalidated preburst signal PREBRST [2: 0] = 0 and the postburst signal POSTBRST [ 2: 0] = 0 is output. On the other hand, when it is determined that the access is exceptional, the access burst number determination circuit 111 sends the active exception access determination flag ext_acs, the valid preburst signal PREBRST [2: 0], and the postburst signal POSTBRST [2: 0]. Are output.

When the inactive exception access determination flag ext_acs is input, the exception access control circuit 131 of the control signal generation circuit 13 determines normal access and outputs an address selection signal ADSEL of “0”. At this time, in the address generation circuit 12, the lower address LA [7: 0] (lower bitCOLA [7: 0]) and the upper 7bitCOLA [14: 8] output from the multiplexer 121 when it is determined as normal access. Thus, the start column address COLA [14: 0] is determined, and the start row address ROWA [14: 0] is determined by the upper address UA [14: 0] output from the multiplexer 122.

The exception access control circuit 13 1, an exception access determination flag ext_acs active is input, the address selection signal ADSEL at a timing of switching the access from the start page to the next page switch to "1" to "0". At this time, lower bitCOLA [7: 0] = “0x00” is output from the multiplexer 121, and the start row address ROWA [14: 0] obtained by adding 1 by the adder 123 is output from the multiplexer 122. . In this way, by updating the start row address ROWA [14: 0] and the start column address COLA [14: 0], it becomes possible to access the first column in the next page.

  For example, when the access start address BMA [24: 2] is “0x0000FE”, the lower bitCOLA [7: 0] is “0xFE”, which is an even number. When the number of burst access words required by the master circuit 2 is 4, as shown in Table 1, the burst length signal BRST [1: 0] expressed as “11” in binary notation is used as the address control circuit. 14 to the SDRAM 3 through the three-state buffer 4. Therefore, in this case, it is necessary to access 4 words at an address determined by “0x0000FF”, “0x000100”, and “0x000101” from the access start address BMA [24: 2] = “0x0000FE”.

  At this time, PREBRST [2: 0] = 2 and POSTBRST [2: 0] = 2 are output from the access burst number determination table shown in FIG. 3 by the access operation information determination circuit 111b, and the exception access determination flag ext_acs. = 1 is output. The start address determination circuit 132 determines that the start column address COLA [14: 0] is an even number. Therefore, the start row address ROWA [14: 0] is determined at the timing specified by the basic burst access timing specification circuit 133. ] And the start column address COLA [14: 0] are output from the address control circuit 14 and various control signals are output from the control signal generation circuit 13.

  As a result, in the SDRAM 3, two words are accessed from the column specified by the start column address COLA [14: 0] in the access start page specified by the start row address ROWA [14: 0], and the first page in the next page is accessed. The remaining two words are accessed from the column. At the time of accessing 4 words, the data mask enable signal DQM [3: 0] becomes “0” and the access is not masked. As described above, when page crossing occurs, two accesses (issue of two start column addresses COLA [14: 0]) are executed over two pages.

  On the other hand, when page crossing does not occur, if the normal address is determined as described above, the values of the preburst signal PREBRST [2: 0] and the postburst signal POSTBRST [2: 0] are invalid (= 0). Become. Accordingly, from the column specified by the start column address COLA [14: 0] in the access start page specified by the start row address ROWA [14: 0], the number specified by the burst length signal BRST [1: 0] A word is accessed. As described above, when page crossing does not occur, only one access is executed on one page.

  When the start column address COLA [14: 0] is an even number, as shown in FIG. 4A, the least significant bit of the column address as the start address is “0” (or “2”). When the least significant bit of the subsequent column address is “1” (or “3”), the following operation is performed. In this case, if the burst length is 1 word, the DQM (data mask) operation is inactive (L level) even if the least significant bit of the start address is “0” (or “2”). Access only the start address. As a result, access as expected expected access is possible, and the reverse of the access order as described above does not occur. If the burst length is 2 words, the least significant bit of the start address is “0” (or “2”), so that the expected effective access is “0, 1” (or “2, 3”. ), And in practice, “0, 1” (or “2, 3”) is obtained by accessing a period of two words during which the DQM operation is inactive (“L”). Access is performed in the order of. This is the same even when the burst length is 3 words or 4 words, and the least significant bit of the column address as the start address increases, and access is normally performed.

  By the way, when the start column address COLA [14: 0] is an odd number, an irregular burst access sequence is executed for access of the start page in normal access and exception access. As for the next page access in the exception access, since the access is performed from the top column (column address = 0) of the page, the irregular burst access sequence is not executed.

  For example, when the access start address BMA [24: 2] is “0x0000FD”, the lower bitCOLA [7: 0] is “0xFD”, which is an odd number. When the number of burst access words required by the master circuit 2 is 4, as shown in Table 1, the burst length signal BRST [1: 0] expressed as “11” in binary notation is used as the address control circuit. 14 to the SDRAM 3 through the three-state buffer 4. Therefore, in this case, it is necessary to access 4 words at an address determined by “0x0000FE”, “0x0000FF”, and “0x000100” from the access start address BMA [24: 2] = “0x0000FD”.

  At this time, PREBRST [2: 0] = 3 and POSTBRST [2: 0] = 1 are output from the access burst number determination table shown in FIG. 3 by the access operation information determination circuit 111b, and the exception access determination flag ext_acs. = 1 is output. In addition, since the start column address COLA [14: 0] is determined to be an odd number by the start address determination circuit 132, the start row address ROWA [14: 0] is determined at the timing specified by the irregular burst access timing specification circuit 134. ] And the start column address COLA [14: 0] changed to the previous even number are output from the address control circuit 14 and various control signals are output from the control signal generation circuit 13.

  At this time, in the SDRAM 3, 3 words are accessed from the column (access start address BMA [24: 2] = “0x0000FC”) specified in the access start page specified by the even start row address ROWA [14: 0]. The remaining one word is accessed from the first column in the next page. In addition, the access of the number of 4 words designated from the original odd start column address COLA [14: 0] is not masked because the data mask enable signal DQM [3: 0] is “L”, but other than that, Access at the column address is masked by the data mask enable signal DQM [3: 0] being “H”.

  When an irregular access is performed, as shown in FIG. 4C, the start column address COLA [14: 0] is changed from an odd number to an even number one before, so that the least significant bit of the column address serving as the start address is “0” (or “2”), and the least significant bit of the subsequent column address is “1” (or “3”). In this case, if the burst length is 1 word, the DQM operation becomes inactive and invalid even if the least significant bit of the start address is “0” (or “2”). Access is enabled during the period in which the DQM operation is active at the next least significant bit “1” (or “3”) as an address. At this time, as specified by the irregular burst access timing defining circuit 134, the SDRAM 3 is instructed to access 2 burst lengths. As described above, 1 of the odd start column address COLA [14: 0] Burst access is executed only for words.

  In one-word burst access, as shown in FIG. 4B, even if the start column address COLA [14: 0] is an odd number, it can be accessed without any problem. Access is performed according to the specified irregular burst access timing.

  Similarly, if the burst length is 2 words, it can be accessed by the DQM operation in which 2 words are activated from the next odd address, but access to the address including the start address converted to an even number other than that is possible. , The DQM operation becomes inactive and becomes invalid. At this time, since the access is controlled in units of 2 bursts by the control signal generation circuit 13, when burst access of 2 words is requested, access of 4 burst lengths is performed in the SDRAM 3, and the odd address From the odd start column address COLA [14: 0] by the DQM operation in which two words are active ("L") from the first, burst access of only two words such as "1, 2" (or "2, 3") Is executed.

  Also, when the burst length is 3 words, as in the case of 2-word access, access of 4 burst lengths is performed, but “1, 2, 3” (or by the DQM operation in which 3 words from the odd address become active. "2, 3, 4"). Further, when the burst length is 4 words, an access of 6 burst lengths is performed, but “1, 2, 3, 4” (or “2, 3, 4” is performed by the DQM operation in which 4 words are activated from the odd address. , 5 ").

  As described above, the SDRAM controller 1 according to the present embodiment has the column address page in which the burst access spans two pages before the memory access sequence is started according to the timing defined by the irregular burst access timing defining circuit 134. In the case where an overshoot occurs, the access burst number determination circuit 111 of the exception access determination circuit 11 determines that an exception access requires a page crossing, and also exceeds the page based on the burst length information by the burst length signal BRST [1: 0]. The number of access bursts before and after the page is specified by the values of the pre-burst signal PREBRST [2: 0] and the post-burst signal POSTBRST [2: 0]. As a result, it is possible to avoid the determination of page crossing during access to the SDRAM 3, so that a timing margin can be given to the clock signal CLK. Therefore, it is possible to prevent a decrease in memory access speed without increasing the size of hardware for computation.

  Also, the SDRAM controller 1 of the present embodiment is started by the start address determination circuit 132 until the memory access sequence is started according to the timing specified by the basic burst access timing specifying circuit 133 or the irregular burst access timing specifying circuit 134. When it is determined that the column address COLA [14: 0] is an odd number, the start column address COLA [14: 0] is changed to the previous even number, and the odd start column address COLA [14: 0] is changed. The timing at which the data max enable signal DQM [3: 0] is activated is controlled so as to enable the access. As a result, access is realized in the order from the lower address to the higher address where the least significant bit of the start column address COLA [14: 0] changes from “0” to “1”. Therefore, in the SDRAM controller 1, it is not necessary to provide a buffer for data alignment, the increase in hardware scale can be prevented, and the processing time for data alignment is reduced to reduce the memory access speed. Can be prevented.

  In the above description, the case where the high-speed memory is the SDRAM 3 has been described. However, if the high-speed memory is a memory that can be burst-accessed and can access data over two adjacent pages during the burst access, the SDRAM 3 It is not limited to. For example, the high-speed memory may be an R (Rambus®) DRAM or an SDRAM (Synchronous Graphics RAM) SGRAM specialized for storing image data. The SDRAM is also used for controlling these RAMs. By controlling access by a control device equivalent to the controller 1, substantially the same effect as in the present embodiment can be obtained.

  In this embodiment, the burst length is set to 4 words at the maximum. However, the present invention is not limited to this, and the maximum burst length may be set to 8 words, for example.

  The high-speed memory access control apparatus according to the present invention can secure a timing margin and perform page crossing over by performing arithmetic processing for determining burst access over two pages before the memory access sequence. It is possible to reduce the hardware scale by reducing the arithmetic circuit for performing the determination in the memory access sequence. Also, the odd start column address is changed to an even number, and burst access is performed from the original odd start column address. By controlling the access timing to be performed, a data alignment buffer is not required, and the processing time for that purpose can be reduced. Therefore, it can be applied to access control of a high-speed memory such as an SDRAM.

1 is a block diagram showing a configuration of an SDRAM control system including an SDRAM controller according to an embodiment of the present invention. It is a block diagram which shows the structure of the principal part of the said SDRAM controller. It is a figure which shows the access burst number determination table provided in the address burst number determination circuit of the exception access determination circuit in the SDRAM controller. (A) to (c) are address operations and data mask operations in the SDRAM when the start column address is an even number, the start column address is an odd number, and the start column address is changed from an odd number to an even number. FIG.

Explanation of symbols

1 SDRAM controller (high-speed memory access controller)
2 Master circuit 3 SDRAM (High-speed memory)
11 Exception access determination circuit (exception access information determination means)
12 Address generation circuit (address generation means)
13 control signal generation circuit 14 address control circuit (address changing means)
111 Address burst number judgment circuit 131 Exception access control circuit (switching control means)
132 Start address determination circuit (odd number determination means)
133 Basic burst access timing specifying circuit (timing control means)
134 Anomalous burst access timing specifying circuit (timing control means)

Claims (2)

A high-speed memory access control device that controls access to a high-speed memory that performs burst access to continuously input and output a specified number of data,
Odd number determination means for determining whether or not the start column address for starting access to the page is an odd number;
Address changing means for changing the start column address to the previous even number when it is determined that the column address is an odd number;
A high-speed memory access control device, comprising: timing control means for controlling access timing so that only the access of the number of words of burst access designated from the odd column address is valid. The timing control means does not mask access of the designated number of words after the start column address determined as odd by the odd number determination means, while the other start column address changed from odd to even 2. The high-speed memory access control apparatus according to claim 1, wherein an access to a column address including the address is masked.