JP4529474B2 - Memory device provided with SDRAM - Google Patents

Description

The present invention relates to a memory device including an SDRAM, and more particularly, to a memory device including an SDRAM (Synchronous DRAM) having a burst access function and dynamically controlling the number of burst access accesses .

The information processing system in the prior art is composed of a CPU (Central Processing Unit) that performs various operations for controlling the operation of the entire system, an SDRAM that is a memory for storing data, and an interface unit for input and output. Yes.
The SDRAM used as a memory is a DRAM (Dynamic Random Access Memory) that operates in synchronization with a clock signal, operates under the control of a command, and allows burst access, and the burst length can be set. It is. Therefore, the SDRAM can be accessed at higher speed than other types of DRAM.
Here, burst access means that continuous input / output of data in the read cycle or write cycle can be controlled, and the burst length is the number of data words in burst access.

The CPU and SDRAM cannot be directly connected because their control signal functions and processing methods are different from each other.
Therefore, as shown in FIG. 4, in order to use the SDRAM 114, a memory control device 113 with a bus 112 for controlling access from the CPU 111 to the system memory 122 of the SDRAM 114 is required. The CPU 111 accesses the system memory 122 via the memory control device 113.

  The memory control device 113 controls the system memory 122 of the SDRAM 114 by outputting an address signal, various control signals, and a clock signal to the SDRAM 114 based on a command from the CPU 111.

  This control signal includes a chip select signal (CS signal), a clock enable signal (CKE signal), a row address strobe signal (RAS signal), a column address strobe signal (CAS signal), a write enable signal (WE signal), and the like. It is.

  As shown in FIG. 4, the SDRAM 114 includes a memory control unit 115 that controls a memory and a system memory 122 including banks A to D.

  As shown in FIG. 4, the memory control unit 115 includes a command decoder 116 that decodes a command by synchronizing a control signal with a clock signal, a mode register 117 that is set at initialization and fixes a burst operation, and a command decoder 116. The control logic 118 for performing burst access stored in the mode register 117, the burst counter 119 for counting burst access based on the burst length, and the lower column address of burst access from the burst counter 119 are stored in the mode register 117. A column address 120 to be executed and a row address 121 for storing an upper address from an address signal are roughly constituted.

The system memory 122 operates in synchronization with the rising edge of the clock signal. The CS signal is a signal for designating the SDRAM 114 to be accessed, the CKE signal is a signal for designating whether or not to operate the SDRAM 114 at the rising edge of the clock signal, and the RAS signal, CAS signal, and WE signal are , A signal for designating access contents (read / write / precharge, etc.) to the SDRAM 114.
The system memory 122 is classified into four banks A to D in the address space. The burst lengths of the banks A to D are set by a mode register command that sets the contents of the mode register 117 during the initialization process.
As shown in FIG. 2, the mode register 117 is a register for storing setting contents related to the operation method of the SDRAM 114 (in addition to the burst length, the order of incrementing address values (sequential / interleave) at the time of burst access).
The mode register command sets the contents of the mode register based on the logical value of a predetermined bit of the address signal at that time if each control signal input to the SDRAM 114 is a predetermined logical value at the rising edge of the clock signal.

In setting the mode register 117 by this mode register command, the burst length is set by the lower 3 bits 0, 1, and 2 of the address as shown in FIG.
This burst length is set according to the size of data when the CPU 111 accesses the SDRAM 114 via the memory control device 113. For example, assuming that the CPU 111 accesses in units of 32 bytes and the data width between the memory controller 113 and the system memory 122 is 64 bits (8 bytes), the burst length of each bank of the system memory 122 is 4 ( 32 bytes / 8).

  Depending on the burst length set in the mode register 117, the control logic 118 gives a count-up signal to the burst counter 119 to count up the lower column address. The burst length is fixed, and the size of the data to be accessed When (in the embodiment, 4 bursts) exceeds this burst length, the SDRAM 114 interrupts the transfer when transferring 4 bursts (32 bytes) of data, or accesses the system memory 122 with a burst length of 4 Must be performed multiple times.

Japanese Patent Laid-Open No. 2002-175215 (pages 2 to 3 and FIG. 1)

However, in the SDRAM described in the prior art, the control logic gives a count-up signal to the burst counter according to the burst length set in the mode register and counts up the lower column address, and the burst length is fixed. The number of cycles is also fixed, and it is necessary to write a burst strap command when writing to the mode register at the time of initialization for both read / write and interrupting burst access in the middle.
Either the read / write cycle has the same number of burst cycles, or the read cycle has multiple cycles and the write cycle is a single cycle burst cycle. If other data access is required, the burst length When data for the specified burst is transferred, it is necessary to interrupt the transfer, or to access the set burst length multiple times, which reduces the data transfer efficiency and speeds up the processing in the system. There is a problem of obstructing.

Accordingly, there is a problem that must be solved by improving the access efficiency by allowing the burst access number based on the set burst length to be dynamically changed while leaving the burst length set in the mode register as it is. .

In order to solve the above problems, a memory device including an SDRAM according to the present invention has the following configuration.
(1) A memory device including an SDRAM is a memory device that controls an SDRAM that performs burst access based on the burst length in a burst cycle including a read / write cycle based on the burst length. In the initialization to be set, the number of burst cycles is set in the burst number counter, and the burst cycle is performed the number of times set in the burst number counter.
(2) The memory device including the SDRAM according to (1), wherein the burst number counter is provided in a mode register.

The memory device including the SDRAM of the present invention has a feature that the access efficiency can be improved by dynamically changing the number of burst accesses by setting the number of burst accesses in the mode register .
In addition, since the number of burst accesses is specified at the beginning of the cycle, access to the required system memory can be preempted. This is because burst access is canceled in accordance with the actual transfer cycle as in the conventional memory. There is no need to specify, and there is an effect that the efficiency of access can be further increased.

  Hereinafter, a memory device including the SDRAM of the present invention will be described in detail with reference to the drawings.

The memory device including the SDRAM of the present invention can perform desired burst access a plurality of times by performing burst access based on the burst length set at the initialization for the number of times set in the counter. It can be set at the time of initialization, and burst access can be interrupted or burst access can be performed multiple times at the beginning, so that the efficiency of access to the system memory can be increased accordingly. Has characteristics.

The memory device provided with the SDRAM has a configuration using the SDRAM as described in the prior art, and has a CPU (Central Processing Unit) for performing various operations for controlling the operation of the entire system, and a data SDRAM, which is a memory for storing data, and an interface unit for input / output.
The SDRAM used as a memory is a DRAM (Dynamic Random Access Memory) that operates in synchronization with a clock signal, operates under the control of a command, and allows burst access, and the burst length can be set. It is.
By having the function of performing burst access based on the burst length, the SDRAM has another type of D
It is possible to access faster than RAM.
Burst access is the ability to control continuous input / output of data in a read cycle or write cycle, and the burst length is the number of words of data in burst access.

Here, the CPU and the SDRAM cannot be directly connected since the functions and processing methods of the control signals are different from each other.
Therefore, as shown in FIG. 1, in order to use the SDRAM 14 as a memory, a memory control device 13 for controlling access from the CPU 11 to the SDRAM 14 via the bus 12 is required. The CPU 11 accesses the SDRAM 14 via the memory control device 13. In addition, although it is CPU in an Example, it is not limited to this, For example, a controller may be sufficient.

  The memory control device 13 controls the system memory 22 of the SDRAM 14 by outputting an address signal, various control signals, and a clock signal to the SDRAM 14 side based on a command from the CPU 11.

  The control signal includes a chip select signal (CS signal) for designating the SDRAM 14 to be accessed, a clock enable signal (CKE signal) for designating whether to operate the SDRAM 14 at the rising edge of the clock signal, and access to the SDRAM 14 Includes a row address strobe signal (RAS signal) for specifying the contents, a column address strobe signal (CAS signal) for specifying the contents of access to the SDRAM 14, a write enable signal (WE signal) for specifying the contents of access to the SDRAM 14, etc. It is.

  As shown in FIG. 1, the SDRAM 14 includes a memory control unit 15 that controls a memory and a system memory 22 including banks A to D.

  As shown in FIG. 1, the memory control unit 15 includes a command decoder 16 that decodes a command by synchronizing a control signal with a clock signal, a burst decoder that is set at initialization, fixes a burst operation, and performs burst access based on a burst length. A mode register 17 having a burst number counter 23 for setting the number of times, a control logic 18 for performing burst access stored in the mode register 17 based on a command in the command decoder 16, and a burst access based on the burst length Is substantially composed of a burst counter 19 that counts the column address, a column address 20 that performs the lower column address of the burst access from the burst counter 19, and a row address 21 that stores the upper address from the address signal.

The system memory 22 is classified into four banks A to D in the address space. The burst lengths of the banks A to D are set by a mode register command that sets the contents of the mode register 17 during the initialization process.
As shown in FIGS. 1 and 2 , the mode register 17 is a register that stores setting contents related to the operation method of the SDRAM 14 (in addition to the burst length, the order of incrementing address values (sequential / interleave) at the time of burst access, etc.). .
This mode register command sets the contents of the mode register based on the logical value of a predetermined bit of the address signal at that time if each control signal input to the SDRAM 14 is a predetermined logical value at the rising edge of the clock signal.

In the setting in the mode register 17 by this mode register command, the burst length is set by the lower 3 bits 0, 1 and 2 of the address as shown in FIG.
This burst length is set according to the size of data when the CPU 11 accesses the memory control device 13. For example, assuming that the CPU 11 accesses in units of 32 bytes and the data width between the memory control device 13 and the SDRAM 14 is 64 bits (8 bytes), the burst length of each bank of the system memory 22 is 4 (32 bytes). / 8).
In the embodiment, a constant value is set in the burst number counter 23 using unused bits, for example, bits 10 to 13.

  According to the burst length set in the mode register 17, the control logic 18 gives a count-up signal to the burst counter 19 and counts up the lower column address. The burst length is fixed and set. The burst length data transfer is accessed the number of times set in the burst number counter 23.

  With reference to the block diagram of FIG. 1, the burst access in the memory device including the SDRAM having the above configuration will be described based on the flowchart shown in FIG.

First, it is determined whether it is a mode register command (step ST11).
If it is a mode register command, the required number of cycles is loaded into the burst number counter 23 of the mode register 17 using an address or a dedicated pin, and the burst length is loaded into the burst counter 19 for generating the lower column address. (Step ST12).

  Next, in each cycle in burst access, for example, burst read single write, the burst number counter 23 is loaded into the burst number counter 23 to count down the burst number counter and perform a burst cycle based on a predetermined burst length. Only the count value is performed (step ST13).

  Then, when the burst end signal is received from the burst number counter 23, the control logic 18 ends the burst access. Is continued (step ST14).

  In this way, desired burst access can be realized by dynamically changing and setting necessary burst access to initialization of access, such as interruption in the middle, setting of multiple burst access again, etc. Therefore, it is possible to improve the efficiency of access to the system memory.

  With respect to burst access set at the initial stage of access, a memory device including an SDRAM capable of realizing desired burst access by setting the number of times of burst access at that time can be provided.

1 is a block diagram of a memory device including an SDRAM of the present invention. It is explanatory drawing which showed the content set to the mode register by a mode register command. 3 is a flowchart for performing burst access. It is a block diagram of the memory device provided with SDRAM in the prior art.

Explanation of symbols

11 CPU
12 bus 13 memory control device 14 SDRAM
15 Memory Control Unit 16 Command Decoder 17 Mode Register 18 Control Logic 19 Burst Counter 20 Column Address 21 Row Address 22 System Memory 23 Burst Number Counter

Claims (2)

A memory device for controlling an SDRAM that performs burst access a number of times based on the burst length in a burst cycle consisting of a read / write cycle based on the burst length ,
During initialization of setting the burst length, the number of the burst cycle is set to the burst counter, equipped with SDRAM, characterized in that said burst cycle has to perform a set number of times in the burst counter Memory device.   2. The memory device having an SDRAM according to claim 1, wherein the burst number counter is provided in a mode register.

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