JP2007018161A - Memory controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory controller capable of reducing the number of terminals connected to an external synchronous type memory part. <P>SOLUTION: When a system clock signal SYSCLK is at a level of "L", a selector 19 selects output signals /CS#1, BA#1[1:0], A#1[13:0], /RAS#1, /CAS#1, and /WE#1 of a memory controller 17. When the system clock signal SYSCLK is at a level of "H", the selector 19 selects output signals /CS#2, BA#2[1:0], A#2[13:0], /RAS#2, /CAS#2, and /WE#2 of a memory controller 18. The selected signals are given to DDR-SDRAM parts 2, 3 as a common control signal via a common terminal group 22. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a memory control device, and in particular, includes first and second synchronous memory units for inputting and outputting data signals in response to both a first level change and a second level change of a clock signal. The present invention relates to a memory control device that controls independently.

  When an application that processes a large amount of data such as image data is executed, a memory that can input and output data at high speed is required. As a memory capable of high-speed operation, an SDRAM (Synchronous Dynamic Random Access Memory) that operates in synchronization with a clock signal having a fixed period is used. There are two types of SDRAM: SDR (Single Data Rate) -SDRAM that exchanges data once per clock cycle and DDR (Double Data Rate) -SDRAM that exchanges data twice per clock cycle. The DDR-SDRAM allows data to be input / output at both the rising edge (first level change) and the falling edge (second level change) of the clock signal, which is twice that of the SDR-SDRAM. The transfer speed is realized. The access timing of the DDR-SDRAM is described in detail in the standard “JEDEC standard JESD79D” defined by JEDEC (Joint Electron Device Engineering Council).

  When it is necessary to connect a plurality of external SDRAMs to a memory control device formed as an LSI (Large Scale Integrated Circuit) and control each SDRAM independently, a plurality of memory controllers corresponding to each SDRAM are provided. Provided inside. In such a case, there is a problem that the number of terminals for connecting the memory control device and the external SDRAM increases.

  For example, the following Patent Document 1 discloses a memory controller having a small number of external terminals even though memories controlled by different access procedures can be controlled. According to this, an address decoder for determining which controller unit controls an address signal from the access source and an access of each controller unit based on the instruction of the address decoder. There is provided a multiplexer that selects a controller unit that controls a target memory and connects to a shared external terminal.

Patent Document 2 below discloses a memory control device that can easily cope with a change in the capacity of an SDRAM element and does not require a change in a memory side interface control circuit. According to this, an identification control signal for identifying whether the address line is an SDRAM column signal or a row signal, and an address line used for the column signal and an address line used for the row signal based on the identification control signal Selection setting means for selectively setting the address lines to be set is provided.
Japanese Patent Laying-Open No. 2005-85216 JP 2001-22635 A

  As described above, when a plurality of external SDRAMs are connected to a memory control device incorporating a plurality of memory controllers and controlled independently, the number of terminals connecting the memory control device and the external SDRAM There was a problem of increasing. In order to reduce the area and cost of the memory control device, it is desired to reduce the number of terminals.

  Therefore, a main object of the present invention is to provide a memory control device capable of reducing the number of terminals connected to an external synchronous memory unit.

  The memory control device according to the present invention has independent first and second synchronous memory units for inputting / outputting data signals in response to both the first level change and the second level change of the clock signal. A memory control device for controlling, operating in synchronization with a system clock signal having a fixed period, and changing in response to a first clock signal having the same phase as the system clock signal and a first level change of the system clock signal And a first memory controller that exchanges data signals with the first synchronous memory unit and operates in synchronization with an inverted signal of the system clock signal, and inverts the system clock signal. A second clock signal having the same phase as the signal, and a second control signal that changes in response to a first level change of the inverted signal of the system clock signal; Receiving a first memory signal and a second memory controller for exchanging data signals with the synchronous memory portion, and selecting the first control signal when the system clock signal is at the first logic level. And a selector that selects the second control signal when the system clock signal is at the second logic level and outputs the selected signal to the first and second synchronous memory units.

  Preferably, each of the first and second control signals includes at least one of a chip select signal, a bank address signal, an address signal, a row address strobe signal, a column address strobe signal, and a write enable signal.

  Preferably, the memory control device is formed as an integrated circuit on the same semiconductor chip.

  The memory control device according to the present invention operates in synchronization with a system clock signal having a fixed period, and changes in response to a first clock signal having the same phase as the system clock signal and a first level change of the system clock signal. And a first memory controller that exchanges data signals with the first synchronous memory unit and operates in synchronization with an inverted signal of the system clock signal, and inverts the system clock signal. A second clock signal having the same phase as the signal and a second control signal that changes in response to a first level change of the inverted signal of the system clock signal, and a second synchronous memory unit and a data signal When the system clock signal is at the first logic level, the first control signal is received when the first and second control signals are received from the second memory controller for exchanging data. Select the system clock signal when the second logic level to select the second control signal, and a selector is provided for outputting the selected signal to first and second synchronous memory section. Therefore, the first and second synchronous memory units can share the common terminal group that receives the output signal of the selector without adversely affecting the control of the synchronous memory unit by the first and second memory controllers. it can. As a result, the number of terminals connected to the first and second synchronous memory units can be reduced.

  FIG. 1 is a block diagram showing a schematic configuration of a memory control device incorporating a plurality of memory controllers according to an embodiment of the present invention. In FIG. 1, the memory control device 1 is connected to an external DDR-SDRAM unit 2 and a DDR-SDRAM unit 3. The memory control device 1 includes a clock generation circuit 11, CPUs 12 and 13, bus controllers 14 and 15, an inverter 16, memory controllers 17 and 18, and a selector 19. Further, the memory control device 1 is provided with individual terminal groups 20, 21, 23, 24 and a common terminal group 22. The memory control device 1 is formed as an LSI on the same semiconductor chip, and is used for a DVD (digital video disk) recorder, for example.

  The clock generation circuit generates a system clock signal SYSCLK having a constant period. The CPUs 12 and 13 instruct the operations of the corresponding DDR-SDRAM units 2 and 3, respectively. However, the CPUs 12 and 13 may be provided outside the memory control device 1. A single CPU may be configured to instruct the operations of the two DDR-SDRAM units 2 and 3. Further, an initiator other than the CPU (subject that activates access to the memory) may be used.

  The bus controller 14 is provided between the CPU 12 and the memory controller 17 and has a function of arbitrating the bus right. The bus controller 15 is provided between the CPU 13 and the memory controller 18 and has a function of arbitrating the bus right. The inverter 16 receives the system clock signal SYSCLK from the clock generation circuit 11 and outputs a signal SYSCLKN whose logic level is inverted.

  The memory controller 17 operates in synchronization with the system clock signal SYSCLK from the clock generation circuit 17 and controls the operation of the corresponding DDR-SDRAM unit 2 based on an instruction from the CPU 12 to exchange data signals. The memory controller 17 supplies the clock signals CK # 1, / CK # 1 and the clock enable signal CKE # 1 to the DDR-SDRAM unit 2 through the individual terminal group 20. The memory controller 17 also includes a chip select signal / CS # 1, a bank address signal BA # 1 [1: 0], an address signal A # 1 [13: 0], a row address strobe signal / RAS # 1, a column address strobe. Signal / CAS # 1 and write enable signal / WE # 1 are applied to selector 19. Further, the memory controller 17 provides the data signal DQ # 1 [7: 0], the data mask signal DM # 1 and the data strobe signal DQS # 1 to the DDR-SDRAM unit 2 through the individual terminal group 21.

  The memory controller 18 operates in synchronization with the output signal / SYSCLK of the inverter 16 and controls the operation of the corresponding DDR-SDRAM unit 3 based on an instruction from the CPU 13 to exchange data signals. The memory controller 18 provides the clock signals CK # 2, / CK # 2 and the clock enable signal CKE # 2 to the DDR-SDRAM unit 3 through the individual terminal group 23. The memory controller 18 also includes a chip select signal / CS # 2, a bank address signal BA # 2 [1: 0], an address signal A # 2 [13: 0], a row address strobe signal / RAS # 2, a column address strobe. Signal / CAS # 2 and write enable signal / WE # 2 are applied to selector 19. In addition, the memory controller 18 provides the data signal DQ # 2 [7: 0], the data mask signal DM # 2, and the data strobe signal DQS # 2 to the DDR-SDRAM unit 3 through the individual terminal group 24.

  The memory controllers 17 and 18 operate independently of each other and independently control the corresponding DDR-SDRAM units. Each of the DDR-SDRAM units 2 and 3 includes one or more DDR-SDRAMs.

  Selector 19 selectively outputs the signals received from memory controllers 17 and 18 in response to system clock signal SYSCLK from clock generation circuit 11. Specifically, when system clock signal SYSCLK is at “L” level (“0”), signals received from memory controller 17 (chip select signal / CS # 1, bank address signal BA # 1 [1: 0], Address signal A # 1 [13: 0], row address strobe signal / RAS # 1, column address strobe signal / CAS # 1 and write enable signal / WE # 1) are selected, and system clock signal SYSCLK is at "H" level. In the case of (“1”), signals received from the memory controller 18 (chip select signal / CS # 2, bank address signal BA # 2 [1: 0], address signal A # 2 [13: 0], row address strobe Signal / RAS # 2, column address strobe signal / CAS # 2, and write enable signal / WE # ) Is selected. Then, the selected signal is used as a common control signal (chip select signal / CS, bank address signal BA [1: 0], address signal A [13: 0], row address strobe signal / RAS, column address strobe signal / CAS, and write signal. The enable signal / WE) is applied to the DDR-SDRAM units 2 and 3 through the common terminal group 22.

  The individual terminal group 20 includes three individual terminals corresponding to the clock signals CK # 1, / CK # 1 and the clock enable signal CKE # 1. The individual terminal group 21 includes 10 individual terminals corresponding to the data signal DQ # 1 [7: 0], the data mask signal DM # 1, and the data strobe signal DQS # 1.

  The common terminal group 22 includes common control signals (chip select signal / CS, bank address signal BA [1: 0], address signal A [13: 0], row address strobe signal / RAS, column address strobe signal / CAS, and write signal. 20 common terminals corresponding to the enable signal / WE).

  The individual terminal group 23 includes three individual terminals corresponding to the clock signals CK # 2 and / CK # 2 and the clock enable signal CKE # 2. The individual terminal group 24 includes ten individual terminals corresponding to the common control signal (data signal DQ # 2 [7: 0], data mask signal DM # 2, and data strobe signal DQS # 2.

  The data width of the DDR-SDRAM units 2 and 3 (the amount of data handled by one reading and writing) is 8 bits. However, the number of bits of the data width, the memory capacity, and the speed grade of the DDR-SDRAM units 2 and 3 may be different from each other.

  FIG. 2 is a time chart for explaining the operation of the memory control device 1 shown in FIG. Referring to FIG. 2, clock signals CK # 1 and / CK # 2 are both in phase with system clock signal SYSCLK. The clock signals / CK # 1 and CK # 2 are both in phase opposite to the system clock signal SYSCLK. The clock signals CK # 1 and / CK # 1 are differential clock signals that are opposite to each other, and the clock signals CK # 2 and / CK # 2 are differential clock signals that are opposite to each other. The memory controllers 17 and 18 operate at a timing at which the phases are shifted from each other by 180 degrees.

  Specifically, the memory controller 17 operates in synchronization with the system clock signal SYSCLK, and changes at the timing of time t0 to t8 (changes in response to the rising edge of the system clock signal SYSCLK). # 1, bank address signal BA # 1 [1: 0], address signal A # 1 [13: 0], row address strobe signal / RAS # 1, column address strobe signal / CAS # 1 and write enable signal / WE # 1 is output.

  On the other hand, the memory controller 18 operates in synchronization with the output signal / SYSCLK (inverted signal of the system clock SYSCLK) of the inverter 16 and changes at the timing from time t10 to t19 (in response to the rising edge of the system clock signal / SYSCLK) Chip select signal / CS # 2, bank address signal BA # 2 [1: 0], address signal A # 2 [13: 0], row address strobe signal / RAS # 2, column address strobe signal / CAS # 2 and write enable signal / WE # 2 are output.

  In the selector 19, when the system clock signal SYSCLK is at "H" level ("1"), the output signal of the memory controller 18 (chip select signal / CS # 2, bank address signal BA # 2 [1: 0], address signal) A # 2 [13: 0], row address strobe signal / RAS # 2, column address strobe signal / CAS # 2 and write enable signal / WE # 2) are selected and common control signals (chip select signal / CS, Bank address signal BA [1: 0], address signal A [13: 0], row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE). On the other hand, when the system clock signal SYSCLK is at “L” level (“0”), the output signal of the memory controller 17 (chip select signal / CS # 1, bank address signal BA # 1 [1: 0], address signal A # 1 [13: 0], row address strobe signal / RAS # 1, column address strobe signal / CAS # 1 and write enable signal / WE # 1 are selected, and a common control signal (chip select signal / CS, bank address) is selected. Signal BA [1: 0], address signal A [13: 0], row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE).

  Although the signal delay is not expressed in FIG. 2, the output signals CK # 1, / CK # 1, CKE # 1, / CS # 1, BA # 1 [1: 0], A # 1 [13: 0], / RAS # 1, / CAS # 1, / WE # 1, DQ # 1 [7: 0], DM # 1, DQS # 1 are from the rising edge of the system clock signal SYSCLK. Also changes with a predetermined delay time. Further, the output signals CK # 2, / CK # 2, CKE # 2, / CS # 2, BA # 2 [1: 0], A # 2 [13: 0], / RAS # 2, / of the memory controller 18 CAS # 2, / WE # 2, DQ # 2 [7: 0], DM # 2, DQS # 2 change with a predetermined delay time from the falling edge of the system clock signal SYSCLK.

  Therefore, if the clock skew is within an appropriate range, the output signals CK # 1, / CK # 1, CKE # 1, and the output of the memory controller 17 during the period when the system clock signal SYSCLK is at the “L” level (“0”). / CS # 1, BA # 1 [1: 0], A # 1 [13: 0], / RAS # 1, / CAS # 1, / WE # 1, DQ # 1 [7: 0], DM # 1 , DQS # 1 does not change. Further, the output signals CK # 2, / CK # 2, CKE # 2, / CS # 2, BA # 2 [1: [1] of the memory controller 18 during the period when the system clock signal SYSCLK is at the “H” level (“1”). 0], A # 2 [13: 0], / RAS # 2, / CAS # 2, / WE # 2, DQ # 2 [7: 0], DM # 2, DQS # 2 do not change. Therefore, the common control signals / CS, BA [1: 0], A [13: 0], / RAS, / CAS, / WE are unstable near the rising edge and falling edge of the system clock signal SYSCLK. The risk of becoming is avoided.

  In DDR-SDRAM unit 2, when clock signal CK # 1 rises from "L" level to "H" level and clock signal / CK # 1 falls from "H" level to "L" level, these The point where the two signals intersect is considered the rising edge of the clock signal. That is, the command is taken in at the timing from time t0 to time t8 (timing of the rising edge of system clock signal SYSCLK).

  In DDR-SDRAM unit 3, when clock signal CK # 2 rises from "L" level to "H" level and clock signal / CK # 2 falls from "H" level to "L" level, these The point where the two signals intersect is considered the rising edge of the clock signal. That is, the command is fetched at the timing from time t10 to t19 (timing of the rising edge of system clock signal / SYSCLK).

  Therefore, the DDR-SDRAM unit 2 outputs the output signals CK # 2, / CK # 2, CKE # 2, / CS # 2, BA # 2 [1: 0], A # 2 [13: 0] from the memory controller 18. , / RAS # 2, / CAS # 2, / WE # 2, DQ # 2 [7: 0], DM # 2, DQS # 2, and without being affected by the output signal CK # 1, / of the memory controller 17 CK # 1, CKE # 1, / CS # 1, BA # 1 [1: 0], A # 1 [13: 0], / RAS # 1, / CAS # 1, / WE # 1, DQ # 1 [ 7: 0], DM # 1, DQS # 1 can be sampled.

  The DDR-SDRAM unit 3 outputs the output signals CK # 1, / CK # 1, CKE # 1, / CS # 1, BA # 1 [1: 0], A # 1 [13: 0] from the memory controller 17. , / RAS # 1, / CAS # 1, / WE # 1, DQ # 1 [7: 0], DM # 1, DQS # 1 and the output signal CK # 2, / CK # 2, CKE # 2, / CS # 2, BA # 2 [1: 0], A # 2 [13: 0], / RAS # 2, / CAS # 2, / WE # 2, DQ # 2 [ 7: 0], DM # 2, DQS # 2.

  FIG. 3 is a time chart for explaining the operation of the memory control device 1 in more detail. With reference to FIG. 3, the operation of the memory controller 17 will be described first.

  During the period from time t1 to time t2, the memory controller 17 activates the row address strobe signal / RAS # 1 and sets the row address RA # 1 (act command ACT) as the address signal A # 1 [13: 0]. ) Is output.

  Next, in a period from time t2 to time t4 after one clock cycle from time t2, the memory controller 17 sets the column address strobe signal / CAS # 1 to the activation level and sets the address signal A # 1 [13: 0. ], The first column address CA1 # 1 (read command RD) is output. Subsequently, in a period from time t4 to time t5 after one clock cycle from time t4, the memory controller 17 sets the column address strobe signal / CAS # 1 to the activation level and sets the address signal A # 1 [13: 0. ], The second column address CA2 # 1 (read command RD) is output.

  The memory controller 17 continuously outputs the data signal DQ # 1 for four data from time t6, which is two clock cycles after giving the first column address CA1 # 1 (time t4). Subsequently, after the second column address CA2 # 1 is applied (time t6), the data signal DQ # 1 is continuously output for four data from time t8 after two clock cycles. However, it is assumed that CL (CAS latency) of the memory controller 17 is set to 2 and BL (burst length) is set to 4.

  Next, the operation of the memory controller 18 will be described. In the period from time t13 to time t14, the memory controller 18 sets the row address strobe signal / RAS # 2 to the activation level and sets the row address RA # 2 (act command ACT) as the address signal A # 2 [13: 0]. ) Is output.

  Next, during a period from time t15 to time t16 one clock cycle after time t14, the memory controller 18 sets the column address strobe signal / CAS # 2 to the activation level and sets the address signal A # 2 [13: 0. ], The first column address CA1 # 2 (read command RD) is output. Subsequently, in a period from time t16 to time t17 after one clock cycle from time t16, the memory controller 18 sets the column address strobe signal / CAS # 2 to the activation level and sets the address signal A # 2 [13: 0. ], The second column address CA2 # 2 (read command RD) is output.

  Then, the memory controller 18 continuously outputs the data signal DQ # 2 for four data from time t18, which is two clock cycles after giving the first column address CA1 # 2 (time t16). Subsequently, after the second column address CA2 # 2 is applied (time t18), the data signal DQ # 1 is continuously output for four data from time t20 after two clock cycles (not shown). However, it is assumed that CL (CAS latency) of the memory controller 18 is set to 2 and BL (burst length) is set to 4.

  Next, the operation of the selector 19 will be described. When the system clock signal SYSCLK is at “L” level (“0”), the output signals of the memory controller 17 (address signal A # 1 [13: 0], row address strobe signal / RAS # 1, column address strobe signal / CAS). # 1) is selected and output as a common control signal (address signal A [13: 0], row address strobe signal / RAS, column address strobe signal / CAS). When the system clock signal SYSCLK is at “H” level (“1”), the output signal of the memory controller 18 (address signal A # 2 [13: 0], row address strobe signal / RAS # 2, column address strobe signal) / CAS # 2) is selected and output as a common control signal (address signal A [13: 0], row address strobe signal / RAS, column address strobe signal / CAS).

  That is, the row address strobe signal / RAS is set to the activation level in the period from time t12 to time t2 and in the period from time t3 to time t14. Further, the column address strobe signal / CAS is set to the activation level in the period from time t14 to time t4, in the period from time t5 to time 6, and in the period from time t7 to time t18. The address signal A [13: 0] is set to the row address RA # 1 during the period from the time t12 to the time t2, and is set to the row address RA # 2 during the period from the time t3 to the time t14. The period from t4 is column dress CA1 # 1, the period from time t5 to time t16 is column dress CA1 # 2, the period from time t16 to time t6 is column dress CA2 # 1, and from time t17 The period up to time t18 is set to column dress CA2 # 2.

  In DDR-SDRAM unit 2, a command is taken in at the rising edge of clock signal CK # 1. That is, commands NOP (No Operation: do nothing), NOP, ACT, NOP, RD, NOP, RD, NOP, NOP, NOP are sampled at the timing of time t0 to t9. Therefore, it can be seen that the command output from the memory controller 17 is taken into the DDR-SDRAM unit 2.

  In DDR-SDRAM portion 3, a command is taken in at the rising edge of clock signal CK # 2. That is, the commands NOP, NOP, NOP, NOP, ACT, NOP, RD, NOP, RD, NOP, NOP are sampled at the timing from time t10 to t20. Therefore, it can be seen that the command output from the memory controller 18 is taken into the DDR-SDRAM unit 3.

  In this example, the command sequences output from the memory controllers 17 and 18 are the same, but the command sequence output from the memory controller 17 and the command sequence output from the memory controller 18 are arbitrary.

  As described above, in this embodiment, the selector 19 that performs the selection operation according to the system clock signal SYSCLK is provided, and the common control signal (chip select signal / CS, bank address signal BA [1: 0], address Signal A [13: 0], row address strobe signal / RAS, column address strobe signal / CAS and write enable signal / WE) are applied to DDR-SDRAM units 2 and 3 via common terminal group 22. Therefore, the DDR-SDRAM units 2 and 3 can share the 20 common terminals constituting the common terminal group 22 without adversely affecting the control of the DDR-SDRAM units 2 and 3 by the memory controllers 17 and 18. it can. That is, the number of terminals is reduced by 20 compared to the case where the DDR-SDRAM units 2 and 3 do not share terminals. As a result, the area and cost of the memory control device formed as an LSI can be reduced.

  In this embodiment, the chip select signal / CS, the bank address signal BA [1: 0], the address signal A [13: 0], the row address strobe signal / RAS, the column address strobe signal / CAS, and the write The enable signal / WE is used as a common control signal. Among the output signals of the memory controllers 17 and 18, signals that can be shared are signals that change in units of one clock cycle (condition 1), and signals other than before and after the clock edge sampled by the corresponding DDR-SDRAM unit. The signal must not be a problem even if the level changes (condition 2).

  Chip select signals / CS # 1, / CS # 2, bank address signals BA # 1 [1: 0], BA # 2 [1: 0], address signals A # 1 [13: 0], A # 2 [13 : 0], the row address strobe signals / RAS # 1, / RAS # 2, the column address strobe signals / CAS # 1, / CAS # 2 and the write enable signals / WE # 1, / WE # 2 , 2 is satisfied.

  On the other hand, the clock signals CK # 1, CK # 2, / CK # 1, / CK # 2 do not satisfy the above condition 1 because they change twice within one clock cycle. The clock enable signals CKE # 1 and CKE # 2 are limited in the setup time and hold time, and need to keep the “H” level or “L” level continuously over a plurality of clock cycles. 2 is not satisfied. Data signals DQ # 1 [7: 0], DQ # 2 [7: 0], data mask signals DM # 1, DM # 2, and data strobe signals DQS # 1, DQS # 2 are twice in one clock cycle. Since it changes, the above condition 1 is not satisfied.

  In the conventional memory controller disclosed in Patent Document 1, the SDRAM controller unit and the SDRAM controller unit receive an instruction from a single CPU, and the multiplexer has two controller units according to the address to be accessed. The connection relationship between each terminal and the external terminal is changed. For this reason, the two controller units cannot operate in parallel within the same clock cycle.

  On the other hand, in this embodiment, the selector 19 selects the output signal of the memory controller 17 when the system clock signal SYSCLK is at “L” level, and the memory controller 17 when the system clock signal SYSCLK is at “H” level. 18 output signals are selected. That is, the two memory controllers 17 and 18 can operate in parallel within the same clock cycle. For this reason, the two memory controllers 17 and 18 can operate independently of each other, and are not affected by each other's operation. Therefore, the present invention is also applicable to the case where the two CPUs 12 and 13 independently access the corresponding DDR-SDRAM unit via the corresponding memory controller.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 is a block diagram showing a schematic configuration of a memory control device incorporating a plurality of memory controllers according to an embodiment of the present invention. FIG. 3 is a time chart for explaining the operation of the memory control device shown in FIG. 1. It is a time chart for explaining operation of a memory control device in detail.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Memory control apparatus, 2,3 DDR-SDRAM part, 11 Clock generation circuit, 12, 13 CPU, 14, 15 Bus controller, 16 Inverter, 17, 18 Memory controller, 19 Selector, 20, 21, 23, 24 Individual terminal Group, 22 Common terminal group.

Claims (3)

A memory control device for independently controlling first and second synchronous memory units for inputting and outputting data signals in response to both a first level change and a second level change of a clock signal,
A first clock signal that operates in synchronization with a system clock signal of a fixed period, has the same phase as the system clock signal, and a first control signal that changes in response to a first level change of the system clock signal; A first memory controller for exchanging data signals with the first synchronous memory unit,
It operates in synchronization with the inverted signal of the system clock signal and changes in response to a second clock signal having the same phase as the inverted signal of the system clock signal and a first level change of the inverted signal of the system clock signal And a second memory controller for exchanging data signals with the second synchronous memory unit, and receiving the first and second control signals, the system clock signal being The first control signal is selected when the first logic level is selected, the second control signal is selected when the system clock signal is the second logic level, and the selected signal is selected as the first and second signals. A memory control device comprising a selector that outputs to two synchronous memory units.   The first and second control signals each include at least one of a chip select signal, a bank address signal, an address signal, a row address strobe signal, a column address strobe signal, and a write enable signal. The memory control device according to 1.   The memory control device according to claim 1, wherein the memory control device is formed as an integrated circuit on the same semiconductor chip.

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